From: Kalyani Chidambaram Vaidyanathan Date: Mon, 24 Apr 2023 20:56:12 +0000 (-0700) Subject: fix(tegra210): mark bits [23:17] as zero for Fast SMCs X-Git-Tag: baikal/aarch64/sdk5.10~1^2~9^2 X-Git-Url: https://git.baikalelectronics.ru/sdk/?a=commitdiff_plain;h=cb6c8efc4f2dd951b2b51801a12ba1755d49fe79;p=arm-tf.git fix(tegra210): mark bits [23:17] as zero for Fast SMCs Per SMCCC documentation, bits [23:17] must be zero for Fast SMCs. Other values are reserved for future use. Ensure that these bits are zeroes for TEGRA_SIP_PMC_COMMANDS. Commit f8a35797 introduced a check to return error if these bits are not zero, thus breaking Tegra210 platforms. This patch fixes the anomaly. Change-Id: I19edc3b33c999a6fee6b86184233fba146316466 Signed-off-by: Kalyani Chidambaram Vaidyanathan Signed-off-by: Varun Wadekar --- diff --git a/plat/nvidia/tegra/soc/t210/plat_sip_calls.c b/plat/nvidia/tegra/soc/t210/plat_sip_calls.c index 93d12832e..f3ebd4bb9 100644 --- a/plat/nvidia/tegra/soc/t210/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t210/plat_sip_calls.c @@ -33,8 +33,7 @@ /******************************************************************************* * Tegra210 SiP SMCs ******************************************************************************/ -#define TEGRA_SIP_PMC_COMMANDS_LEGACY U(0xC2FEFE00) -#define TEGRA_SIP_PMC_COMMANDS U(0xC2FFFE00) +#define TEGRA_SIP_PMC_COMMANDS U(0xC200FE00) /******************************************************************************* * This function is responsible for handling all T210 SiP calls @@ -55,10 +54,12 @@ int plat_sip_handler(uint32_t smc_fid, if (!ns) SMC_RET1(handle, SMC_UNK); - if ((smc_fid == TEGRA_SIP_PMC_COMMANDS) || (smc_fid == TEGRA_SIP_PMC_COMMANDS_LEGACY)) { + if (smc_fid == TEGRA_SIP_PMC_COMMANDS) { + /* check the address is within PMC range and is 4byte aligned */ - if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3)) + if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3)) { return -EINVAL; + } switch (x2) { /* Black listed PMC registers */