From: Daniel Vetter Date: Thu, 7 Jan 2021 11:20:28 +0000 (+0100) Subject: Merge tag 'drm-intel-next-2021-01-04' of git://anongit.freedesktop.org/drm/drm-intel... X-Git-Url: https://git.baikalelectronics.ru/sdk/?a=commitdiff_plain;h=ca765c731ebd62231ec096a121ca11a39a51a07b;p=kernel.git Merge tag 'drm-intel-next-2021-01-04' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Display hotplug fix for gen2/gen3 (Chris) - Remove trailing semicolon (Tom) - Suppress display warnings for old ifwi presend on our CI (Chris) - OA/Perf related workaround (Lionel) - Replace I915_READ/WRITE per new uncore and display read/write functions (Jani) - PSR improvements (Jose) - HDR and other color changes on LSPCON (Uma, Ville) - FBC fixes for TGL (Uma) - Record plane update times for debugging (Chris) - Refactor panel backlight control functions (Dave) - Display power improvements (Imre) - Add VRR register definition (Manasi) - Atomic modeset improvements for bigjoiner pipes (Ville) - Switch off the scanout during driver unregister (Chris) - Clean-up DP's FEW enable (Manasi) - Fix VDSCP slice count (Manasi) - Fix and clean up around rc_model_size for DSC (Jani) - Remove Type-C noisy debug warn message (Sean) - Display HPD code clean-up (Ville) - Refactor Intel Display (Dave) - Start adding support for Intel's eDP backlight controls (Lyude) Signed-off-by: Daniel Vetter From: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20210104211018.GA1094707@intel.com --- ca765c731ebd62231ec096a121ca11a39a51a07b diff --cc drivers/gpu/drm/i915/display/intel_display_types.h index a780ced06f121,de2371eff3d47..1067bd073c955 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@@ -1438,12 -1451,13 +1457,15 @@@ struct intel_dp struct { int min_tmds_clock, max_tmds_clock; int max_dotclock; + int pcon_max_frl_bw; u8 max_bpc; bool ycbcr_444_to_420; + bool rgb_to_ycbcr; } dfp; + /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ + struct pm_qos_request pm_qos; + /* Display stream compression testing */ bool force_dsc_en; diff --cc drivers/gpu/drm/i915/intel_pm.c index a20b5051f18c1,57db548673dd4..bbc73df7f753b --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@@ -7103,10 -7103,24 +7103,10 @@@ static void icl_init_clock_gating(struc 0, CNL_DELAY_PMRSP); } -static void gen12_init_clock_gating(struct drm_i915_private *i915) -{ - unsigned int i; - - /* This is not a WA. Enable VD HCP & MFX_ENC powergate */ - for (i = 0; i < I915_MAX_VCS; i++) - if (HAS_ENGINE(&i915->gt, _VCS(i))) - intel_uncore_rmw(&i915->uncore, POWERGATE_ENABLE, 0, - VDN_HCP_POWERGATE_ENABLE(i) | - VDN_MFX_POWERGATE_ENABLE(i)); -} - static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) { - gen12_init_clock_gating(dev_priv); - /* Wa_1409120013:tgl */ - I915_WRITE(ILK_DPFC_CHICKEN, + intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL); /* Wa_1409825376:tgl (pre-prod)*/ @@@ -7121,9 -7135,11 +7121,9 @@@ static void dg1_init_clock_gating(struct drm_i915_private *dev_priv) { - gen12_init_clock_gating(dev_priv); - /* Wa_1409836686:dg1[a0] */ if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0)) - I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) | + intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) | DPT_GATING_DIS); }