From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Tue, 22 Dec 2020 21:34:27 +0000 (-0800)
Subject: Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux
X-Git-Url: https://git.baikalelectronics.ru/sdk/?a=commitdiff_plain;h=c45647f9f562b52915b43b6bb447827cebf511bd;p=kernel.git

Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux

Pull ARM updates from Russell King:

 - Rework phys/virt translation

 - Add KASan support

 - Move DT out of linear map region

 - Use more PC-relative addressing in assembly

 - Remove FP emulation handling while in kernel mode

 - Link with '-z norelro'

 - remove old check for GCC <= 4.2 in ARM unwinder code

 - disable big endian if using clang's linker

* tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (46 commits)
  ARM: 9027/1: head.S: explicitly map DT even if it lives in the first physical section
  ARM: 9038/1: Link with '-z norelro'
  ARM: 9037/1: uncompress: Add OF_DT_MAGIC macro
  ARM: 9036/1: uncompress: Fix dbgadtb size parameter name
  ARM: 9035/1: uncompress: Add be32tocpu macro
  ARM: 9033/1: arm/smp: Drop the macro S(x,s)
  ARM: 9032/1: arm/mm: Convert PUD level pgtable helper macros into functions
  ARM: 9031/1: hyp-stub: remove unused .L__boot_cpu_mode_offset symbol
  ARM: 9044/1: vfp: use undef hook for VFP support detection
  ARM: 9034/1: __div64_32(): straighten up inline asm constraints
  ARM: 9030/1: entry: omit FP emulation for UND exceptions taken in kernel mode
  ARM: 9029/1: Make iwmmxt.S support Clang's integrated assembler
  ARM: 9028/1: disable KASAN in call stack capturing routines
  ARM: 9026/1: unwind: remove old check for GCC <= 4.2
  ARM: 9025/1: Kconfig: CPU_BIG_ENDIAN depends on !LD_IS_LLD
  ARM: 9024/1: Drop useless cast of "u64" to "long long"
  ARM: 9023/1: Spelling s/mmeory/memory/
  ARM: 9022/1: Change arch/arm/lib/mem*.S to use WEAK instead of .weak
  ARM: kvm: replace open coded VA->PA calculations with adr_l call
  ARM: head.S: use PC relative insn sequence to calculate PHYS_OFFSET
  ...
---

c45647f9f562b52915b43b6bb447827cebf511bd
diff --cc arch/arm/Kconfig
index b8ade91281bc5,b2bf019dcefa6..138248999df74
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@@ -68,8 -67,8 +68,9 @@@ config AR
  	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
+ 	select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
  	select HAVE_ARCH_MMAP_RND_BITS if MMU
 +	select HAVE_ARCH_PFN_VALID
  	select HAVE_ARCH_SECCOMP
  	select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
  	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
diff --cc arch/arm/kernel/entry-common.S
index 77d16390a5245,fee279e28a72e..e0d7833a1827e
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@@ -50,10 -50,11 +50,11 @@@ __ret_fast_syscall
   UNWIND(.cantunwind	)
  	disable_irq_notrace			@ disable interrupts
  	ldr	r2, [tsk, #TI_ADDR_LIMIT]
- 	cmp	r2, #TASK_SIZE
+ 	ldr	r1, =TASK_SIZE
+ 	cmp	r2, r1
  	blne	addr_limit_check_failed
  	ldr	r1, [tsk, #TI_FLAGS]		@ re-check for syscall tracing
 -	tst	r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK
 +	movs	r1, r1, lsl #16
  	bne	fast_work_pending
  
  
@@@ -87,10 -88,11 +88,11 @@@ __ret_fast_syscall
  #endif
  	disable_irq_notrace			@ disable interrupts
  	ldr	r2, [tsk, #TI_ADDR_LIMIT]
- 	cmp	r2, #TASK_SIZE
+ 	ldr     r1, =TASK_SIZE
+ 	cmp     r2, r1
  	blne	addr_limit_check_failed
  	ldr	r1, [tsk, #TI_FLAGS]		@ re-check for syscall tracing
 -	tst	r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK
 +	movs	r1, r1, lsl #16
  	beq	no_work_pending
   UNWIND(.fnend		)
  ENDPROC(ret_fast_syscall)
@@@ -128,10 -130,11 +130,11 @@@ ret_slow_syscall
  	disable_irq_notrace			@ disable interrupts
  ENTRY(ret_to_user_from_irq)
  	ldr	r2, [tsk, #TI_ADDR_LIMIT]
- 	cmp	r2, #TASK_SIZE
+ 	ldr     r1, =TASK_SIZE
+ 	cmp	r2, r1
  	blne	addr_limit_check_failed
  	ldr	r1, [tsk, #TI_FLAGS]
 -	tst	r1, #_TIF_WORK_MASK
 +	movs	r1, r1, lsl #16
  	bne	slow_work_pending
  no_work_pending:
  	asm_trace_hardirqs_on save = 0