From: Tien Fong Chee <tien.fong.chee@intel.com>
Date: Tue, 7 May 2019 09:42:25 +0000 (+0800)
Subject: ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK
X-Git-Tag: baikal/mips/sdk5.9~976^2~14
X-Git-Url: https://git.baikalelectronics.ru/sdk/?a=commitdiff_plain;h=b98c77340a4f8a102ef2fde19db5d5a9140731da;p=uboot.git

ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK

Add default fitImage file bundling FPGA bitstreams for Arria10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---

diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its b/board/altera/arria10-socdk/fit_spl_fpga.its
new file mode 100644
index 0000000000..adae997213
--- /dev/null
+++ b/board/altera/arria10-socdk/fit_spl_fpga.its
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+ /*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	description = "FIT image with FPGA bistream";
+	#address-cells = <1>;
+
+	images {
+		fpga-periph-1 {
+			description = "FPGA peripheral bitstream";
+			data = /incbin/("../../../ghrd_10as066n2.periph.rbf");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+		};
+
+		fpga-core-1 {
+			description = "FPGA core bitstream";
+			data = /incbin/("../../../ghrd_10as066n2.core.rbf");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "config-1";
+		config-1 {
+			description = "Boot with FPGA early IO release config";
+			fpga = "fpga-periph-1", "fpga-core-1";
+		};
+	};
+};