From: Marc Kleine-Budde <mkl@pengutronix.de>
Date: Mon, 6 Jul 2020 14:34:43 +0000 (+0200)
Subject: spi: spi-sun6i: sun6i_spi_transfer_one(): enable RF_RDY interrupt only if needed
X-Git-Tag: baikal/mips/sdk5.9~12865^2~60^2
X-Git-Url: https://git.baikalelectronics.ru/sdk/?a=commitdiff_plain;h=ad9d976e6e26eb4b4148ab54c4b490c2a86ac5b2;p=kernel.git

spi: spi-sun6i: sun6i_spi_transfer_one(): enable RF_RDY interrupt only if needed

In sun6i_spi_transfer_one() the RX FIFO Ready (SUN6I_INT_CTL_RF_RDY) is
unconditionally enabled.

A RX interrupt is only needed, if more data than fits into the FIFO is going to
be received during this transfer. As the RX-FIFO is drained during transfer
complete interrupt, enable the RX FIFO Ready interrupt only if the data doesn't
fit into the FIFO.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20200706143443.9855-11-mkl@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
---

diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
index bba9843c40c50..19238e1b76b44 100644
--- a/drivers/spi/spi-sun6i.c
+++ b/drivers/spi/spi-sun6i.c
@@ -190,7 +190,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
 	unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;
 	unsigned int start, end, tx_time;
 	unsigned int trig_level;
-	unsigned int tx_len = 0;
+	unsigned int tx_len = 0, rx_len = 0;
 	int ret = 0;
 	u32 reg;
 
@@ -245,10 +245,12 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
 	 * If it's a TX only transfer, we don't want to fill the RX
 	 * FIFO with bogus data
 	 */
-	if (sspi->rx_buf)
+	if (sspi->rx_buf) {
 		reg &= ~SUN6I_TFR_CTL_DHB;
-	else
+		rx_len = tfr->len;
+	} else {
 		reg |= SUN6I_TFR_CTL_DHB;
+	}
 
 	/* We want to control the chip select manually */
 	reg |= SUN6I_TFR_CTL_CS_MANUAL;
@@ -302,8 +304,10 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
 	sun6i_spi_fill_fifo(sspi);
 
 	/* Enable the interrupts */
-	reg = SUN6I_INT_CTL_TC | SUN6I_INT_CTL_RF_RDY;
+	reg = SUN6I_INT_CTL_TC;
 
+	if (rx_len > sspi->fifo_depth)
+		reg |= SUN6I_INT_CTL_RF_RDY;
 	if (tx_len > sspi->fifo_depth)
 		reg |= SUN6I_INT_CTL_TF_ERQ;