From: Ankit Nautiyal Date: Mon, 8 Feb 2021 05:55:54 +0000 (+0530) Subject: drm/i915: Fix HAS_LSPCON macro for platforms between GEN9 and GEN10 X-Git-Url: https://git.baikalelectronics.ru/sdk/?a=commitdiff_plain;h=81637a6ede89b95b6ea7b2f8c594676881110890;p=kernel.git drm/i915: Fix HAS_LSPCON macro for platforms between GEN9 and GEN10 Legacy LSPCON chip from MCA and Parade is only used for platforms between GEN9 and GEN10. Fixing the HAS_LSPCON macro to reflect the same. Signed-off-by: Ankit Nautiyal Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20210208055554.24357-1-ankit.k.nautiyal@intel.com --- diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 017208ff8df41..d8f418eaeb782 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1722,7 +1722,7 @@ tgl_stepping_get(struct drm_i915_private *dev_priv) #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) -#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) +#define HAS_LSPCON(dev_priv) (IS_GEN_RANGE(dev_priv, 9, 10)) /* DPF == dynamic parity feature */ #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)