From: Jani Nikula <jani.nikula@intel.com>
Date: Tue, 2 Feb 2021 10:50:04 +0000 (+0200)
Subject: Merge tag 'topic/adl-s-enabling-2021-02-01-1' of git://anongit.freedesktop.org/drm... 
X-Git-Url: https://git.baikalelectronics.ru/sdk/?a=commitdiff_plain;h=29e92559013360c43886e7fb229ed12fd96f46ef;p=kernel.git

Merge tag 'topic/adl-s-enabling-2021-02-01-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-intel-next

Driver Changes:
  - Add basic support for Alder Lake S, to be shared between
  drm-intel-next and drm-intel-gt-next

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

# Conflicts:
#	drivers/gpu/drm/i915/i915_drv.h
From: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210202025620.2212559-1-lucas.demarchi@intel.com
---

29e92559013360c43886e7fb229ed12fd96f46ef
diff --cc drivers/gpu/drm/i915/i915_drv.h
index 574f3575879df,548344ef1e8b8..2a4666f9d9d02
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -1755,11 -1785,9 +1778,14 @@@ tgl_stepping_get(struct drm_i915_privat
  #define INTEL_DISPLAY_ENABLED(dev_priv) \
  	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
  
 +static inline bool run_as_guest(void)
 +{
 +	return !hypervisor_is_type(X86_HYPER_NATIVE);
 +}
 +
+ #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
+ 					      IS_ALDERLAKE_S(dev_priv))
+ 
  static inline bool intel_vtd_active(void)
  {
  #ifdef CONFIG_INTEL_IOMMU
diff --cc drivers/gpu/drm/i915/intel_pm.c
index 0c3e63f27c29d,319acca2630b9..c58e5077590df
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@@ -7065,14 -7103,14 +7065,14 @@@ static void icl_init_clock_gating(struc
  			 0, CNL_DELAY_PMRSP);
  }
  
 -static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 +static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
  {
 -	/* Wa_1409120013:tgl */
 +	/* Wa_1409120013:tgl,rkl,adl_s,dg1 */
  	intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
 -		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 +			   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
  
  	/* Wa_1409825376:tgl (pre-prod)*/
- 	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
+ 	if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
  			   TGL_VRH_GATING_DIS);