From: Ye Li Date: Tue, 31 Jan 2023 08:42:21 +0000 (+0800) Subject: imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers X-Git-Tag: baikal/mips/sdk6.2~4^2~3^2~175^2~16^2~84 X-Git-Url: https://git.baikalelectronics.ru/sdk/?a=commitdiff_plain;h=1658137da304be8409cf64082585c8dfb774ad8d;p=uboot.git imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers At present, in cgc1_pll3_init we don't set the pll3pfd div values, just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2 to 1 and pfd2div1 to 3. This finally causes some clocks' rate decreased, for example USDHC. So clear the PLL3DIV_PFD dividers to get correct rate. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index d240abaee4..104109e693 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -169,6 +169,9 @@ void cgc1_pll3_init(ulong freq) while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30))) ; + clrbits_le32(&cgc1_regs->pll3div_pfd0, 0x3f3f3f3f); + clrbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f); + clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7)); clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15)); clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23));