+++ /dev/null
-bm1000_bl1_logo_v4.c
\ No newline at end of file
+++ /dev/null
-/*
- * Copyright (c) 2020, Baikal Electronics, JSC. All rights reserved.
- *
- * Author: Pavel Parkhomenko <pavel.parkhomenko@baikalelectronics.ru>
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/*
- * To change a logo, replace array contents below with a BMP file dump.
- * Source BMP file have to be of 16-bpp color format (RGB565).
- * Optimal size is 72x72 pixels (or 64x84 pixels for wide displays).
- */
-
-#if !DEBUG
-const unsigned char bl1_logo[] = {
- 0x42, 0x4d, 0xc6, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x00,
- 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x48, 0x00,
- 0x00, 0x00, 0x01, 0x00, 0x10, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, 0x28,
- 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xe0, 0x07,
- 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x62, 0x08, 0xe4, 0x10, 0x86, 0x21, 0x6a, 0x2a,
- 0xab, 0x32, 0xc7, 0x21, 0xc3, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x82, 0x08, 0x27, 0x2a, 0x6c, 0x43, 0xad, 0x43, 0x6d, 0x43,
- 0x2c, 0x3b, 0xeb, 0x3a, 0x8a, 0x32, 0xe8, 0x21, 0x25, 0x19, 0x41, 0x08,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x41, 0x08,
- 0x82, 0x08, 0x82, 0x08, 0x82, 0x08, 0x42, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0xe3, 0x10, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0x66, 0x19,
- 0x49, 0x2a, 0x0d, 0x3b, 0x8f, 0x43, 0x6f, 0x43, 0x0d, 0x3b, 0xac, 0x32,
- 0x8c, 0x32, 0x6b, 0x2a, 0x4b, 0x2a, 0xad, 0x32, 0x2b, 0x2a, 0x05, 0x11,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x67, 0x32, 0x2a, 0x3b, 0xed, 0x4b,
- 0x6e, 0x54, 0x4e, 0x54, 0x0e, 0x4c, 0xee, 0x4b, 0xee, 0x4b, 0xce, 0x4b,
- 0xce, 0x4b, 0xef, 0x4b, 0xef, 0x4b, 0x6d, 0x43, 0xab, 0x32, 0xc7, 0x21,
- 0xc3, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x11,
- 0x6a, 0x43, 0x87, 0x32, 0x84, 0x19, 0x61, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x08,
- 0x45, 0x19, 0x09, 0x2a, 0xcc, 0x32, 0x2e, 0x3b, 0x90, 0x43, 0xd1, 0x43,
- 0xd2, 0x4b, 0xb1, 0x43, 0xd2, 0x43, 0x92, 0x43, 0x51, 0x3b, 0x10, 0x3b,
- 0x8d, 0x32, 0xea, 0x21, 0x47, 0x19, 0xa3, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa2, 0x08,
- 0x23, 0x19, 0x06, 0x2a, 0x09, 0x3b, 0x2d, 0x54, 0xf0, 0x64, 0x4e, 0x54,
- 0x8c, 0x43, 0x2b, 0x3b, 0xea, 0x3a, 0x89, 0x32, 0x89, 0x32, 0x89, 0x32,
- 0xca, 0x32, 0xeb, 0x3a, 0x4d, 0x43, 0xcf, 0x4b, 0x10, 0x4c, 0x2d, 0x3b,
- 0x49, 0x2a, 0x66, 0x19, 0xa3, 0x10, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
- 0x83, 0x08, 0x06, 0x11, 0xa9, 0x21, 0x6d, 0x2a, 0x12, 0x3b, 0xeb, 0x21,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc5, 0x21, 0x0b, 0x54, 0x6a, 0x43, 0xc8, 0x3a,
- 0x06, 0x2a, 0x23, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xa2, 0x10, 0x04, 0x11, 0x65, 0x19, 0x85, 0x21, 0x85, 0x21, 0x86, 0x21,
- 0x24, 0x19, 0x04, 0x11, 0x82, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x41, 0x08, 0x25, 0x11, 0xc8, 0x21, 0x4a, 0x2a, 0xac, 0x32, 0xcd, 0x32,
- 0xcd, 0x32, 0xcd, 0x32, 0xad, 0x32, 0xad, 0x32, 0x6c, 0x2a, 0x0a, 0x22,
- 0x88, 0x21, 0x05, 0x11, 0x42, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x84, 0x21, 0x84, 0x21, 0xe5, 0x21, 0x67, 0x32,
- 0x09, 0x3b, 0x0c, 0x4c, 0x0f, 0x65, 0xef, 0x5c, 0xcc, 0x4b, 0x0a, 0x3b,
- 0x68, 0x2a, 0xe6, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0x19, 0xf0, 0x4b,
- 0xb0, 0x43, 0xcc, 0x32, 0x09, 0x2a, 0x87, 0x21, 0x25, 0x19, 0xe4, 0x10,
- 0xe4, 0x10, 0xe4, 0x10, 0xe4, 0x10, 0xc4, 0x10, 0x26, 0x11, 0x67, 0x19,
- 0xc9, 0x21, 0x6c, 0x2a, 0xf0, 0x3a, 0x73, 0x3b, 0xaf, 0x32, 0x2c, 0x2a,
- 0xaa, 0x21, 0x68, 0x19, 0x07, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x00,
- 0x08, 0x3b, 0xe8, 0x3a, 0xc7, 0x3a, 0x67, 0x32, 0x06, 0x2a, 0x64, 0x19,
- 0xa2, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x19, 0x06, 0x22,
- 0x68, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x21, 0x00, 0xe4, 0x10, 0x46, 0x19, 0xa7, 0x21, 0xc8, 0x21,
- 0xe9, 0x21, 0xe9, 0x21, 0xe9, 0x21, 0xa8, 0x21, 0x87, 0x19, 0x26, 0x19,
- 0xa3, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x08, 0x06, 0x11,
- 0x68, 0x19, 0xaa, 0x21, 0xec, 0x21, 0x48, 0x19, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x43,
- 0x48, 0x43, 0x28, 0x43, 0x28, 0x43, 0x69, 0x43, 0xca, 0x4b, 0x6c, 0x54,
- 0x2f, 0x65, 0x50, 0x6d, 0x8e, 0x5c, 0x6b, 0x43, 0xa9, 0x32, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x8b, 0x32, 0x0d, 0x3b, 0x8c, 0x32, 0x4a, 0x2a,
- 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2b, 0x2a, 0x6c, 0x2a, 0xae, 0x32,
- 0x10, 0x3b, 0x93, 0x43, 0x32, 0x3b, 0x8e, 0x2a, 0xca, 0x21, 0x47, 0x19,
- 0xc5, 0x10, 0x83, 0x08, 0x41, 0x00, 0x42, 0x08, 0x21, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x63, 0x19, 0x43, 0x19,
- 0xa4, 0x21, 0x84, 0x21, 0x23, 0x19, 0x03, 0x11, 0xa2, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x03, 0x11, 0x27, 0x2a, 0xe6, 0x21, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa3, 0x08, 0xe4, 0x10,
- 0xe4, 0x10, 0x05, 0x11, 0xe4, 0x10, 0xc4, 0x10, 0x83, 0x08, 0x21, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x62, 0x08, 0x06, 0x11, 0xa9, 0x21, 0x2d, 0x2a,
- 0x8f, 0x32, 0xd1, 0x32, 0xf2, 0x32, 0xf3, 0x3a, 0xf3, 0x32, 0xb2, 0x32,
- 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc2, 0x10, 0xee, 0x75, 0xae, 0x75, 0x4d, 0x6d,
- 0x4d, 0x65, 0x2d, 0x65, 0x2e, 0x65, 0x8f, 0x6d, 0x6f, 0x6d, 0x4f, 0x6d,
- 0x2f, 0x65, 0x4d, 0x54, 0x2a, 0x3b, 0x85, 0x19, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0xcd, 0x32,
- 0x91, 0x43, 0x71, 0x43, 0x71, 0x43, 0x92, 0x43, 0x92, 0x43, 0x92, 0x43,
- 0x72, 0x43, 0x10, 0x3b, 0x4d, 0x2a, 0xa9, 0x21, 0xe5, 0x10, 0x62, 0x08,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xe3, 0x10, 0xe6, 0x21, 0x2a, 0x3b, 0xe3, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x62, 0x08, 0xe5, 0x10, 0xa9, 0x21, 0x4d, 0x2a, 0xf1, 0x32, 0x33, 0x3b,
- 0x13, 0x3b, 0x13, 0x3b, 0x13, 0x3b, 0xb1, 0x32, 0xb2, 0x32, 0xb2, 0x32,
- 0xd3, 0x32, 0x71, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x8a, 0x5c, 0x6d, 0x6d, 0xce, 0x75, 0xae, 0x75, 0xae, 0x6d,
- 0xae, 0x6d, 0x8e, 0x6d, 0x6f, 0x6d, 0x6f, 0x6d, 0x4f, 0x6d, 0xad, 0x5c,
- 0xcb, 0x4b, 0xe9, 0x3a, 0x44, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x62, 0x08, 0x2f, 0x3b, 0xb2, 0x43, 0x92, 0x43, 0x51, 0x3b,
- 0xae, 0x32, 0x2c, 0x2a, 0x68, 0x19, 0xa4, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x62, 0x08, 0x84, 0x08, 0xa4, 0x08, 0x84, 0x08, 0x84, 0x08,
- 0x84, 0x08, 0x62, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x45, 0x32, 0x07, 0x3b, 0x04, 0x2a, 0x43, 0x19, 0x02, 0x11, 0xa1, 0x08,
- 0xa2, 0x08, 0xa2, 0x08, 0xc2, 0x10, 0x03, 0x11, 0x84, 0x21, 0x26, 0x2a,
- 0xe9, 0x3a, 0x0c, 0x4c, 0x06, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x10, 0x05, 0x11, 0x46, 0x19,
- 0xa9, 0x21, 0x4c, 0x2a, 0xd0, 0x32, 0x52, 0x3b, 0x32, 0x3b, 0x12, 0x3b,
- 0xb0, 0x32, 0x6f, 0x2a, 0x2d, 0x2a, 0x0d, 0x22, 0x0d, 0x22, 0x0d, 0x22,
- 0x0d, 0x22, 0x2f, 0x2a, 0x71, 0x2a, 0x4a, 0x19, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, 0x10,
- 0x45, 0x32, 0x47, 0x43, 0x09, 0x4c, 0x8b, 0x5c, 0xcc, 0x5c, 0x2d, 0x65,
- 0x2d, 0x65, 0x0d, 0x65, 0xcd, 0x5c, 0x6c, 0x54, 0xeb, 0x4b, 0x49, 0x43,
- 0x67, 0x32, 0x64, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x00, 0x4c, 0x2a,
- 0xea, 0x21, 0x26, 0x19, 0x83, 0x08, 0x00, 0x00, 0x42, 0x08, 0xe5, 0x10,
- 0x47, 0x19, 0x89, 0x19, 0xaa, 0x21, 0xaa, 0x21, 0xab, 0x21, 0x8a, 0x19,
- 0x8a, 0x19, 0x49, 0x19, 0x07, 0x11, 0xc5, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x0d, 0x7e,
- 0xed, 0x75, 0xeb, 0x64, 0x29, 0x54, 0x68, 0x43, 0x07, 0x3b, 0xa7, 0x32,
- 0xa7, 0x32, 0xa7, 0x32, 0xc8, 0x3a, 0x08, 0x3b, 0x8a, 0x43, 0x2c, 0x54,
- 0xee, 0x5c, 0x50, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x0b, 0x22, 0x72, 0x43, 0x52, 0x3b, 0x32, 0x3b, 0xf1, 0x32, 0x6e, 0x2a,
- 0xeb, 0x21, 0xaa, 0x21, 0x69, 0x19, 0x48, 0x19, 0x27, 0x19, 0x49, 0x19,
- 0x49, 0x19, 0x8a, 0x19, 0xac, 0x21, 0x0f, 0x22, 0x51, 0x2a, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa1, 0x08, 0xe2, 0x10,
- 0xe2, 0x10, 0xc4, 0x21, 0x86, 0x32, 0x07, 0x3b, 0x88, 0x43, 0x89, 0x43,
- 0xea, 0x4b, 0x89, 0x43, 0x69, 0x43, 0x08, 0x3b, 0x87, 0x32, 0xc5, 0x21,
- 0xe3, 0x10, 0xa2, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x83, 0x08, 0x05, 0x11, 0x89, 0x19, 0x0c, 0x22,
- 0x6e, 0x2a, 0xb0, 0x32, 0xb1, 0x32, 0xb1, 0x32, 0xd2, 0x32, 0x91, 0x32,
- 0x91, 0x2a, 0x2f, 0x2a, 0xee, 0x21, 0x8b, 0x19, 0x08, 0x11, 0x21, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x19, 0xac, 0x75, 0xec, 0x75,
- 0xcd, 0x75, 0xcd, 0x75, 0xad, 0x6d, 0x8d, 0x6d, 0x2c, 0x65, 0xcc, 0x5c,
- 0xac, 0x5c, 0x8c, 0x5c, 0xed, 0x64, 0x0e, 0x65, 0x2e, 0x65, 0x0f, 0x65,
- 0x2f, 0x65, 0x0c, 0x4c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc1, 0x10, 0x49, 0x6d, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x0b, 0x22, 0x2c, 0x2a, 0x89, 0x19,
- 0x26, 0x11, 0xc5, 0x10, 0xa4, 0x08, 0x83, 0x08, 0x83, 0x08, 0x83, 0x08,
- 0xa4, 0x08, 0xc5, 0x10, 0x07, 0x11, 0x6a, 0x19, 0xcd, 0x21, 0x72, 0x2a,
- 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x54, 0xa7, 0x4b, 0x45, 0x2a,
- 0x63, 0x21, 0x83, 0x21, 0x84, 0x21, 0xa4, 0x21, 0x05, 0x2a, 0x25, 0x2a,
- 0x25, 0x2a, 0x25, 0x2a, 0xe5, 0x29, 0x84, 0x21, 0x64, 0x19, 0x64, 0x19,
- 0x64, 0x19, 0x44, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x4a, 0x7e, 0xeb, 0x75, 0x04, 0x2a, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x11, 0x12, 0x3b,
- 0x12, 0x3b, 0xf2, 0x32, 0xf2, 0x32, 0xd2, 0x32, 0xd2, 0x32, 0xb2, 0x32,
- 0xb2, 0x32, 0x92, 0x32, 0x92, 0x32, 0x72, 0x2a, 0xee, 0x21, 0x6a, 0x19,
- 0x84, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xe2, 0x10, 0xc6, 0x3a, 0xe8, 0x4b, 0x2b, 0x6d,
- 0xcc, 0x75, 0xad, 0x6d, 0x8d, 0x6d, 0x8d, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d,
- 0x4d, 0x6d, 0x4e, 0x6d, 0x2e, 0x65, 0x2e, 0x65, 0x2e, 0x65, 0x0e, 0x65,
- 0x0f, 0x65, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0xac, 0x6d, 0x0a, 0x4c, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x83, 0x08, 0xe6, 0x10, 0xa4, 0x08, 0xe6, 0x10, 0xe6, 0x10, 0xc5, 0x10,
- 0xc5, 0x10, 0xa5, 0x10, 0xa5, 0x10, 0xc5, 0x10, 0x29, 0x19, 0xad, 0x21,
- 0x52, 0x2a, 0x42, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xe9, 0x64, 0xec, 0x75, 0xac, 0x75, 0x49, 0x54,
- 0x07, 0x3b, 0x25, 0x2a, 0x45, 0x2a, 0x25, 0x2a, 0x25, 0x2a, 0x45, 0x2a,
- 0x05, 0x2a, 0x25, 0x2a, 0x05, 0x2a, 0x06, 0x2a, 0x06, 0x2a, 0x06, 0x2a,
- 0xc8, 0x32, 0xe9, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x0d, 0x65,
- 0x44, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x89, 0x19, 0x13, 0x3b, 0xd2, 0x32, 0xb2, 0x32, 0xb2, 0x32,
- 0xb2, 0x32, 0x92, 0x32, 0x92, 0x32, 0x72, 0x2a, 0x72, 0x2a, 0x31, 0x2a,
- 0xad, 0x21, 0xa5, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xa5, 0x32, 0x65, 0x32, 0x85, 0x32, 0xa8, 0x4b,
- 0xea, 0x64, 0xad, 0x75, 0x8d, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x4d, 0x6d,
- 0x4d, 0x6d, 0x2d, 0x65, 0x2e, 0x65, 0x2e, 0x65, 0x0e, 0x65, 0x0e, 0x65,
- 0x2c, 0x54, 0x88, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0x0f, 0x65, 0xe9, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc4, 0x10, 0xab, 0x21, 0x89, 0x19, 0x69, 0x19,
- 0x48, 0x19, 0x07, 0x11, 0x07, 0x11, 0x07, 0x11, 0xe7, 0x10, 0x08, 0x11,
- 0x8c, 0x21, 0x11, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x87, 0x4b, 0x0c, 0x7e, 0xcb, 0x75, 0xcc, 0x75, 0xcc, 0x75,
- 0x4b, 0x6d, 0x29, 0x54, 0x68, 0x43, 0xc7, 0x3a, 0xe7, 0x3a, 0xc7, 0x3a,
- 0x66, 0x32, 0xc7, 0x3a, 0xa7, 0x32, 0xa7, 0x32, 0x29, 0x43, 0xeb, 0x4b,
- 0xce, 0x5c, 0xec, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x8e, 0x5c, 0x2e, 0x54, 0xa2, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x08, 0x90, 0x2a, 0x70, 0x2a,
- 0x70, 0x2a, 0x92, 0x32, 0x92, 0x2a, 0x72, 0x2a, 0x52, 0x2a, 0x52, 0x2a,
- 0x52, 0x2a, 0x11, 0x2a, 0xa6, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xe7, 0x4b, 0x26, 0x43, 0x06, 0x3b, 0x06, 0x3b, 0xe6, 0x3a,
- 0x67, 0x43, 0x69, 0x54, 0x0b, 0x65, 0x6d, 0x6d, 0x4d, 0x6d, 0x4d, 0x6d,
- 0x4d, 0x6d, 0x2d, 0x65, 0x2d, 0x65, 0x0e, 0x65, 0x6c, 0x54, 0xab, 0x4b,
- 0xc8, 0x3a, 0x06, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x54, 0x4e, 0x54, 0x70, 0x54, 0x28, 0x2a, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc5, 0x10, 0x91, 0x2a,
- 0x2f, 0x2a, 0xed, 0x21, 0x8b, 0x21, 0x49, 0x19, 0x49, 0x19, 0x29, 0x19,
- 0x29, 0x19, 0x6b, 0x19, 0x8d, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x22, 0x19, 0x4a, 0x6d, 0xcb, 0x75, 0xcb, 0x75, 0xab, 0x6d, 0x8b, 0x6d,
- 0x6c, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0xce, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0x10, 0x4c, 0x4e, 0x43,
- 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc5, 0x10,
- 0xcc, 0x21, 0xed, 0x21, 0x2f, 0x2a, 0x72, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x32, 0x2a, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x46, 0x43, 0xcb, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xef, 0x4b, 0xaf, 0x4b,
- 0xd1, 0x4b, 0x66, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xe7, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0x09, 0x65, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xef, 0x4b, 0xaf, 0x43,
- 0x6f, 0x43, 0x71, 0x43, 0x8d, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x49, 0x19, 0x71, 0x32, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x6c, 0x19, 0x00, 0x00, 0x00, 0x00,
- 0x2b, 0x7e, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xef, 0x4b, 0xaf, 0x4b,
- 0x70, 0x43, 0x50, 0x43, 0x30, 0x3b, 0x11, 0x3b, 0xc5, 0x10, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x21, 0x00, 0x92, 0x32, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xf1, 0x29, 0x00, 0x00, 0x02, 0x19,
- 0x0b, 0x7e, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xef, 0x4b, 0xaf, 0x4b,
- 0x70, 0x43, 0x50, 0x43, 0x10, 0x3b, 0xf0, 0x3a, 0xf2, 0x3a, 0xcb, 0x21,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x2f, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x32, 0x2a, 0x21, 0x00, 0x44, 0x2a,
- 0xea, 0x75, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xef, 0x4b, 0xaf, 0x4b,
- 0x70, 0x43, 0x50, 0x43, 0x30, 0x3b, 0xf0, 0x3a, 0xb0, 0x32, 0x91, 0x32,
- 0x50, 0x32, 0x42, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x8a, 0x19, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x12, 0x2a, 0x84, 0x08, 0x25, 0x43,
- 0xca, 0x75, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xef, 0x4b, 0xaf, 0x4b,
- 0x70, 0x43, 0x50, 0x43, 0x30, 0x3b, 0xf0, 0x3a, 0xb0, 0x32, 0x90, 0x32,
- 0x71, 0x32, 0x52, 0x2a, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x28, 0x19, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xc7, 0x10, 0xc7, 0x4b,
- 0xca, 0x75, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xef, 0x4b, 0xaf, 0x4b,
- 0x70, 0x43, 0x50, 0x43, 0x30, 0x3b, 0xf0, 0x3a, 0xb0, 0x32, 0x90, 0x32,
- 0x51, 0x32, 0x52, 0x2a, 0xe8, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x07, 0x11, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x09, 0x19, 0x48, 0x54,
- 0xca, 0x75, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xef, 0x4b, 0xaf, 0x4b,
- 0x70, 0x43, 0x50, 0x43, 0x30, 0x3b, 0xf0, 0x3a, 0xb0, 0x32, 0x90, 0x32,
- 0x92, 0x32, 0x6a, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x28, 0x19, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x4b, 0x19, 0xa8, 0x5c,
- 0xca, 0x75, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xef, 0x4b, 0xaf, 0x4b,
- 0x70, 0x43, 0x50, 0x43, 0x10, 0x3b, 0xf0, 0x3a, 0xd1, 0x3a, 0x4f, 0x2a,
- 0x63, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xac, 0x21, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x6c, 0x19, 0xa8, 0x5c,
- 0xca, 0x75, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xef, 0x4b, 0xaf, 0x4b,
- 0x6f, 0x43, 0x50, 0x43, 0x30, 0x3b, 0xf0, 0x3a, 0x06, 0x11, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x8d, 0x21, 0xa8, 0x5c,
- 0xca, 0x75, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xef, 0x4b, 0xaf, 0x43,
- 0x90, 0x43, 0x91, 0x43, 0xc9, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x84, 0x08, 0x92, 0x32, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x8d, 0x21, 0xc8, 0x5c,
- 0xca, 0x75, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xef, 0x4b, 0xf1, 0x4b,
- 0xac, 0x32, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xed, 0x21, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x6c, 0x19, 0x48, 0x54,
- 0xca, 0x75, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x6e, 0x54, 0x4e, 0x54, 0x4f, 0x54, 0x8e, 0x43, 0xa3, 0x10,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x08,
- 0xb2, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x4b, 0x19, 0xc7, 0x4b,
- 0xca, 0x75, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xad, 0x5c, 0x8e, 0x5c, 0x6f, 0x54, 0x85, 0x21, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x2a, 0x19, 0x26, 0x43,
- 0xca, 0x75, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0x0f, 0x65, 0x88, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2e, 0x2a, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xe7, 0x10, 0x64, 0x32,
- 0xea, 0x75, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0x8b, 0x6d, 0x6c, 0x6d, 0x8d, 0x6d, 0xaa, 0x4b,
- 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2e, 0x2a, 0xb1, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x12, 0x2a, 0x85, 0x08, 0x22, 0x19,
- 0x0b, 0x7e, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x2a, 0x7e, 0xeb, 0x75, 0xea, 0x64, 0x02, 0x19, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x21, 0x00, 0x90, 0x2a, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x12, 0x2a, 0x21, 0x00, 0x00, 0x00,
- 0x4b, 0x7e, 0xaa, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x19, 0x4b, 0x7e, 0x24, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x48, 0x19, 0xf2, 0x32, 0xb1, 0x32, 0x90, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x12, 0x2a, 0x00, 0x00, 0x00, 0x00,
- 0x09, 0x65, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x81, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc4, 0x10, 0xb0, 0x32,
- 0xd1, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x8d, 0x21, 0x00, 0x00, 0x00, 0x00,
- 0x46, 0x43, 0xcb, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x42, 0x08, 0x6d, 0x2a, 0x11, 0x3b, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xe8, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0x62, 0x19, 0xeb, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xea, 0x21, 0x32, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x32, 0x2a, 0x42, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xcb, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x67, 0x19,
- 0x31, 0x3b, 0x11, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0xf0, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x87, 0x4b, 0xab, 0x75, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x10, 0x10, 0x3b, 0x31, 0x3b,
- 0x10, 0x3b, 0x10, 0x33, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x31, 0x2a, 0x09, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xc1, 0x10, 0x0b, 0x76, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x61, 0x08, 0xad, 0x32, 0x71, 0x43, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x52, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc9, 0x64, 0x8b, 0x6d, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x2a, 0x2a, 0x91, 0x43, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x8c, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc3, 0x21, 0xcb, 0x75, 0x6b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x87, 0x19, 0x91, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x52, 0x2a, 0x63, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0x64, 0x8b, 0x6d, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xe4, 0x10, 0x6f, 0x43, 0x90, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a,
- 0xad, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x19, 0xec, 0x75, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x41, 0x08, 0xed, 0x3a, 0xd1, 0x4b, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x52, 0x2a,
- 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x54, 0x6b, 0x6d,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x2a,
- 0x11, 0x4c, 0xb0, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x6b, 0x19,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0xcc, 0x75,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc7, 0x21, 0xf0, 0x4b, 0xd0, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x2a,
- 0xac, 0x75, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x04, 0x11, 0xae, 0x43, 0x10, 0x4c, 0xcf, 0x4b, 0xaf, 0x43,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x92, 0x32, 0x84, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x09, 0x54, 0x6c, 0x6d, 0x2c, 0x65, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x71, 0x54, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x71, 0x32, 0x6a, 0x19, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x0b, 0x65, 0x4c, 0x6d, 0x2c, 0x65, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x30, 0x4c, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x71, 0x2a, 0x0f, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x40, 0x08, 0x6c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x30, 0x4c, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x71, 0x2a, 0x70, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xa1, 0x08, 0x6d, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x30, 0x4c, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, 0x10, 0x4d, 0x6d, 0x0c, 0x65,
- 0x0c, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x30, 0x4c, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32,
- 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa1, 0x08, 0x2d, 0x65,
- 0x0d, 0x65, 0xed, 0x64, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x30, 0x4c, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x90, 0x32, 0x21, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
- 0xac, 0x5c, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x30, 0x4c, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x4f, 0x2a, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xa9, 0x4b, 0x2e, 0x65, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x30, 0x4c, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xf2, 0x32, 0xab, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc5, 0x21, 0x2e, 0x65, 0xcd, 0x5c, 0xad, 0x5c,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x30, 0x4c, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd1, 0x32,
- 0xd1, 0x32, 0xc5, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x8a, 0x43, 0x0e, 0x65,
- 0xae, 0x5c, 0xab, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x30, 0x4c, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0x12, 0x3b, 0xeb, 0x21,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x19,
- 0x2c, 0x54, 0xec, 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x30, 0x4c, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0x31, 0x3b, 0x8e, 0x2a, 0x62, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x03, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x30, 0x4c, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x52, 0x3b, 0x6d, 0x2a, 0xa4, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x30, 0x4c, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x71, 0x43, 0x10, 0x3b, 0xc9, 0x21,
- 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc3, 0x10, 0x30, 0x54, 0xef, 0x4b, 0xef, 0x4b, 0xcf, 0x4b, 0xcf, 0x4b,
- 0xaf, 0x43, 0xb0, 0x43, 0xb0, 0x43, 0x90, 0x43, 0x90, 0x43, 0xb1, 0x43,
- 0xb1, 0x43, 0xcd, 0x32, 0xc9, 0x21, 0xa3, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x62, 0x08, 0xaa, 0x32, 0xcb, 0x32, 0x0c, 0x3b, 0x0c, 0x3b, 0x0c, 0x3b,
- 0xec, 0x3a, 0xab, 0x32, 0x4a, 0x2a, 0xe8, 0x21, 0x46, 0x19, 0x83, 0x08,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2020, Baikal Electronics, JSC. All rights reserved.
- *
- * Author: Pavel Parkhomenko <pavel.parkhomenko@baikalelectronics.ru>
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/*
- * To change a logo, replace array contents below with a BMP file dump.
- * Source BMP file have to be of 16-bpp color format (RGB565).
- * Optimal size is 72x72 pixels (or 64x84 pixels for wide displays).
- */
-
-#if !DEBUG
-const unsigned char bl1_logo[] = {
- 0x42, 0x4d, 0x46, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x00,
- 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x54, 0x00,
- 0x00, 0x00, 0x01, 0x00, 0x10, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x2a,
- 0x00, 0x00, 0x46, 0x5c, 0x00, 0x00, 0x46, 0x5c, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xe0, 0x07,
- 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x82, 0x08,
- 0xe4, 0x10, 0xa7, 0x21, 0x29, 0x2a, 0x45, 0x19, 0x61, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x41, 0x00, 0x27, 0x2a, 0x0e, 0x4c, 0x2f, 0x4c,
- 0x0f, 0x4c, 0xef, 0x4b, 0xef, 0x4b, 0x8e, 0x43, 0x69, 0x2a, 0xe3, 0x10,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x20, 0x00, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x21, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x86, 0x21,
- 0xab, 0x32, 0x0e, 0x3b, 0x2e, 0x3b, 0x2f, 0x3b, 0x2f, 0x3b, 0x2f, 0x3b,
- 0xce, 0x32, 0x47, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x85, 0x19, 0x6b, 0x43, 0xe9, 0x3a, 0x27, 0x2a, 0xa5, 0x21, 0x44, 0x19,
- 0x44, 0x19, 0x24, 0x19, 0x24, 0x19, 0x45, 0x19, 0xa6, 0x21, 0x29, 0x2a,
- 0xeb, 0x3a, 0x6e, 0x43, 0x0c, 0x3b, 0x29, 0x2a, 0x66, 0x19, 0xe4, 0x10,
- 0x83, 0x08, 0x62, 0x08, 0x41, 0x08, 0x41, 0x08, 0x83, 0x08, 0xc4, 0x10,
- 0x83, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
- 0x85, 0x21, 0xa9, 0x32, 0x4b, 0x43, 0xad, 0x43, 0xad, 0x4b, 0xad, 0x43,
- 0x8d, 0x43, 0x4c, 0x43, 0xaa, 0x32, 0xc7, 0x21, 0xa3, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x62, 0x08, 0x82, 0x08, 0x82, 0x08,
- 0x83, 0x08, 0x83, 0x08, 0x62, 0x08, 0x62, 0x08, 0x41, 0x08, 0x20, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x2a,
- 0xae, 0x5c, 0xec, 0x4b, 0x27, 0x2a, 0x61, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x19, 0xab, 0x32, 0x8f, 0x43,
- 0x8f, 0x43, 0x90, 0x43, 0x90, 0x43, 0x70, 0x43, 0x0e, 0x3b, 0x30, 0x3b,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x8e, 0x32, 0x88, 0x19,
- 0x42, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x08, 0xe3, 0x10, 0x85, 0x21,
- 0xc9, 0x3a, 0x4d, 0x54, 0x6e, 0x54, 0xed, 0x4b, 0x8c, 0x43, 0x4b, 0x43,
- 0x0b, 0x3b, 0x0b, 0x3b, 0x0b, 0x3b, 0x2c, 0x3b, 0x6d, 0x43, 0xcf, 0x4b,
- 0xcf, 0x4b, 0xab, 0x32, 0x66, 0x19, 0xc3, 0x10, 0x62, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x41, 0x00, 0x83, 0x08, 0x05, 0x11, 0xca, 0x21, 0xaf, 0x32, 0x0c, 0x22,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x10, 0x08, 0x3b,
- 0xc8, 0x32, 0xe5, 0x21, 0x44, 0x19, 0x82, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x20, 0x00, 0x03, 0x11, 0x85, 0x21, 0xc6, 0x21, 0x07, 0x2a, 0x07, 0x2a,
- 0xe7, 0x21, 0x85, 0x19, 0x04, 0x11, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x61, 0x08, 0xe4, 0x10, 0x66, 0x19, 0xe9, 0x21, 0x6b, 0x2a, 0x6b, 0x2a,
- 0x6b, 0x2a, 0x4b, 0x2a, 0x4b, 0x2a, 0xc9, 0x21, 0x47, 0x19, 0xc4, 0x10,
- 0x62, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x46, 0x2a, 0x29, 0x3b, 0xaa, 0x4b, 0x6d, 0x54,
- 0x8d, 0x5c, 0xae, 0x5c, 0x6e, 0x54, 0x2a, 0x3b, 0xc5, 0x21, 0x82, 0x08,
- 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x08, 0x2a, 0x8f, 0x43, 0xaf, 0x43, 0x8f, 0x43,
- 0x4e, 0x3b, 0xac, 0x32, 0x2a, 0x2a, 0x09, 0x22, 0xe9, 0x21, 0xe9, 0x21,
- 0xea, 0x21, 0x6c, 0x2a, 0xcf, 0x32, 0xf0, 0x3a, 0xf0, 0x3a, 0xf0, 0x3a,
- 0x0c, 0x2a, 0x26, 0x11, 0x63, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x00,
- 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08,
- 0x24, 0x19, 0xa8, 0x32, 0x0d, 0x4c, 0x8f, 0x5c, 0x24, 0x19, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x82, 0x08, 0x62, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x21, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xa4, 0x10, 0xa9, 0x21, 0x6e, 0x2a,
- 0xf2, 0x32, 0xf2, 0x32, 0x2d, 0x22, 0x62, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xc2, 0x10, 0x2a, 0x54, 0x8e, 0x6d, 0x6e, 0x6d, 0x4e, 0x6d,
- 0xee, 0x64, 0x4c, 0x54, 0x4a, 0x43, 0x67, 0x2a, 0x44, 0x19, 0x20, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x46, 0x19, 0x4e, 0x3b, 0x90, 0x43, 0xd1, 0x43, 0xb1, 0x43,
- 0xb1, 0x43, 0x91, 0x43, 0x91, 0x43, 0x51, 0x3b, 0xcf, 0x32, 0x2c, 0x2a,
- 0x88, 0x19, 0xe5, 0x10, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x42, 0x08, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08,
- 0xe2, 0x10, 0xc2, 0x10, 0xa2, 0x10, 0x03, 0x11, 0xa4, 0x21, 0x87, 0x32,
- 0xab, 0x4b, 0x2d, 0x54, 0x8e, 0x5c, 0xef, 0x5c, 0x85, 0x21, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00,
- 0x25, 0x11, 0x45, 0x19, 0xa3, 0x08, 0x82, 0x08, 0x82, 0x08, 0x82, 0x08,
- 0xa3, 0x08, 0x05, 0x11, 0xa9, 0x21, 0x6c, 0x2a, 0xae, 0x32, 0xf0, 0x32,
- 0x11, 0x3b, 0xd0, 0x32, 0x2c, 0x2a, 0xaa, 0x21, 0x68, 0x19, 0x28, 0x19,
- 0xc5, 0x10, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x84, 0x21, 0xe7, 0x3a, 0x28, 0x43, 0x89, 0x4b,
- 0x08, 0x3b, 0xa7, 0x32, 0x06, 0x2a, 0x03, 0x11, 0x00, 0x00, 0x00, 0x00,
- 0x20, 0x00, 0x81, 0x08, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa3, 0x10,
- 0xe8, 0x21, 0x2a, 0x2a, 0x6b, 0x2a, 0x0a, 0x22, 0xc9, 0x21, 0x67, 0x19,
- 0xa3, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x08, 0x68, 0x19,
- 0x0c, 0x22, 0x6f, 0x2a, 0xb1, 0x32, 0xb1, 0x32, 0xb2, 0x32, 0x07, 0x11,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x21,
- 0xad, 0x75, 0x4d, 0x6d, 0xec, 0x64, 0xed, 0x64, 0xcd, 0x64, 0x2e, 0x65,
- 0x2e, 0x65, 0x0e, 0x65, 0xce, 0x5c, 0x2c, 0x54, 0x09, 0x3b, 0xc2, 0x10,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x21, 0x2f, 0x3b,
- 0x50, 0x3b, 0x30, 0x3b, 0x71, 0x43, 0x71, 0x43, 0x51, 0x3b, 0x31, 0x3b,
- 0xae, 0x32, 0x2c, 0x2a, 0x68, 0x19, 0xa4, 0x10, 0x21, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa2, 0x10,
- 0xc5, 0x21, 0x09, 0x3b, 0xa8, 0x32, 0x61, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x62, 0x08, 0x26, 0x19, 0xea, 0x21, 0x6d, 0x2a,
- 0xd0, 0x32, 0x12, 0x3b, 0xf2, 0x3a, 0xf2, 0x32, 0xb1, 0x32, 0x90, 0x32,
- 0x90, 0x32, 0xb2, 0x32, 0x2f, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xa6, 0x3a, 0xcb, 0x64, 0x4d, 0x6d, 0x4d, 0x65, 0x2d, 0x65, 0x2d, 0x65,
- 0x0d, 0x65, 0x0d, 0x65, 0xee, 0x64, 0xeb, 0x4b, 0x67, 0x32, 0xc2, 0x10,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xe4, 0x10, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b,
- 0xae, 0x32, 0xa9, 0x21, 0x83, 0x08, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
- 0xe5, 0x10, 0x48, 0x19, 0x8a, 0x21, 0x8a, 0x19, 0x8a, 0x19, 0x6a, 0x19,
- 0x28, 0x11, 0x42, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x21, 0x8c, 0x6d, 0x0b, 0x65,
- 0x09, 0x54, 0x68, 0x43, 0x08, 0x3b, 0x08, 0x3b, 0x28, 0x3b, 0x89, 0x43,
- 0x2b, 0x54, 0xee, 0x64, 0xef, 0x64, 0x4d, 0x54, 0x44, 0x19, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x82, 0x08, 0x6c, 0x2a, 0xae, 0x32, 0x31, 0x3b, 0x31, 0x3b,
- 0x11, 0x3b, 0xd0, 0x32, 0x8f, 0x32, 0x4d, 0x2a, 0xca, 0x21, 0x48, 0x19,
- 0x06, 0x11, 0xe6, 0x10, 0xe6, 0x10, 0x07, 0x11, 0x29, 0x19, 0x8b, 0x19,
- 0x63, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x61, 0x08, 0x61, 0x08, 0xc2, 0x10, 0x63, 0x19, 0xc4, 0x21,
- 0x05, 0x2a, 0x05, 0x2a, 0xc5, 0x21, 0x84, 0x21, 0x03, 0x11, 0x81, 0x08,
- 0x81, 0x08, 0x03, 0x11, 0x61, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x42, 0x08, 0x62, 0x08, 0x42, 0x08, 0xc4, 0x10, 0x89, 0x19,
- 0x2d, 0x2a, 0xaf, 0x32, 0xf1, 0x32, 0xf2, 0x32, 0xd2, 0x32, 0xd2, 0x32,
- 0xb2, 0x32, 0xb2, 0x32, 0x92, 0x32, 0x71, 0x2a, 0x8b, 0x19, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x21, 0x0b, 0x65,
- 0x8c, 0x6d, 0x6c, 0x6d, 0x4d, 0x6d, 0x4d, 0x6d, 0x2d, 0x65, 0x0d, 0x65,
- 0x0d, 0x65, 0x0d, 0x65, 0xee, 0x64, 0xee, 0x64, 0xce, 0x5c, 0xc9, 0x3a,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x08,
- 0xae, 0x32, 0x31, 0x3b, 0x6d, 0x2a, 0x26, 0x19, 0x62, 0x08, 0x21, 0x00,
- 0x00, 0x00, 0x42, 0x08, 0x63, 0x08, 0x62, 0x08, 0x63, 0x08, 0x63, 0x08,
- 0x21, 0x00, 0x00, 0x00, 0x21, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x41, 0x08, 0x49, 0x54, 0x8c, 0x6d, 0x29, 0x54, 0xc6, 0x3a,
- 0xc4, 0x21, 0x43, 0x19, 0xc2, 0x10, 0xc2, 0x10, 0x03, 0x11, 0x84, 0x21,
- 0x46, 0x2a, 0x49, 0x43, 0x8d, 0x54, 0x2a, 0x3b, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x08, 0x4c, 0x2a,
- 0x31, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0x90, 0x32,
- 0x90, 0x32, 0x70, 0x2a, 0x70, 0x2a, 0x70, 0x2a, 0x50, 0x2a, 0x50, 0x2a,
- 0x51, 0x2a, 0xac, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
- 0xa1, 0x10, 0x83, 0x21, 0xc6, 0x3a, 0x88, 0x4b, 0xe9, 0x4b, 0x0a, 0x54,
- 0x2a, 0x54, 0x2b, 0x54, 0xea, 0x4b, 0xca, 0x4b, 0x69, 0x43, 0xa8, 0x32,
- 0x85, 0x21, 0xa2, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x83, 0x08,
- 0x26, 0x19, 0xeb, 0x21, 0x4e, 0x2a, 0x8f, 0x32, 0xb0, 0x32, 0xb1, 0x32,
- 0x91, 0x32, 0x70, 0x2a, 0x2f, 0x2a, 0xcc, 0x21, 0x29, 0x19, 0x84, 0x08,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x40, 0x08, 0x67, 0x43, 0xac, 0x75, 0xac, 0x75,
- 0x8c, 0x6d, 0x6c, 0x6d, 0x4c, 0x6d, 0x0c, 0x65, 0xcc, 0x5c, 0xac, 0x5c,
- 0xcd, 0x5c, 0xed, 0x64, 0xee, 0x64, 0xee, 0x5c, 0xce, 0x5c, 0xa8, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x40, 0x08, 0x25, 0x43, 0xa3, 0x21, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0xca, 0x21, 0xea, 0x21, 0x26, 0x11,
- 0xa4, 0x08, 0x83, 0x08, 0x62, 0x08, 0x42, 0x08, 0x42, 0x08, 0x63, 0x08,
- 0x83, 0x08, 0xc5, 0x10, 0x29, 0x19, 0xce, 0x21, 0x6a, 0x19, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x83, 0x21, 0xea, 0x64, 0x2b, 0x6d, 0x88, 0x4b, 0xe4, 0x29, 0xa1, 0x08,
- 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00,
- 0x61, 0x08, 0x84, 0x21, 0xc8, 0x3a, 0x26, 0x2a, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x61, 0x08, 0x27, 0x54, 0xeb, 0x75, 0x63, 0x19, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xeb, 0x21, 0xd0, 0x32, 0xd1, 0x32, 0xb1, 0x32,
- 0xb1, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0xcd, 0x21, 0x63, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x83, 0x21,
- 0x06, 0x3b, 0x69, 0x54, 0xcb, 0x5c, 0x0b, 0x65, 0x2c, 0x65, 0x2c, 0x65,
- 0x2d, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0x8d, 0x5c, 0x4c, 0x54,
- 0xcb, 0x4b, 0xc5, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54,
- 0xcb, 0x75, 0x6c, 0x6d, 0x04, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xa4, 0x08, 0x48, 0x19, 0x89, 0x19, 0xab, 0x21, 0xec, 0x21,
- 0xab, 0x21, 0x8a, 0x19, 0x28, 0x19, 0xa5, 0x10, 0x42, 0x08, 0x84, 0x08,
- 0x4a, 0x19, 0xc6, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xc1, 0x10, 0x69, 0x5c, 0xec, 0x75, 0x8c, 0x6d, 0x8c, 0x6d,
- 0x6c, 0x6d, 0xab, 0x5c, 0x2a, 0x54, 0xa9, 0x4b, 0x69, 0x43, 0x69, 0x43,
- 0x89, 0x4b, 0xca, 0x4b, 0x4c, 0x54, 0xee, 0x5c, 0xce, 0x5c, 0x88, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d,
- 0x4d, 0x6d, 0x66, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x83, 0x08, 0xcb, 0x21, 0xaa, 0x19, 0x8a, 0x19, 0x8a, 0x19, 0x8a, 0x19,
- 0xac, 0x21, 0xee, 0x21, 0x51, 0x2a, 0x52, 0x2a, 0x52, 0x2a, 0x8c, 0x21,
- 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x19,
- 0x2a, 0x6d, 0x89, 0x5c, 0x47, 0x43, 0xc4, 0x21, 0xe2, 0x10, 0x04, 0x2a,
- 0xa6, 0x32, 0x28, 0x43, 0x89, 0x4b, 0x89, 0x43, 0x08, 0x3b, 0x87, 0x32,
- 0xc5, 0x21, 0xc2, 0x10, 0x84, 0x21, 0x44, 0x19, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xc8, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe6, 0x10,
- 0xb1, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x50, 0x2a,
- 0x2f, 0x2a, 0xee, 0x21, 0x6b, 0x19, 0xc6, 0x10, 0x21, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, 0x10, 0xe6, 0x3a, 0xa9, 0x5c,
- 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x2c, 0x65,
- 0x0d, 0x65, 0xed, 0x64, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x6d, 0x54, 0x67, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54,
- 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x09, 0x3b,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x08, 0xc5, 0x10,
- 0xa4, 0x08, 0x63, 0x08, 0x21, 0x00, 0x84, 0x08, 0x28, 0x11, 0xcd, 0x21,
- 0x31, 0x2a, 0x32, 0x2a, 0xc7, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x81, 0x08, 0x68, 0x5c, 0xcb, 0x75, 0xab, 0x75, 0xac, 0x75, 0x4b, 0x6d,
- 0xe9, 0x4b, 0xc6, 0x3a, 0x45, 0x2a, 0x45, 0x2a, 0xe5, 0x29, 0x05, 0x2a,
- 0x26, 0x2a, 0x26, 0x2a, 0xa8, 0x32, 0xab, 0x4b, 0x8d, 0x5c, 0x88, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d,
- 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x6e, 0x54, 0xea, 0x3a, 0x41, 0x08,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0x19, 0x90, 0x2a, 0x70, 0x2a,
- 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x52, 0x2a, 0x31, 0x2a,
- 0x09, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x08, 0x68, 0x5c,
- 0x08, 0x54, 0x67, 0x43, 0x85, 0x32, 0xc6, 0x3a, 0x09, 0x54, 0xeb, 0x64,
- 0x6d, 0x6d, 0x4d, 0x6d, 0x4d, 0x6d, 0x4d, 0x6d, 0x2e, 0x65, 0x0e, 0x65,
- 0x6c, 0x54, 0x4a, 0x43, 0x26, 0x2a, 0x03, 0x11, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xae, 0x5c, 0x6e, 0x54, 0x6f, 0x54, 0xca, 0x3a, 0x61, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x83, 0x08, 0x2e, 0x22, 0x50, 0x2a, 0x2f, 0x2a, 0xed, 0x21,
- 0xac, 0x21, 0x6b, 0x19, 0x08, 0x19, 0x08, 0x11, 0x6b, 0x19, 0x21, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x63, 0x19, 0x09, 0x65, 0xab, 0x75, 0x8b, 0x6d,
- 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54,
- 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x6e, 0x54,
- 0x2e, 0x54, 0x0f, 0x4c, 0x0c, 0x3b, 0x61, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x63, 0x08, 0x28, 0x19, 0x8a, 0x19, 0xee, 0x21, 0x51, 0x2a, 0x51, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x32, 0x2a, 0x64, 0x08, 0x00, 0x00, 0x20, 0x00,
- 0x26, 0x43, 0xeb, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d,
- 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d,
- 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x6e, 0x54, 0x2e, 0x54, 0x0f, 0x4c,
- 0xd0, 0x4b, 0x2e, 0x3b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x08, 0x4f, 0x2a,
- 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a,
- 0x32, 0x2a, 0xe7, 0x10, 0x00, 0x00, 0x20, 0x00, 0x68, 0x5c, 0xcb, 0x75,
- 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xae, 0x5c, 0x6e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x90, 0x43,
- 0x2f, 0x3b, 0xa3, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0x21, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x31, 0x2a, 0x4b, 0x19,
- 0x00, 0x00, 0x20, 0x00, 0x8a, 0x6d, 0xab, 0x75, 0x8b, 0x6d, 0x8b, 0x6d,
- 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54,
- 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x6e, 0x54,
- 0x2e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x90, 0x43, 0x50, 0x43, 0x10, 0x3b,
- 0xa4, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xc5, 0x10, 0x50, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xae, 0x21, 0x00, 0x00, 0xa1, 0x10,
- 0x0b, 0x76, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d,
- 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d,
- 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x6e, 0x54, 0x2e, 0x54, 0x0f, 0x4c,
- 0xcf, 0x4b, 0x90, 0x43, 0x50, 0x43, 0x30, 0x3b, 0xcf, 0x32, 0x06, 0x19,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x50, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a,
- 0x11, 0x2a, 0x11, 0x2a, 0x82, 0x10, 0x83, 0x21, 0xeb, 0x75, 0xaa, 0x75,
- 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xae, 0x5c, 0x6e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x90, 0x43,
- 0x50, 0x43, 0x30, 0x3b, 0xf0, 0x3a, 0x90, 0x32, 0x27, 0x19, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xed, 0x21, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x12, 0x2a,
- 0xc5, 0x18, 0x64, 0x32, 0xeb, 0x75, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d,
- 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54,
- 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x6e, 0x54,
- 0x2e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x90, 0x43, 0x50, 0x43, 0x30, 0x3b,
- 0xf0, 0x3a, 0xb0, 0x32, 0x70, 0x32, 0x07, 0x11, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x6a, 0x19, 0x71, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x12, 0x2a, 0x27, 0x19, 0x05, 0x3b,
- 0xeb, 0x75, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d,
- 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d,
- 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x6e, 0x54, 0x2e, 0x54, 0x0f, 0x4c,
- 0xcf, 0x4b, 0x90, 0x43, 0x50, 0x43, 0x30, 0x3b, 0xf0, 0x3a, 0xb0, 0x32,
- 0x91, 0x32, 0x51, 0x2a, 0xa5, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x28, 0x11, 0x71, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a,
- 0x11, 0x2a, 0x11, 0x2a, 0x49, 0x21, 0xa6, 0x4b, 0xca, 0x75, 0xaa, 0x75,
- 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xae, 0x5c, 0x6e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x90, 0x43,
- 0x50, 0x43, 0x30, 0x3b, 0xf0, 0x3a, 0xb0, 0x32, 0x70, 0x32, 0x51, 0x32,
- 0x6b, 0x19, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x11, 0x71, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a,
- 0x8b, 0x21, 0x47, 0x54, 0xca, 0x75, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d,
- 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54,
- 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x6e, 0x54,
- 0x2e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x90, 0x43, 0x50, 0x43, 0x30, 0x3b,
- 0xf0, 0x3a, 0xb0, 0x32, 0x71, 0x32, 0x51, 0x32, 0xe7, 0x10, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x07, 0x11, 0x71, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xac, 0x29, 0x68, 0x5c,
- 0xca, 0x75, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d,
- 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d,
- 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x6e, 0x54, 0x2e, 0x54, 0x0f, 0x4c,
- 0xcf, 0x4b, 0x90, 0x43, 0x50, 0x43, 0x30, 0x3b, 0xf0, 0x3a, 0xb0, 0x32,
- 0x91, 0x32, 0x29, 0x19, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x49, 0x19, 0x71, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a,
- 0x11, 0x2a, 0x11, 0x2a, 0xcd, 0x29, 0xc8, 0x5c, 0xca, 0x75, 0xaa, 0x75,
- 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xae, 0x5c, 0x6e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x90, 0x43,
- 0x50, 0x43, 0x30, 0x3b, 0xf0, 0x3a, 0x8f, 0x32, 0x06, 0x11, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xac, 0x21, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xf1, 0x29,
- 0xee, 0x29, 0xc8, 0x5c, 0xca, 0x75, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d,
- 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54,
- 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x6e, 0x54,
- 0x2e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x90, 0x43, 0x50, 0x43, 0x30, 0x3b,
- 0x8d, 0x32, 0x62, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x2f, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xf1, 0x29, 0x0f, 0x32, 0xc8, 0x5c,
- 0xca, 0x75, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d,
- 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d,
- 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x6e, 0x54, 0x2e, 0x54, 0x0f, 0x4c,
- 0xcf, 0x4b, 0x90, 0x43, 0x70, 0x43, 0x0a, 0x2a, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x08,
- 0x50, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a,
- 0x11, 0x2a, 0xf1, 0x29, 0x0f, 0x32, 0xc8, 0x5c, 0xca, 0x75, 0xaa, 0x75,
- 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xae, 0x5c, 0x6e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x90, 0x43,
- 0xe4, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x19, 0x70, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xf1, 0x29,
- 0xee, 0x29, 0x68, 0x5c, 0xca, 0x75, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d,
- 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54,
- 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x6e, 0x54,
- 0x2e, 0x54, 0x30, 0x4c, 0xec, 0x3a, 0x82, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x2e, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xf1, 0x29, 0xcd, 0x29, 0x47, 0x54,
- 0xca, 0x75, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d,
- 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d,
- 0x2c, 0x65, 0xed, 0x64, 0xae, 0x5c, 0x6e, 0x54, 0x2f, 0x54, 0x69, 0x2a,
- 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x11, 0x70, 0x2a,
- 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a,
- 0x11, 0x2a, 0x11, 0x2a, 0xac, 0x29, 0xa6, 0x4b, 0xca, 0x75, 0xaa, 0x75,
- 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64,
- 0xae, 0x5c, 0x2d, 0x54, 0xa6, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x21, 0x00, 0x0d, 0x22, 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a,
- 0x8b, 0x29, 0x26, 0x43, 0xeb, 0x75, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d,
- 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54,
- 0xcb, 0x75, 0x6b, 0x6d, 0x2c, 0x65, 0xed, 0x64, 0x0c, 0x54, 0x81, 0x08,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x19,
- 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x69, 0x21, 0x84, 0x32,
- 0xeb, 0x75, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d,
- 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54, 0xcb, 0x75, 0x6b, 0x6d,
- 0x6d, 0x6d, 0xe8, 0x3a, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xe6, 0x10, 0x90, 0x32, 0x91, 0x32, 0x71, 0x2a,
- 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a,
- 0x11, 0x2a, 0x12, 0x2a, 0x28, 0x19, 0xa3, 0x21, 0xeb, 0x75, 0xaa, 0x75,
- 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x61, 0x08, 0x27, 0x54, 0xeb, 0x75, 0x4b, 0x65, 0xe4, 0x21, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc5, 0x10,
- 0x90, 0x32, 0xb1, 0x32, 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x12, 0x2a,
- 0xe5, 0x18, 0xc1, 0x10, 0x0b, 0x76, 0xaa, 0x75, 0x8b, 0x6d, 0x8b, 0x6d,
- 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x27, 0x54,
- 0xe9, 0x64, 0xa1, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc5, 0x10, 0xb1, 0x32, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x12, 0x2a, 0x83, 0x10, 0x20, 0x00,
- 0xaa, 0x6d, 0xab, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d,
- 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x81, 0x08, 0x83, 0x21, 0x61, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xca, 0x21,
- 0xd1, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x71, 0x2a,
- 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a,
- 0x11, 0x2a, 0xcf, 0x21, 0x00, 0x00, 0x20, 0x00, 0x68, 0x5c, 0xcb, 0x75,
- 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x62, 0x08, 0x6d, 0x2a, 0xf1, 0x32, 0xd0, 0x32, 0xb0, 0x32,
- 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x6c, 0x19,
- 0x00, 0x00, 0x20, 0x00, 0x46, 0x43, 0xeb, 0x75, 0x8b, 0x6d, 0x8b, 0x6d,
- 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x11, 0xd0, 0x32,
- 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x11, 0x2a, 0x32, 0x2a, 0xe8, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0xe4, 0x21, 0xeb, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d,
- 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xca, 0x21, 0x10, 0x33, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x71, 0x2a,
- 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x11, 0x2a,
- 0x32, 0x2a, 0x84, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0xab, 0x75,
- 0x8b, 0x6d, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x08, 0x8d, 0x2a, 0x11, 0x3b,
- 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32,
- 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0xf0, 0x21, 0x22, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x81, 0x08, 0x68, 0x5c, 0xab, 0x75, 0x8b, 0x6d,
- 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x05, 0x11, 0x0f, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32,
- 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x31, 0x2a, 0x6c, 0x19, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x20, 0x00, 0xe5, 0x3a, 0xcb, 0x75, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d,
- 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9, 0x21, 0x51, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x71, 0x2a,
- 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x32, 0x2a,
- 0xe7, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x21,
- 0xab, 0x75, 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x08,
- 0xcd, 0x32, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b,
- 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32,
- 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x10, 0x2a, 0x84, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x69, 0x5c, 0xab, 0x6d,
- 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x46, 0x19, 0x2f, 0x3b, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32,
- 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x31, 0x2a, 0x8c, 0x21, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0xe6, 0x3a, 0xab, 0x75, 0x6b, 0x6d, 0x4b, 0x6d,
- 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x09, 0x22,
- 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x71, 0x2a,
- 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x51, 0x2a, 0x08, 0x11,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x83, 0x21, 0x0a, 0x65, 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x82, 0x08, 0xcc, 0x32, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b,
- 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32,
- 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x51, 0x2a, 0xef, 0x21, 0x84, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0xe8, 0x4b,
- 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x19, 0x6f, 0x43,
- 0xb0, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32,
- 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a,
- 0x6b, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45, 0x2a, 0x4b, 0x6d, 0x6b, 0x6d,
- 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x08, 0x22, 0xf0, 0x4b, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43,
- 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x71, 0x2a,
- 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x0f, 0x2a, 0xc6, 0x10, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x81, 0x08, 0x49, 0x54, 0x6c, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x4d, 0x43, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b,
- 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32,
- 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0xad, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x85, 0x32, 0x2b, 0x65, 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x86, 0x19, 0x8e, 0x43, 0xcf, 0x4b, 0xaf, 0x4b, 0xaf, 0x43, 0x8f, 0x43,
- 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32,
- 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x30, 0x2a, 0xe6, 0x10,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0x5c,
- 0x4c, 0x6d, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x2a, 0xef, 0x4b, 0xef, 0x4b,
- 0xcf, 0x4b, 0xaf, 0x4b, 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43,
- 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x71, 0x2a,
- 0x71, 0x2a, 0x51, 0x2a, 0xcd, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc4, 0x21, 0x2b, 0x65, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x41, 0x08, 0xca, 0x32, 0x0f, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b,
- 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32,
- 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x50, 0x2a,
- 0x84, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xa8, 0x4b, 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xca, 0x32,
- 0x0f, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b, 0xaf, 0x43, 0x8f, 0x43,
- 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32,
- 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x71, 0x2a, 0x6a, 0x19, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x61, 0x08, 0xeb, 0x64, 0x2c, 0x65, 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xca, 0x32, 0x0f, 0x4c, 0xcf, 0x4b,
- 0xcf, 0x4b, 0xaf, 0x4b, 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43,
- 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x91, 0x2a,
- 0x2f, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x21,
- 0x4c, 0x6d, 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x41, 0x08, 0xca, 0x32, 0x0f, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b,
- 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32,
- 0xb0, 0x32, 0x91, 0x32, 0x91, 0x32, 0x91, 0x32, 0x83, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc7, 0x3a, 0x4d, 0x6d,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xca, 0x32,
- 0x0f, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b, 0xaf, 0x43, 0x8f, 0x43,
- 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32,
- 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32,
- 0xb1, 0x32, 0x07, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x88, 0x43, 0x4d, 0x6d, 0x0d, 0x65,
- 0xed, 0x64, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xca, 0x32, 0x0f, 0x4c, 0xcf, 0x4b,
- 0xcf, 0x4b, 0xaf, 0x4b, 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43,
- 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x8a, 0x21, 0x21, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xa2, 0x10, 0x0a, 0x54, 0x2d, 0x65, 0xed, 0x64, 0xcd, 0x5c,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x41, 0x08, 0xca, 0x32, 0x0f, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b,
- 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32,
- 0xb1, 0x32, 0xec, 0x21, 0x42, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x03, 0x11, 0x2b, 0x54, 0x0d, 0x65, 0xcd, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xca, 0x32,
- 0x0f, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b, 0xaf, 0x43, 0x8f, 0x43,
- 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32,
- 0xd0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb1, 0x32, 0x2d, 0x2a, 0x63, 0x08,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x19,
- 0x4b, 0x54, 0xed, 0x64, 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xca, 0x32, 0x0f, 0x4c, 0xcf, 0x4b,
- 0xcf, 0x4b, 0xaf, 0x4b, 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43,
- 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd1, 0x32, 0x4e, 0x2a, 0x63, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x10, 0x4c, 0x54,
- 0xcd, 0x5c, 0xad, 0x5c, 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x41, 0x08, 0xca, 0x32, 0x0f, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b,
- 0xf0, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0x4e, 0x2a, 0x42, 0x08,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xaa, 0x4b, 0xce, 0x5c,
- 0x8d, 0x5c, 0x67, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xca, 0x32,
- 0x0f, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b, 0xaf, 0x43, 0x8f, 0x43,
- 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xf0, 0x32,
- 0xf1, 0x32, 0x0c, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 0x32, 0x8d, 0x5c, 0x67, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xca, 0x32, 0x0f, 0x4c, 0xcf, 0x4b,
- 0xcf, 0x4b, 0xaf, 0x4b, 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43,
- 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b,
- 0x10, 0x3b, 0x10, 0x3b, 0x10, 0x33, 0xf1, 0x32, 0x47, 0x19, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xe3, 0x10, 0xc5, 0x21, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x41, 0x08, 0xca, 0x32, 0x0f, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x31, 0x3b,
- 0x6d, 0x2a, 0x83, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xca, 0x32,
- 0x0f, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b, 0xaf, 0x43, 0x8f, 0x43,
- 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x31, 0x3b, 0xcf, 0x32, 0x47, 0x19, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0xca, 0x32, 0x0f, 0x4c, 0xcf, 0x4b,
- 0xcf, 0x4b, 0xaf, 0x4b, 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43,
- 0x70, 0x43, 0x70, 0x43, 0x50, 0x43, 0x50, 0x3b, 0xce, 0x32, 0x88, 0x19,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x41, 0x08, 0xca, 0x32, 0x0f, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x90, 0x43, 0x70, 0x43,
- 0x2a, 0x2a, 0x62, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x65, 0x19,
- 0x69, 0x2a, 0xaa, 0x32, 0xcb, 0x32, 0xcb, 0x32, 0x8b, 0x32, 0x29, 0x2a,
- 0xa7, 0x21, 0x04, 0x11, 0x82, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2020, Baikal Electronics, JSC. All rights reserved.
- *
- * Author: Pavel Parkhomenko <pavel.parkhomenko@baikalelectronics.ru>
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/*
- * To change a logo, replace array contents below with a BMP file dump.
- * Source BMP file have to be of 16-bpp color format (RGB565).
- * Optimal size is 54x54 pixels (or 48x63 pixels for wide displays).
- */
-
-#if !DEBUG
-const unsigned char bl1_logo[] = {
- 0x42, 0x4d, 0x52, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0x00,
- 0x00, 0x00, 0x7c, 0x00, 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x36, 0x00,
- 0x00, 0x00, 0x01, 0x00, 0x10, 0x00, 0x03, 0x00, 0x00, 0x00, 0xc8, 0x16,
- 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xe0, 0x07,
- 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x47,
- 0x52, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
- 0x82, 0x08, 0x82, 0x08, 0x62, 0x08, 0x62, 0x08, 0xe4, 0x10, 0x66, 0x21,
- 0x29, 0x2a, 0x08, 0x22, 0xc3, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc3, 0x10,
- 0xc6, 0x21, 0xc7, 0x21, 0x86, 0x21, 0x65, 0x19, 0x04, 0x11, 0xa3, 0x10,
- 0xc3, 0x10, 0x66, 0x19, 0xe8, 0x21, 0xe8, 0x21, 0xa7, 0x21, 0xa8, 0x21,
- 0xa7, 0x19, 0xa8, 0x21, 0x47, 0x19, 0x82, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x24, 0x19, 0xe9, 0x3a, 0xcc, 0x4b, 0x2d, 0x4c, 0xcd, 0x4b,
- 0xad, 0x43, 0x8d, 0x43, 0x8d, 0x43, 0xae, 0x43, 0x6d, 0x43, 0xab, 0x32,
- 0xa7, 0x21, 0x82, 0x08, 0x41, 0x08, 0x41, 0x08, 0x21, 0x00, 0x20, 0x00,
- 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x09, 0x3b,
- 0x87, 0x32, 0x43, 0x19, 0x82, 0x08, 0x41, 0x08, 0x21, 0x00, 0x20, 0x00,
- 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x21, 0x00, 0x41, 0x08, 0x61, 0x08,
- 0xc4, 0x10, 0xc7, 0x21, 0xab, 0x32, 0x0d, 0x3b, 0x6f, 0x3b, 0x91, 0x43,
- 0x70, 0x3b, 0x71, 0x43, 0x10, 0x3b, 0xcf, 0x32, 0x2b, 0x2a, 0x88, 0x21,
- 0xc4, 0x08, 0x42, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc2, 0x10, 0x46, 0x2a, 0xc5, 0x21, 0x64, 0x21,
- 0x64, 0x21, 0xa5, 0x21, 0x88, 0x32, 0x47, 0x2a, 0x28, 0x2a, 0x68, 0x32,
- 0x48, 0x32, 0x48, 0x32, 0x48, 0x2a, 0x28, 0x2a, 0x28, 0x2a, 0x49, 0x2a,
- 0x66, 0x19, 0x24, 0x11, 0x05, 0x19, 0x05, 0x11, 0x46, 0x19, 0x46, 0x19,
- 0x46, 0x19, 0x46, 0x19, 0x25, 0x11, 0xe4, 0x10, 0xe5, 0x10, 0xc5, 0x10,
- 0x26, 0x11, 0x48, 0x19, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x43, 0x19, 0xe5, 0x29, 0x46, 0x2a, 0xe9, 0x3a,
- 0x0c, 0x4c, 0xce, 0x5c, 0x8b, 0x4b, 0x89, 0x32, 0x27, 0x22, 0x61, 0x08,
- 0x21, 0x00, 0x21, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x24, 0x11,
- 0xd0, 0x4b, 0x2e, 0x3b, 0x2a, 0x2a, 0xa7, 0x21, 0x25, 0x19, 0x05, 0x11,
- 0x05, 0x11, 0x05, 0x11, 0x47, 0x11, 0x88, 0x19, 0x2a, 0x22, 0xaf, 0x32,
- 0x11, 0x33, 0x2c, 0x2a, 0x89, 0x21, 0x27, 0x11, 0x63, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x03, 0x11, 0x69, 0x43, 0xe8, 0x42, 0x87, 0x32, 0x06, 0x2a, 0x44, 0x11,
- 0x61, 0x08, 0x20, 0x00, 0x04, 0x19, 0xe5, 0x21, 0x03, 0x11, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xe4, 0x10, 0x87, 0x21, 0xe8, 0x21, 0x09, 0x22,
- 0x09, 0x22, 0xe9, 0x21, 0xc8, 0x21, 0x47, 0x19, 0xa3, 0x08, 0x41, 0x08,
- 0x21, 0x00, 0xc4, 0x08, 0x47, 0x19, 0x89, 0x21, 0x8a, 0x19, 0x21, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00,
- 0x46, 0x32, 0x45, 0x32, 0xe5, 0x29, 0x05, 0x22, 0x05, 0x22, 0x87, 0x32,
- 0xc8, 0x3a, 0x09, 0x3b, 0xa9, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x25, 0x19, 0xa7, 0x21, 0xa7, 0x19, 0x66, 0x19,
- 0x67, 0x19, 0x66, 0x19, 0x47, 0x19, 0x47, 0x19, 0xa9, 0x21, 0xea, 0x21,
- 0xeb, 0x21, 0xea, 0x21, 0xcb, 0x21, 0xcb, 0x21, 0xab, 0x21, 0xcb, 0x21,
- 0x49, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x43, 0x8e, 0x75,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x64, 0x4e, 0x65, 0x0e, 0x65, 0xce, 0x5c,
- 0xab, 0x4b, 0x47, 0x2a, 0x61, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x67, 0x19, 0x50, 0x43,
- 0x51, 0x43, 0x51, 0x43, 0x51, 0x43, 0x51, 0x3b, 0xf0, 0x3a, 0x2c, 0x2a,
- 0x68, 0x19, 0xa3, 0x08, 0x21, 0x00, 0x21, 0x00, 0x41, 0x00, 0x41, 0x00,
- 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa1, 0x08, 0x81, 0x08, 0x61, 0x08,
- 0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x41, 0x08, 0xe3, 0x10,
- 0x07, 0x22, 0xe6, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x41, 0x08, 0x41, 0x08, 0x41, 0x00, 0xa4, 0x10, 0x88, 0x21,
- 0x2d, 0x2a, 0xd1, 0x32, 0xd2, 0x3a, 0xf2, 0x3a, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0xb2, 0x2a, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc2, 0x10, 0x29, 0x54, 0xc9, 0x4b, 0x88, 0x43,
- 0x28, 0x3b, 0x28, 0x3b, 0x29, 0x43, 0x69, 0x43, 0xaa, 0x4b, 0x8a, 0x4b,
- 0x8b, 0x43, 0xa2, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x62, 0x08, 0x4b, 0x2a, 0x8d, 0x32, 0x6c, 0x2a, 0x6d, 0x2a, 0x4d, 0x2a,
- 0x0b, 0x22, 0x89, 0x21, 0x48, 0x19, 0x48, 0x19, 0x48, 0x11, 0x28, 0x11,
- 0x28, 0x11, 0x28, 0x19, 0x49, 0x19, 0x84, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0xe4, 0x29, 0x47, 0x43, 0x09, 0x4c, 0x6b, 0x54,
- 0xcc, 0x5c, 0xac, 0x5c, 0x6c, 0x54, 0x0b, 0x4c, 0x49, 0x43, 0x67, 0x32,
- 0x44, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x6c, 0x2a, 0x88, 0x21, 0xc4, 0x08,
- 0x41, 0x08, 0xc5, 0x10, 0x68, 0x19, 0xaa, 0x19, 0xca, 0x21, 0xcb, 0x21,
- 0xaa, 0x19, 0x8a, 0x19, 0x49, 0x11, 0xa4, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xe6, 0x3a, 0x8c, 0x6d, 0x8a, 0x5c, 0x88, 0x4b, 0x07, 0x3b,
- 0xa7, 0x32, 0xa7, 0x32, 0xa8, 0x3a, 0xe8, 0x3a, 0xaa, 0x4b, 0x6d, 0x54,
- 0x6d, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xae, 0x32, 0x31, 0x3b,
- 0x11, 0x3b, 0xb0, 0x2a, 0x2c, 0x22, 0xcb, 0x21, 0x8a, 0x19, 0x48, 0x19,
- 0x6a, 0x19, 0x8a, 0x19, 0xcc, 0x21, 0x30, 0x22, 0x29, 0x11, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xc1, 0x10, 0x87, 0x43, 0x47, 0x43, 0xe9, 0x4b, 0x6a, 0x54, 0x8a, 0x5c,
- 0x6b, 0x54, 0x6b, 0x54, 0x6c, 0x54, 0x4c, 0x54, 0xcb, 0x4b, 0x29, 0x3b,
- 0xe6, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x64, 0x32, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xa9, 0x19, 0xca, 0x21, 0xa9, 0x19, 0xaa, 0x21, 0x8a, 0x19, 0xaa, 0x19,
- 0x8a, 0x19, 0x8a, 0x19, 0x6a, 0x19, 0x6a, 0x19, 0x6b, 0x19, 0x22, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x28, 0x54, 0x47, 0x43, 0xc4, 0x29, 0xe4, 0x29, 0xe5, 0x29, 0x25, 0x2a,
- 0x45, 0x2a, 0x45, 0x2a, 0x25, 0x2a, 0xc5, 0x21, 0xa5, 0x21, 0xc5, 0x21,
- 0x44, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6a, 0x7e, 0x67, 0x43, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x62, 0x08, 0x4d, 0x2a, 0xf2, 0x3a, 0xb1, 0x32, 0xb1, 0x32, 0xb1, 0x2a,
- 0x91, 0x2a, 0x91, 0x32, 0x71, 0x32, 0x71, 0x2a, 0xcd, 0x21, 0x84, 0x08,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x19,
- 0x47, 0x43, 0xca, 0x5c, 0xac, 0x75, 0x6d, 0x65, 0x4d, 0x6d, 0x2c, 0x65,
- 0x2c, 0x65, 0x0d, 0x6d, 0xed, 0x64, 0x0d, 0x65, 0xed, 0x64, 0x0f, 0x65,
- 0x2a, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x4b, 0x7e, 0xac, 0x6d, 0xcc, 0x5c,
- 0x61, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x41, 0x00, 0xe6, 0x10, 0xe6, 0x10, 0x07, 0x11,
- 0xe6, 0x10, 0xc6, 0x10, 0xc6, 0x10, 0xe6, 0x10, 0x8c, 0x21, 0x73, 0x2a,
- 0x21, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x43,
- 0x29, 0x54, 0xe8, 0x4b, 0xc8, 0x4b, 0xc9, 0x4b, 0xc9, 0x4b, 0xc9, 0x4b,
- 0xc9, 0x4b, 0xa9, 0x4b, 0x89, 0x43, 0x8a, 0x43, 0x6a, 0x43, 0x4a, 0x43,
- 0x47, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6b, 0x6d, 0x4c, 0x65,
- 0x0d, 0x65, 0x47, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x11, 0x6f, 0x2a, 0x2e, 0x2a,
- 0x0e, 0x2a, 0xed, 0x21, 0xcd, 0x21, 0xcd, 0x19, 0x8c, 0x19, 0x8c, 0x21,
- 0x2a, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x21, 0x8b, 0x75,
- 0x6a, 0x6d, 0xac, 0x75, 0x6b, 0x6d, 0x49, 0x54, 0x48, 0x43, 0x08, 0x43,
- 0xe7, 0x3a, 0xc7, 0x3a, 0xe8, 0x3a, 0xe8, 0x3a, 0xaa, 0x4b, 0xce, 0x5c,
- 0x4a, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x2c, 0x65,
- 0xed, 0x64, 0xad, 0x5c, 0xed, 0x4b, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x08, 0x4e, 0x22,
- 0x4f, 0x2a, 0x50, 0x2a, 0x71, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x52, 0x2a,
- 0xf0, 0x29, 0x22, 0x08, 0x00, 0x00, 0x00, 0x00, 0x24, 0x2a, 0x66, 0x4b,
- 0x26, 0x3b, 0x06, 0x3b, 0x67, 0x43, 0xaa, 0x5c, 0x6c, 0x6d, 0x6d, 0x6d,
- 0x6d, 0x6d, 0x4d, 0x6d, 0x4d, 0x65, 0x0e, 0x65, 0x2c, 0x54, 0x09, 0x43,
- 0xc5, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x2c, 0x65,
- 0xed, 0x64, 0x8d, 0x54, 0x4e, 0x54, 0x70, 0x54, 0x65, 0x19, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x08,
- 0x70, 0x2a, 0x0e, 0x22, 0xab, 0x21, 0x49, 0x19, 0x49, 0x19, 0x29, 0x19,
- 0x8c, 0x19, 0xe7, 0x10, 0x00, 0x00, 0x40, 0x08, 0x08, 0x54, 0xcb, 0x75,
- 0xcb, 0x75, 0xab, 0x6d, 0x8c, 0x6d, 0x4c, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xee, 0x5c,
- 0x4a, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x2c, 0x65,
- 0xed, 0x64, 0x8d, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0x10, 0x4c, 0x4a, 0x2a,
- 0x61, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x83, 0x08, 0x50, 0x2a, 0x50, 0x2a, 0x72, 0x2a, 0x52, 0x2a, 0x52, 0x2a,
- 0x32, 0x2a, 0x6b, 0x19, 0x00, 0x00, 0x81, 0x08, 0x8a, 0x6d, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x2c, 0x65,
- 0xed, 0x64, 0x8d, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x8f, 0x43,
- 0x0f, 0x3b, 0xe5, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x21, 0x00, 0x0e, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0xcf, 0x21, 0x21, 0x00, 0xe2, 0x10, 0x4b, 0x7e, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x2c, 0x65,
- 0xed, 0x64, 0x8d, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x70, 0x43,
- 0x50, 0x43, 0x52, 0x43, 0x69, 0x19, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x49, 0x19, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x32, 0x2a, 0x42, 0x08, 0x24, 0x2a, 0x0b, 0x76, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x2c, 0x65,
- 0xed, 0x64, 0x8d, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x70, 0x43,
- 0x50, 0x43, 0xf0, 0x3a, 0xf2, 0x3a, 0x2e, 0x2a, 0x84, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xe6, 0x10, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x33, 0x2a, 0x84, 0x08, 0x65, 0x43, 0xea, 0x75, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x2c, 0x65,
- 0xed, 0x64, 0x8d, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x70, 0x43,
- 0x50, 0x43, 0x10, 0x3b, 0xb0, 0x32, 0x90, 0x32, 0x72, 0x32, 0x43, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x84, 0x08, 0x50, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x32, 0x2a, 0xe8, 0x10, 0x28, 0x54, 0xca, 0x75, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x2c, 0x65,
- 0xed, 0x64, 0x8d, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x70, 0x43,
- 0x50, 0x43, 0x10, 0x3b, 0xb0, 0x32, 0x90, 0x32, 0x72, 0x32, 0x09, 0x11,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x63, 0x08, 0x50, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x32, 0x2a, 0x2a, 0x19, 0xa8, 0x5c, 0xca, 0x75, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x2c, 0x65,
- 0xed, 0x64, 0x8d, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x70, 0x43,
- 0x50, 0x43, 0x10, 0x3b, 0xd1, 0x3a, 0x70, 0x2a, 0x08, 0x11, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xa4, 0x10, 0x50, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x11, 0x2a, 0x6c, 0x19, 0xc8, 0x5c, 0xca, 0x75, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x2c, 0x65,
- 0xed, 0x64, 0x8d, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x6f, 0x43,
- 0x50, 0x43, 0x51, 0x43, 0x89, 0x19, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x28, 0x11, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x11, 0x2a, 0xad, 0x21, 0xc8, 0x5c, 0xca, 0x75, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x2c, 0x65,
- 0xed, 0x64, 0x8d, 0x5c, 0x4e, 0x54, 0x0f, 0x4c, 0xcf, 0x4b, 0x90, 0x43,
- 0xee, 0x3a, 0x83, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xac, 0x21, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x11, 0x2a, 0xad, 0x21, 0xc8, 0x5c, 0xca, 0x75, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x2c, 0x65,
- 0xed, 0x64, 0x8d, 0x5c, 0x4e, 0x54, 0x50, 0x54, 0x2d, 0x3b, 0x87, 0x19,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x63, 0x08, 0x92, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x11, 0x2a, 0x6c, 0x19, 0x28, 0x54, 0xca, 0x75, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x2c, 0x65,
- 0xed, 0x64, 0xad, 0x5c, 0xd0, 0x5c, 0xa5, 0x21, 0x21, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x70, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x31, 0x2a, 0x4b, 0x19, 0x66, 0x4b, 0xea, 0x75, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x7e, 0x6c, 0x6d, 0x4c, 0x65,
- 0xcd, 0x64, 0x6b, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2d, 0x2a,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x32, 0x2a, 0x08, 0x11, 0x44, 0x32, 0x0b, 0x76, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x6b, 0x86, 0xcc, 0x75, 0xa8, 0x4b,
- 0x64, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x22, 0xb1, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x32, 0x2a, 0x85, 0x08, 0xe2, 0x10, 0x6b, 0x7e, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc1, 0x10, 0x8b, 0x7e, 0x63, 0x19, 0x20, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc5, 0x10, 0xb1, 0x2a, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x33, 0x2a, 0x42, 0x08, 0x81, 0x08, 0x8a, 0x6d, 0x8b, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x62, 0x08, 0x0c, 0x2a, 0xf2, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0xcf, 0x29, 0x21, 0x00, 0x40, 0x08, 0x48, 0x54, 0xab, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x00, 0xa9, 0x21,
- 0xf0, 0x32, 0xf1, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x6c, 0x19, 0x00, 0x00, 0x00, 0x00, 0x06, 0x3b, 0xab, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x67, 0x19, 0xf0, 0x3a, 0xf1, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x11, 0x2a, 0x08, 0x11, 0x00, 0x00, 0x00, 0x00, 0x63, 0x21, 0x6a, 0x6d,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xa3, 0x08, 0x10, 0x3b, 0x31, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0x10, 0x2a, 0x63, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x65,
- 0x8b, 0x6d, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc4, 0x10,
- 0x2a, 0x2a, 0x71, 0x43, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a,
- 0xce, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc3, 0x21,
- 0xeb, 0x75, 0x6b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x2a, 0x4f, 0x43,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x73, 0x2a,
- 0x63, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xea, 0x64, 0x8b, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x05, 0x11, 0xd1, 0x4b, 0x90, 0x43, 0x50, 0x3b,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x32, 0x2a, 0xad, 0x21,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x22, 0x11, 0xab, 0x6d, 0x4b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x45, 0x19, 0xed, 0x3a, 0xd1, 0x4b, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x31, 0x2a, 0x42, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x67, 0x43, 0x6b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0x2d, 0x3b,
- 0xaf, 0x4b, 0xaf, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x51, 0x2a, 0x4a, 0x19, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x81, 0x08, 0x2b, 0x6d, 0x4b, 0x6d, 0x4c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe7, 0x21, 0x30, 0x4c, 0xcf, 0x4b,
- 0xaf, 0x43, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a, 0x30, 0x2a, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x83, 0x21, 0xad, 0x75, 0x2c, 0x65, 0x2c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0xb2, 0x54, 0xcf, 0x4b, 0xcf, 0x4b,
- 0xaf, 0x4b, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x71, 0x2a, 0x92, 0x32, 0x63, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x21, 0xad, 0x6d, 0x0c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0x51, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b,
- 0xaf, 0x4b, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb1, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0xb2, 0x2a, 0x84, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x32, 0x4c, 0x65,
- 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0x51, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b,
- 0xaf, 0x4b, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32,
- 0x91, 0x32, 0x27, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0x32,
- 0x8e, 0x6d, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0x51, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b,
- 0xaf, 0x4b, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb0, 0x32, 0xd2, 0x32,
- 0x27, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x43, 0x19, 0x4e, 0x6d, 0xed, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0x51, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b,
- 0xaf, 0x4b, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0xb2, 0x32, 0xa4, 0x08,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x43, 0x19, 0xac, 0x5c, 0xed, 0x5c, 0xcd, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0x51, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b,
- 0xaf, 0x4b, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32, 0x90, 0x2a, 0x84, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x08, 0x3b, 0xed, 0x5c, 0xce, 0x5c,
- 0x29, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0x51, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b,
- 0xaf, 0x4b, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32,
- 0xf0, 0x32, 0xd1, 0x32, 0xaa, 0x19, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x10, 0x2c, 0x54,
- 0x8b, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0x51, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b,
- 0xaf, 0x4b, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x30, 0x3b, 0x10, 0x3b, 0x52, 0x3b,
- 0x8e, 0x2a, 0x62, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0xa2, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0x51, 0x4c, 0xcf, 0x4b, 0xcf, 0x4b,
- 0xaf, 0x4b, 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x70, 0x43,
- 0x50, 0x3b, 0x50, 0x3b, 0x30, 0x3b, 0x0f, 0x3b, 0xae, 0x2a, 0xa4, 0x08,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0x71, 0x54, 0xef, 0x4b, 0xcf, 0x4b,
- 0xcf, 0x4b, 0xaf, 0x43, 0xb0, 0x43, 0xb1, 0x43, 0xb1, 0x43, 0xd2, 0x4b,
- 0x2f, 0x3b, 0x6c, 0x2a, 0xa9, 0x21, 0xa3, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x0b, 0x3b, 0x0c, 0x3b, 0x2c, 0x3b,
- 0x2c, 0x3b, 0xec, 0x3a, 0x8b, 0x2a, 0x09, 0x22, 0x26, 0x19, 0x82, 0x08,
- 0x41, 0x08, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2020, Baikal Electronics, JSC. All rights reserved.
- *
- * Author: Pavel Parkhomenko <pavel.parkhomenko@baikalelectronics.ru>
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/*
- * To change a logo, replace array contents below with a BMP file dump.
- * Source BMP file have to be of 16-bpp color format (RGB565).
- * Optimal size is 72x72 pixels (or 64x84 pixels for wide displays).
- */
-#if !DEBUG
-const unsigned char bl1_logo[] = {
- 0x42, 0x4d, 0xe6, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x00,
- 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x3f, 0x00,
- 0x00, 0x00, 0x01, 0x00, 0x10, 0x00, 0x03, 0x00, 0x00, 0x00, 0xa0, 0x17,
- 0x00, 0x00, 0x46, 0x5c, 0x00, 0x00, 0x46, 0x5c, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xe0, 0x07,
- 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08,
- 0x82, 0x08, 0x82, 0x08, 0x82, 0x08, 0xc3, 0x10, 0x04, 0x11, 0xa7, 0x21,
- 0x86, 0x21, 0x61, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x21,
- 0x89, 0x32, 0x69, 0x2a, 0x29, 0x2a, 0x08, 0x2a, 0x45, 0x19, 0x00, 0x00,
- 0x21, 0x08, 0x45, 0x19, 0xa8, 0x21, 0xc8, 0x21, 0xc8, 0x21, 0xc8, 0x21,
- 0x26, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x24, 0x11, 0x2a, 0x43, 0x47, 0x2a, 0x64, 0x19, 0xe3, 0x10,
- 0xe3, 0x10, 0xc3, 0x10, 0x04, 0x11, 0xa6, 0x21, 0x8a, 0x32, 0x2d, 0x43,
- 0x8a, 0x32, 0xc7, 0x21, 0x25, 0x19, 0xc4, 0x10, 0xa3, 0x10, 0xa3, 0x10,
- 0xe5, 0x10, 0x83, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08,
- 0xa2, 0x08, 0x41, 0x00, 0x21, 0x08, 0xc6, 0x21, 0xc9, 0x3a, 0x4c, 0x3b,
- 0x4c, 0x43, 0x4c, 0x3b, 0xeb, 0x3a, 0x08, 0x22, 0x83, 0x08, 0x00, 0x00,
- 0x41, 0x00, 0x82, 0x10, 0xc4, 0x10, 0xe4, 0x10, 0xe4, 0x10, 0xe5, 0x10,
- 0xc4, 0x10, 0xa3, 0x10, 0x82, 0x08, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x21,
- 0x2a, 0x3b, 0xc9, 0x3a, 0xa8, 0x32, 0x27, 0x2a, 0xc6, 0x21, 0x85, 0x21,
- 0x65, 0x19, 0x65, 0x19, 0x86, 0x19, 0xe7, 0x21, 0x08, 0x2a, 0x49, 0x2a,
- 0x4a, 0x2a, 0x29, 0x2a, 0xc8, 0x21, 0xc8, 0x21, 0x87, 0x21, 0xa8, 0x21,
- 0xa8, 0x21, 0xc9, 0x21, 0xeb, 0x21, 0xea, 0x21, 0xaa, 0x21, 0x06, 0x11,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa4, 0x21, 0x87, 0x2a, 0x84, 0x19,
- 0xa2, 0x08, 0x20, 0x00, 0x61, 0x08, 0x03, 0x11, 0xe6, 0x29, 0x27, 0x2a,
- 0x48, 0x32, 0x48, 0x2a, 0xc6, 0x21, 0x04, 0x19, 0x62, 0x08, 0x20, 0x00,
- 0x82, 0x08, 0x04, 0x11, 0xa8, 0x21, 0x2a, 0x22, 0x2a, 0x22, 0x0a, 0x22,
- 0xc9, 0x21, 0x26, 0x19, 0x83, 0x08, 0x21, 0x00, 0x41, 0x00, 0x41, 0x00,
- 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x41, 0x00, 0x87, 0x2a, 0x29, 0x43, 0x0c, 0x4c,
- 0x4c, 0x54, 0x6e, 0x54, 0x2a, 0x3b, 0xa5, 0x21, 0x41, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x21, 0x6f, 0x43,
- 0x6e, 0x43, 0x0d, 0x3b, 0x4a, 0x2a, 0xc8, 0x21, 0xa8, 0x19, 0xa8, 0x19,
- 0xe9, 0x21, 0x6d, 0x2a, 0xaf, 0x3a, 0xcf, 0x3a, 0x4d, 0x32, 0x47, 0x11,
- 0x84, 0x08, 0x42, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x20, 0x00, 0x05, 0x2a, 0x48, 0x3b, 0xc7, 0x3a, 0x87, 0x32, 0xe5, 0x21,
- 0x23, 0x19, 0xc3, 0x10, 0x23, 0x19, 0x88, 0x32, 0xe3, 0x10, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x21, 0x00, 0x66, 0x19, 0xc8, 0x21, 0x09, 0x22, 0x09, 0x22, 0xe9, 0x21,
- 0xc9, 0x21, 0x67, 0x19, 0xe5, 0x10, 0x83, 0x08, 0xa4, 0x08, 0x27, 0x11,
- 0x8a, 0x19, 0x69, 0x19, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x22, 0x11, 0x43, 0x19, 0x44, 0x19, 0x05, 0x2a, 0x09, 0x3b,
- 0x0d, 0x54, 0x6d, 0x5c, 0x2d, 0x4c, 0x82, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x66, 0x11, 0x86, 0x21, 0xe4, 0x10, 0xc3, 0x10, 0xc4, 0x10,
- 0x25, 0x11, 0xca, 0x21, 0xad, 0x2a, 0xcf, 0x32, 0xd0, 0x32, 0x6e, 0x2a,
- 0xa9, 0x21, 0x47, 0x19, 0xe6, 0x10, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08,
- 0xe7, 0x3a, 0x89, 0x4b, 0xea, 0x53, 0x49, 0x43, 0xa8, 0x32, 0x44, 0x19,
- 0x41, 0x08, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc3, 0x10, 0x4a, 0x2a, 0xac, 0x32, 0x4b, 0x2a,
- 0xea, 0x21, 0x05, 0x11, 0x41, 0x00, 0x20, 0x00, 0x62, 0x08, 0x48, 0x19,
- 0x0c, 0x22, 0x6f, 0x2a, 0x70, 0x2a, 0xcc, 0x21, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x19,
- 0xc6, 0x3a, 0x45, 0x32, 0x46, 0x2a, 0x46, 0x32, 0x87, 0x32, 0x08, 0x3b,
- 0xeb, 0x4b, 0x6a, 0x43, 0x61, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x19, 0xa8, 0x21, 0x67, 0x19,
- 0xa8, 0x21, 0xc9, 0x21, 0x6d, 0x2a, 0xae, 0x32, 0x6d, 0x2a, 0xeb, 0x29,
- 0x69, 0x19, 0x48, 0x19, 0x27, 0x19, 0x48, 0x19, 0x49, 0x19, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc4, 0x29, 0x6a, 0x5c,
- 0xac, 0x5c, 0xac, 0x5c, 0xac, 0x5c, 0x8c, 0x5c, 0x6c, 0x5c, 0x29, 0x3b,
- 0x64, 0x21, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x08, 0x2f, 0x3b,
- 0xce, 0x32, 0x6d, 0x2a, 0x47, 0x19, 0x41, 0x00, 0x21, 0x00, 0xa3, 0x10,
- 0x48, 0x19, 0xcb, 0x21, 0xcb, 0x21, 0xab, 0x21, 0x6a, 0x19, 0x01, 0x08,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x08, 0xaa, 0x5c, 0x69, 0x54,
- 0x47, 0x43, 0xc7, 0x3a, 0xc7, 0x32, 0xe8, 0x3a, 0xa9, 0x4b, 0x6d, 0x5c,
- 0x8e, 0x5c, 0xa5, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x08,
- 0x4c, 0x2a, 0xcf, 0x32, 0xf0, 0x32, 0xd0, 0x32, 0xb0, 0x32, 0x6e, 0x2a,
- 0xca, 0x21, 0x48, 0x11, 0x27, 0x11, 0x28, 0x11, 0x4a, 0x19, 0xac, 0x19,
- 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc4, 0x21, 0xa6, 0x32, 0x07, 0x3b,
- 0x89, 0x4b, 0xc9, 0x4b, 0xa9, 0x4b, 0x89, 0x43, 0x09, 0x3b, 0x87, 0x32,
- 0x26, 0x2a, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x67, 0x19, 0x89, 0x21, 0x47, 0x19, 0x26, 0x19, 0x47, 0x19,
- 0x89, 0x19, 0x8a, 0x19, 0x8a, 0x21, 0x8b, 0x21, 0x49, 0x19, 0x08, 0x11,
- 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc2, 0x10, 0x4b, 0x65, 0xca, 0x5c, 0xe6, 0x3a,
- 0xe4, 0x21, 0x23, 0x19, 0x23, 0x19, 0xa4, 0x21, 0x66, 0x2a, 0xca, 0x4b,
- 0x4d, 0x54, 0x61, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x63, 0x08, 0xcf, 0x32, 0x11, 0x3b, 0xaf, 0x2a, 0x8e, 0x2a,
- 0x4e, 0x2a, 0x4e, 0x2a, 0x2e, 0x22, 0x2e, 0x22, 0x0e, 0x22, 0x0e, 0x22,
- 0xee, 0x21, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x81, 0x08, 0x63, 0x21, 0xe6, 0x3a, 0xe9, 0x53,
- 0x4a, 0x54, 0x8b, 0x5c, 0x6c, 0x5c, 0x2b, 0x54, 0xca, 0x4b, 0xc8, 0x32,
- 0x44, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x61, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x08, 0x05, 0x19, 0xca, 0x21,
- 0x2d, 0x2a, 0x6e, 0x2a, 0x6f, 0x2a, 0x2f, 0x2a, 0x0d, 0x22, 0x8a, 0x21,
- 0xc7, 0x10, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xa1, 0x10, 0xea, 0x64, 0x6c, 0x75, 0xe8, 0x4b, 0xc6, 0x32,
- 0x65, 0x32, 0x45, 0x2a, 0x25, 0x2a, 0x46, 0x2a, 0x67, 0x32, 0x49, 0x43,
- 0x6a, 0x43, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x27, 0x54, 0x44, 0x2a, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x08, 0x0b, 0x22, 0x0b, 0x22,
- 0xaa, 0x19, 0x69, 0x19, 0x69, 0x19, 0x69, 0x19, 0x6a, 0x19, 0xac, 0x21,
- 0x10, 0x2a, 0xed, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x04, 0x2a, 0xc8, 0x4b, 0x6a, 0x54, 0x8a, 0x5c,
- 0x8b, 0x5c, 0xab, 0x5c, 0x8c, 0x5c, 0x4c, 0x54, 0x0c, 0x54, 0xeb, 0x4b,
- 0xc8, 0x3a, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0xa8, 0x5c, 0xac, 0x75, 0x24, 0x2a, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x07, 0x11,
- 0xaa, 0x21, 0xcc, 0x21, 0x0d, 0x22, 0xcc, 0x21, 0x69, 0x19, 0xa5, 0x10,
- 0x63, 0x08, 0x4a, 0x19, 0x84, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x20, 0x00, 0x49, 0x5c, 0x0c, 0x76, 0x4b, 0x65, 0xeb, 0x64, 0x2a, 0x54,
- 0xa9, 0x4b, 0x49, 0x43, 0x49, 0x43, 0x69, 0x4b, 0xeb, 0x4b, 0x6d, 0x54,
- 0x8b, 0x43, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x8d, 0x75, 0x66, 0x32,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x07, 0x11, 0xcb, 0x21, 0xab, 0x19, 0xab, 0x19, 0xcd, 0x21, 0x2f, 0x22,
- 0x72, 0x2a, 0x52, 0x2a, 0x4a, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x41, 0x00, 0x87, 0x4b, 0x69, 0x5c, 0xa8, 0x4b, 0xe6, 0x3a, 0xc8, 0x4b,
- 0x2a, 0x54, 0x8b, 0x5c, 0x6b, 0x54, 0xeb, 0x4b, 0x69, 0x43, 0x87, 0x32,
- 0x67, 0x2a, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0xa8, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x21, 0x00, 0x6a, 0x19, 0xcb, 0x21, 0x8a, 0x19, 0x28, 0x11, 0x6a, 0x19,
- 0xac, 0x21, 0xcd, 0x21, 0x4b, 0x19, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x24, 0x2a, 0x4a, 0x6d, 0xab, 0x75, 0xcc, 0x75, 0x4a, 0x54, 0xe6, 0x3a,
- 0x85, 0x2a, 0x25, 0x2a, 0x46, 0x2a, 0x46, 0x2a, 0xa8, 0x32, 0x0c, 0x54,
- 0xec, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0xca, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xab, 0x19, 0x4f, 0x2a, 0x4f, 0x22, 0x30, 0x22,
- 0x50, 0x2a, 0x72, 0x2a, 0x31, 0x2a, 0x64, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0xa5, 0x32, 0x48, 0x5c, 0x67, 0x43, 0xa5, 0x3a, 0x09, 0x54, 0x2c, 0x6d,
- 0x8d, 0x6d, 0x6d, 0x6d, 0x6e, 0x6d, 0x4e, 0x65, 0xad, 0x5c, 0x4a, 0x43,
- 0xa5, 0x21, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0x8f, 0x54, 0xaa, 0x3a, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xa4, 0x08, 0x2e, 0x22, 0x0e, 0x2a, 0xed, 0x21,
- 0xac, 0x21, 0x29, 0x19, 0x29, 0x11, 0xe7, 0x10, 0x00, 0x00, 0x40, 0x08,
- 0x08, 0x54, 0xab, 0x75, 0xab, 0x6d, 0x8b, 0x6d, 0x6c, 0x6d, 0x4c, 0x6d,
- 0x0c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xcd, 0x5c, 0xcd, 0x5c, 0xcd, 0x5c,
- 0xcb, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xcc, 0x32, 0x20, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe7, 0x10, 0xed, 0x21, 0x30, 0x2a,
- 0x52, 0x2a, 0x52, 0x2a, 0x32, 0x2a, 0x8c, 0x19, 0x00, 0x00, 0xa1, 0x08,
- 0x4a, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xb0, 0x4b, 0x0e, 0x3b, 0x41, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc5, 0x10, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0xce, 0x21, 0x21, 0x00, 0xe1, 0x10,
- 0x0b, 0x76, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xaf, 0x4b, 0x50, 0x43, 0xf0, 0x3a,
- 0x62, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x2f, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x42, 0x08, 0xa3, 0x21,
- 0x2b, 0x7e, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xb0, 0x4b, 0x50, 0x43, 0x30, 0x3b,
- 0x8e, 0x32, 0xa4, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xed, 0x21, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x32, 0x2a, 0xc5, 0x18, 0xa5, 0x3a,
- 0x0b, 0x7e, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xb0, 0x4b, 0x50, 0x43, 0x30, 0x3b,
- 0xd0, 0x3a, 0x70, 0x32, 0xa4, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, 0x19, 0x71, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x32, 0x2a, 0x28, 0x19, 0x66, 0x43,
- 0xeb, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xb0, 0x4b, 0x50, 0x43, 0x30, 0x3b,
- 0xd0, 0x3a, 0x91, 0x32, 0x30, 0x2a, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe6, 0x08, 0x92, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x12, 0x2a, 0x6a, 0x21, 0x27, 0x54,
- 0xca, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xb0, 0x4b, 0x50, 0x43, 0x30, 0x3b,
- 0xd0, 0x3a, 0x70, 0x32, 0x51, 0x32, 0xa5, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc5, 0x08, 0x92, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xac, 0x21, 0x88, 0x5c,
- 0xca, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xb0, 0x4b, 0x50, 0x43, 0x30, 0x3b,
- 0xd0, 0x32, 0xb2, 0x32, 0x29, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x11, 0x92, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xcd, 0x29, 0xe8, 0x5c,
- 0xca, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xb0, 0x4b, 0x50, 0x43, 0x30, 0x3b,
- 0xaf, 0x32, 0x06, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8b, 0x21, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xee, 0x29, 0xe8, 0x5c,
- 0xca, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xaf, 0x4b, 0x91, 0x4b, 0x8d, 0x32,
- 0x83, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x22, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x0f, 0x32, 0xe8, 0x5c,
- 0xca, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0x2e, 0x54, 0x0f, 0x4c, 0xf1, 0x4b, 0xa7, 0x21, 0x21, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x08, 0x4f, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xee, 0x29, 0x88, 0x5c,
- 0xca, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0x8e, 0x54, 0x4e, 0x54, 0xcf, 0x43, 0x45, 0x19, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x19, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xcd, 0x29, 0x27, 0x54,
- 0xca, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0xed, 0x64,
- 0xae, 0x5c, 0x4c, 0x43, 0xe3, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x2e, 0x22, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0xac, 0x29, 0x87, 0x4b,
- 0xeb, 0x75, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0x88, 0x5c, 0xab, 0x75, 0x2c, 0x65, 0x0d, 0x65,
- 0xa8, 0x32, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x69, 0x19, 0x91, 0x32, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x12, 0x2a, 0x8a, 0x21, 0xc5, 0x3a,
- 0x0b, 0x7e, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0xa8, 0x5c, 0xcb, 0x75, 0x4c, 0x6d, 0x06, 0x2a,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xe6, 0x10, 0xb1, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x32, 0x2a, 0x29, 0x19, 0xc3, 0x21,
- 0x2b, 0x7e, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x00, 0xc8, 0x5c, 0x89, 0x5c, 0x02, 0x11, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x06, 0x11, 0xb1, 0x32, 0xb1, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x32, 0x2a, 0xe6, 0x18, 0xe1, 0x10,
- 0x0b, 0x76, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x61, 0x08, 0xe4, 0x29, 0x61, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xca, 0x21,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x11, 0x2a, 0x42, 0x08, 0xa1, 0x08,
- 0x4a, 0x6d, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x6d, 0x2a, 0xf1, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0xcf, 0x21, 0x21, 0x00, 0x60, 0x08,
- 0x68, 0x54, 0xab, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x06, 0x11, 0xae, 0x2a, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0x8d, 0x19, 0x01, 0x00, 0x00, 0x00,
- 0x66, 0x43, 0x8b, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0xea, 0x21, 0xf1, 0x3a, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x31, 0x2a, 0x09, 0x11, 0x00, 0x00, 0x00, 0x00,
- 0x44, 0x2a, 0x8b, 0x75, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x08,
- 0x6c, 0x2a, 0x30, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x11, 0x2a, 0xa6, 0x08, 0x00, 0x00, 0x00, 0x00,
- 0xe1, 0x10, 0x6a, 0x6d, 0x8b, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x11, 0xee, 0x32,
- 0x51, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x10, 0x2a, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x20, 0x08, 0x28, 0x54, 0xab, 0x6d, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9, 0x21, 0x30, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x31, 0x2a, 0x6b, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x24, 0x2a, 0xcb, 0x75, 0x4b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x41, 0x00, 0xac, 0x2a, 0x91, 0x4b, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x51, 0x2a, 0xc6, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x81, 0x10, 0xea, 0x5c, 0x6b, 0x6d, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x25, 0x19, 0x2e, 0x3b, 0xb1, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x71, 0x2a, 0xee, 0x21, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x07, 0x3b, 0x8b, 0x75, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x22,
- 0xaf, 0x4b, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x51, 0x2a, 0x08, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc2, 0x10, 0xeb, 0x64, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x41, 0x08, 0x2d, 0x43, 0xcf, 0x4b,
- 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x0f, 0x2a, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x27, 0x3b, 0x4c, 0x6d, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x45, 0x19, 0x8d, 0x43, 0xcf, 0x4b, 0xaf, 0x4b,
- 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x51, 0x2a,
- 0x49, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe2, 0x10, 0xea, 0x5c, 0x4c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x0b, 0x3b, 0x0f, 0x4c, 0xcf, 0x4b, 0xaf, 0x4b,
- 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x71, 0x2a, 0x2f, 0x2a,
- 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x3a, 0x6c, 0x6d,
- 0x2c, 0x65, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x08, 0x0b, 0x3b, 0x0f, 0x4c, 0xcf, 0x4b, 0xaf, 0x4b,
- 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x91, 0x2a, 0x91, 0x2a, 0x07, 0x11,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x4b,
- 0x6d, 0x6d, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x08, 0x0b, 0x3b, 0x0f, 0x4c, 0xcf, 0x4b, 0xaf, 0x4b,
- 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0xb2, 0x32, 0xab, 0x21, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x08,
- 0x8b, 0x5c, 0x2c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x08, 0x0b, 0x3b, 0x0f, 0x4c, 0xcf, 0x4b, 0xaf, 0x4b,
- 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x91, 0x32, 0x0e, 0x22, 0x21, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x63, 0x19, 0x0c, 0x65, 0x0d, 0x65, 0xed, 0x5c, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x08, 0x0b, 0x3b, 0x0f, 0x4c, 0xcf, 0x4b, 0xaf, 0x4b,
- 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xb0, 0x32, 0xb0, 0x32, 0x70, 0x2a, 0xa4, 0x10, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x25, 0x2a, 0x0d, 0x65, 0xed, 0x64, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x08, 0x0b, 0x3b, 0x0f, 0x4c, 0xcf, 0x4b, 0xaf, 0x4b,
- 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd0, 0x32, 0xb0, 0x32, 0xe6, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xe5, 0x29, 0x0d, 0x65, 0xcd, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x08, 0x0b, 0x3b, 0x0f, 0x4c, 0xcf, 0x4b, 0xaf, 0x4b,
- 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xd0, 0x32,
- 0xd1, 0x32, 0xe6, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x2a, 0xad, 0x5c, 0xad, 0x5c,
- 0xaa, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x08, 0x0b, 0x3b, 0x0f, 0x4c, 0xcf, 0x4b, 0xaf, 0x4b,
- 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0xf0, 0x32, 0xd0, 0x32, 0xaf, 0x32,
- 0x06, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0x21, 0x2c, 0x4c,
- 0xcb, 0x4b, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x08, 0x0b, 0x3b, 0x0f, 0x4c, 0xcf, 0x4b, 0xaf, 0x4b,
- 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x10, 0x3b, 0x11, 0x33, 0x6d, 0x2a, 0xc5, 0x08,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x61, 0x08,
- 0xe6, 0x21, 0x41, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x08, 0x0b, 0x3b, 0x0f, 0x4c, 0xcf, 0x4b, 0xaf, 0x4b,
- 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x30, 0x3b, 0x10, 0x3b, 0x31, 0x3b, 0xca, 0x21, 0x21, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x08, 0x0b, 0x3b, 0x0f, 0x4c, 0xcf, 0x4b, 0xaf, 0x4b,
- 0x8f, 0x43, 0x8f, 0x43, 0x90, 0x43, 0x70, 0x43, 0x50, 0x3b, 0x50, 0x3b,
- 0x10, 0x3b, 0xae, 0x2a, 0xc4, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x08, 0x2b, 0x3b, 0x10, 0x4c, 0xcf, 0x4b, 0xaf, 0x4b,
- 0xaf, 0x43, 0xaf, 0x43, 0xb1, 0x43, 0xb1, 0x4b, 0x0e, 0x3b, 0xc9, 0x21,
- 0x05, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0xc6, 0x21, 0xca, 0x32, 0xeb, 0x32, 0xeb, 0x32,
- 0x8b, 0x32, 0x08, 0x2a, 0x45, 0x11, 0xa3, 0x08, 0x41, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-#endif
#include "bm1000_splash.h"
+#include <baikal_bootflash.h>
+#include <baikal_mshc.h>
+#include <baikal_def.h>
+
static uint64_t trusted_mailbox[1 + PLATFORM_CORE_COUNT]
- __attribute__ ((used, section(".trusted_mailbox")));
+ __section(".trusted_mailbox") __used;
CASSERT(sizeof(trusted_mailbox) == BAIKAL_TRUSTED_MAILBOX_SIZE,
assert_trusted_mailbox_size);
/* Allocate space in static memory for DDR SPD content */
const struct spd_container spd_content = {0};
+#if !DEBUG
+static char msg_buf[300];
+#endif
+
/*
* Cannot use default weak implementation in bl1_main.c because BL1 RW and BL2
* data size exceeds Mailbox SRAM.
static void ccn_hnf_sam_setup(void)
{
- unsigned i;
+ unsigned int i;
uintptr_t pccn = PLAT_ARM_CCN_BASE + CCN_HNF_OFFSET + 8;
uint64_t snf0 = 0, snf1 = 0;
- INFO("%s...\n", __func__);
-
if (cmu_pll_is_enabled(MMDDR0_CMU0_BASE)) {
snf0 = 4;
}
#endif
write_cntfrq_el0(plat_get_syscnt_freq2());
generic_delay_timer_init();
-#ifndef BAIKAL_QEMU
+
dram_init();
-#endif
ccn_hnf_sam_setup();
-
err = memtest_rand64(BL1_XLAT_BASE, BL1_XLAT_SIZE, sizeof(uint64_t), read_cntpct_el0());
#if DEBUG
- err |= memtest_rand8( BL1_XLAT_BASE, BL1_XLAT_SIZE, sizeof(uint8_t), read_cntpct_el0());
+ err |= memtest_rand8(BL1_XLAT_BASE, BL1_XLAT_SIZE, sizeof(uint8_t), read_cntpct_el0());
#endif
if (err) {
ERROR("%s: DRAM error\n", __func__);
void bl1_platform_setup(void)
{
-#if !DEBUG
- extern uint8_t bl1_logo[];
-#endif
uint8_t *spd_ptr = (uint8_t *)PLAT_DDR_SPD_BASE;
- memcpy(spd_ptr, &spd_content, sizeof(struct spd_container));
+ memcpy(spd_ptr, &spd_content, sizeof(struct spd_container));
plat_baikal_io_setup();
- bootflash_init();
- mmxgbe_init();
+ generic_delay_timer_init();
+ mmavlsp_init();
#if !DEBUG
- hdmi_early_splash(bl1_logo);
-#else
- hdmi_early_splash(NULL);
+ snprintf(msg_buf, sizeof(msg_buf), "BE-M1000\nBL1: %s\nBL1: %s\n", version_string, build_message);
+ lvds_early_splash(msg_buf);
+ mmxgbe_init();
+ hdmi_early_splash(msg_buf);
#endif
}
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
+#include <lib/mmio.h>
#include <lib/utils.h>
#include <libfdt.h>
#ifdef SPD_opteed
u_register_t arg3)
{
meminfo_t *mem_layout = (meminfo_t *)arg1;
+
baikal_console_boot_init();
/* Setup the BL2 memory layout */
ret = fdt_open_into(fdt, fdt, BAIKAL_DTB_MAX_SIZE);
if (ret >= 0) {
- unsigned dimm_idx;
+ unsigned int dimm_idx;
/*
* DBM has 4 DIMM slots with the following SPD addresses:
* 0x50, 0x51, 0x52, 0x53. But only 0x50 and 0x52 are used by SCP FW.
for (dimm_idx = 0; dimm_idx < ARRAY_SIZE(dimm_spd_addrs); ++dimm_idx) {
if (spd_ptr->content[dimm_idx].mem_type == SPD_MEMTYPE_DDR4) {
unsigned int half_bus_shift = 0;
+
if (dimm_idx) {
- if ((*(volatile uint32_t*)(MMDDR1_CTRL_BASE)) & 1 << 12) {
+ if (mmio_read_32(MMDDR1_CTRL_BASE) & BIT(12)) {
half_bus_shift = 1;
}
} else {
- if ((*(volatile uint32_t*)(MMDDR0_CTRL_BASE)) & 1 << 12) {
+ if (mmio_read_32(MMDDR0_CTRL_BASE) & BIT(12)) {
half_bus_shift = 1;
}
}
- const unsigned long long dimm_capacity = \
- spd_get_baseconf_dimm_capacity(&spd_ptr->content[dimm_idx]) \
+
+ const unsigned long long dimm_capacity =
+ spd_get_baseconf_dimm_capacity(&spd_ptr->content[dimm_idx])
>> half_bus_shift;
+
if (dimm_capacity > 0) {
#ifdef BAIKAL_DUAL_CHANNEL_MODE
if (spd_ptr->dual_channel[dimm_idx] == 'y') {
if (total_capacity > 0) {
uint64_t region_descs[3][2];
- unsigned region_num;
+ unsigned int region_num;
region_descs[0][0] = REGION_DRAM0_BASE;
region_descs[1][0] = REGION_DRAM1_BASE;
+++ /dev/null
-const unsigned char bl31_sdk_version_logo[] = {
- 0x42, 0x4d, 0xaa, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a, 0x00,
- 0x00, 0x00, 0x7c, 0x00, 0x00, 0x00, 0x5a, 0x00, 0x00, 0x00, 0x14, 0x00,
- 0x00, 0x00, 0x01, 0x00, 0x20, 0x00, 0x03, 0x00, 0x00, 0x00, 0x20, 0x1c,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0xff,
- 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x42, 0x47,
- 0x52, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0xa0, 0xa0, 0xa0, 0xff, 0x82, 0x82, 0x82, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x1b, 0x1b, 0x1b, 0xff, 0x91, 0x91, 0x91, 0xff, 0x8b, 0x8b,
- 0x8b, 0xff, 0x96, 0x96, 0x96, 0xff, 0x4b, 0x4b, 0x4b, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x02, 0x02, 0x02, 0xff, 0xd3, 0xd3, 0xd3, 0xff, 0xa7, 0xa7,
- 0xa7, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x21, 0x21,
- 0x21, 0xff, 0x9b, 0x9b, 0x9b, 0xff, 0x90, 0x90, 0x90, 0xff, 0x8a, 0x8a,
- 0x8a, 0xff, 0x04, 0x04, 0x04, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x26, 0x26,
- 0x26, 0xff, 0x6e, 0x6e, 0x6e, 0xff, 0x82, 0x82, 0x82, 0xff, 0x09, 0x09,
- 0x09, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x5b, 0x5b, 0x5b, 0xff, 0x10, 0x10, 0x10, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x84, 0x84, 0x84, 0xff, 0x1b, 0x1b,
- 0x1b, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0xa8, 0xa8, 0xa8, 0xff, 0x82, 0x82,
- 0x82, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x8a, 0x8a,
- 0x8a, 0xff, 0x05, 0x05, 0x05, 0xff, 0x00, 0x00, 0x00, 0xff, 0x2c, 0x2c,
- 0x2c, 0xff, 0x68, 0x68, 0x68, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x25, 0x25, 0x25, 0xff, 0x93, 0x93, 0x93, 0xff, 0x94, 0x94,
- 0x94, 0xff, 0x94, 0x94, 0x94, 0xff, 0x94, 0x94, 0x94, 0xff, 0x94, 0x94,
- 0x94, 0xff, 0x90, 0x90, 0x90, 0xff, 0x0a, 0x0a, 0x0a, 0xff, 0x25, 0x25,
- 0x25, 0xff, 0x93, 0x93, 0x93, 0xff, 0x94, 0x94, 0x94, 0xff, 0x94, 0x94,
- 0x94, 0xff, 0x94, 0x94, 0x94, 0xff, 0x94, 0x94, 0x94, 0xff, 0x90, 0x90,
- 0x90, 0xff, 0x0a, 0x0a, 0x0a, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x83, 0x83,
- 0x83, 0xff, 0x11, 0x11, 0x11, 0xff, 0x2e, 0x2e, 0x2e, 0xff, 0x5d, 0x5d,
- 0x5d, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x25, 0x25, 0x25, 0xff, 0x62, 0x62,
- 0x62, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x14, 0x14, 0x14, 0xff, 0x7c, 0x7c,
- 0x7c, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x87, 0x87, 0x87, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x25, 0x25, 0x25, 0xff, 0x93, 0x93,
- 0x93, 0xff, 0x94, 0x94, 0x94, 0xff, 0x94, 0x94, 0x94, 0xff, 0x94, 0x94,
- 0x94, 0xff, 0x94, 0x94, 0x94, 0xff, 0x90, 0x90, 0x90, 0xff, 0x0a, 0x0a,
- 0x0a, 0xff, 0x25, 0x25, 0x25, 0xff, 0x93, 0x93, 0x93, 0xff, 0x94, 0x94,
- 0x94, 0xff, 0x94, 0x94, 0x94, 0xff, 0x94, 0x94, 0x94, 0xff, 0x94, 0x94,
- 0x94, 0xff, 0x90, 0x90, 0x90, 0xff, 0x0a, 0x0a, 0x0a, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x06, 0x06, 0x06, 0xff, 0x8d, 0x8d,
- 0x8d, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x8d, 0x8d,
- 0x8d, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x18, 0x18, 0x18, 0xff, 0x6e, 0x6e,
- 0x6e, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x33, 0x33, 0x33, 0xff, 0xb5, 0xb5,
- 0xb5, 0xff, 0x28, 0x28, 0x28, 0xff, 0x00, 0x00, 0x00, 0xff, 0x4f, 0x4f,
- 0x4f, 0xff, 0x53, 0x53, 0x53, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x24, 0x24, 0x24, 0xff, 0x8f, 0x8f, 0x8f, 0xff, 0x90, 0x90,
- 0x90, 0xff, 0x90, 0x90, 0x90, 0xff, 0x90, 0x90, 0x90, 0xff, 0x90, 0x90,
- 0x90, 0xff, 0x8c, 0x8c, 0x8c, 0xff, 0x0a, 0x0a, 0x0a, 0xff, 0x24, 0x24,
- 0x24, 0xff, 0x8f, 0x8f, 0x8f, 0xff, 0x90, 0x90, 0x90, 0xff, 0x90, 0x90,
- 0x90, 0xff, 0x90, 0x90, 0x90, 0xff, 0x90, 0x90, 0x90, 0xff, 0x8c, 0x8c,
- 0x8c, 0xff, 0x0a, 0x0a, 0x0a, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x59, 0x59, 0x59, 0xff, 0x3b, 0x3b,
- 0x3b, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x65, 0x65,
- 0x65, 0xff, 0x29, 0x29, 0x29, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x0d, 0x0d, 0x0d, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x69, 0x69, 0x69, 0xff, 0x30, 0x30,
- 0x30, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x2b, 0x2b, 0x2b, 0xff, 0x60, 0x60,
- 0x60, 0xff, 0x7c, 0x7c, 0x7c, 0xff, 0x92, 0x92, 0x92, 0xff, 0x68, 0x68,
- 0x68, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x24, 0x24, 0x24, 0xff, 0x8f, 0x8f,
- 0x8f, 0xff, 0x90, 0x90, 0x90, 0xff, 0x90, 0x90, 0x90, 0xff, 0x90, 0x90,
- 0x90, 0xff, 0x90, 0x90, 0x90, 0xff, 0x8c, 0x8c, 0x8c, 0xff, 0x0a, 0x0a,
- 0x0a, 0xff, 0x24, 0x24, 0x24, 0xff, 0x8f, 0x8f, 0x8f, 0xff, 0x90, 0x90,
- 0x90, 0xff, 0x90, 0x90, 0x90, 0xff, 0x90, 0x90, 0x90, 0xff, 0x90, 0x90,
- 0x90, 0xff, 0x8c, 0x8c, 0x8c, 0xff, 0x0a, 0x0a, 0x0a, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x4b, 0x4b, 0x4b, 0xff, 0xd0, 0xd0, 0xd0, 0xff, 0x8a, 0x8a,
- 0x8a, 0xff, 0x02, 0x02, 0x02, 0xff, 0x1a, 0x1a, 0x1a, 0xff, 0x9c, 0x9c,
- 0x9c, 0xff, 0xc1, 0xc1, 0xc1, 0xff, 0x2e, 0x2e, 0x2e, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x0f, 0x0f, 0x0f, 0xff, 0xca, 0xca, 0xca, 0xff, 0x94, 0x94,
- 0x94, 0xff, 0x97, 0x97, 0x97, 0xff, 0x6f, 0x6f, 0x6f, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x03, 0x03, 0x03, 0xff, 0x95, 0x95,
- 0x95, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x10, 0x10, 0x10, 0xff, 0x78, 0x78, 0x78, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x5d, 0x5d,
- 0x5d, 0xff, 0x72, 0x72, 0x72, 0xff, 0x01, 0x01, 0x01, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x10, 0x10, 0x10, 0xff, 0xc6, 0xc6, 0xc6, 0xff, 0x94, 0x94,
- 0x94, 0xff, 0x94, 0x94, 0x94, 0xff, 0x82, 0x82, 0x82, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x56, 0x56, 0x56, 0xff, 0xa8, 0xa8, 0xa8, 0xff, 0x97, 0x97,
- 0x97, 0xff, 0x48, 0x48, 0x48, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00,
- 0x00, 0xff, 0x00, 0x00, 0x00, 0xff
-};
/*
- * Copyright (c) 2018-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2018-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/bl_common.h>
-#include <common/debug.h>
#include <drivers/generic_delay_timer.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include "bm1000_mmca57.h"
#include "bm1000_splash.h"
-#include "bm1000_vdu.h"
+
+#define XSTR(x) STR(x)
+#define STR(x) #x
/*
* The next 3 constants identify the extents of the code, RO data region and the
#define BL31_END (unsigned long)(&__BL31_END__)
extern uint8_t bl31_logo[];
-extern uint8_t bl31_sdk_version_logo[];
+
+static void bl31_splash(void)
+{
+ modeline_t old_lvds_mode, new_lvds_mode;
+ int do_lvds_init;
+
+#ifdef SDK_VERSION
+ snprintf(sdk_version, SDK_VERSION_SIZE, "== v%s ==", XSTR(SDK_VERSION));
+#endif
+ display_logo_and_version(MMXGBE_VDU_BASE, FB2_BASE, &hdmi_video_mode, bl31_logo);
+#if DEBUG
+ vdu_init(MMXGBE_VDU_BASE, (uintptr_t)FB2_BASE, &hdmi_video_mode);
+#endif
+ memcpy(&old_lvds_mode, &lvds_video_mode, sizeof(lvds_video_mode));
+ memcpy(&new_lvds_mode, &lvds_video_mode, sizeof(lvds_video_mode));
+ if (!fdt_get_panel(&new_lvds_mode)) {
+ display_logo_and_version(MMAVLSP_VDU_BASE, FB0_BASE, &new_lvds_mode, bl31_logo);
+#if !DEBUG
+ do_lvds_init = memcmp(&old_lvds_mode, &new_lvds_mode, sizeof(old_lvds_mode));
+#else
+ do_lvds_init = 1;
+#endif
+ if (do_lvds_init) {
+ vdu_init(MMAVLSP_VDU_BASE, (uintptr_t)FB0_BASE,
+ &new_lvds_mode);
+ }
+ }
+}
void bl31_plat_arch_setup(void)
{
void bl31_platform_setup(void)
{
- int fb_cpp;
-
generic_delay_timer_init();
-
+#if DEBUG
INFO("Init AVLSP...\n");
mmavlsp_init();
-
-#ifndef BAIKAL_QEMU
+#endif
INFO("Init CA57 PVTs...\n");
cmu_clkch_enable_by_base(MMCA57_0_PVT_CLKCHCTL, PVT_CLKCH_DIV);
cmu_clkch_enable_by_base(MMCA57_1_PVT_CLKCHCTL, PVT_CLKCH_DIV);
cmu_clkch_enable_by_base(MMCA57_2_PVT_CLKCHCTL, PVT_CLKCH_DIV);
cmu_clkch_enable_by_base(MMCA57_3_PVT_CLKCHCTL, PVT_CLKCH_DIV);
-#endif
INFO("Init XGbE...\n");
- fb_cpp = bmp_to_fb((uintptr_t)FB2_BASE, &hdmi_video_mode, bl31_logo, 0, 0, 1);
- if (fb_cpp > 2) { /* we do not support 16-bit and lower color resolutions here */
- int h1, h2, w1, w2;
-
- /* Put SDK version just behind the logo, aligned to its right edge */
- bmp_get_dimensions(bl31_logo, &w1, &h1);
- bmp_get_dimensions(bl31_sdk_version_logo, &w2, &h2);
- bmp_to_fb((uintptr_t)FB2_BASE,
- &hdmi_video_mode,
- bl31_sdk_version_logo,
- (w1 - w2) / 2,
- (h1 + h2) / 2,
- 0);
-#ifndef BAIKAL_QEMU
- wait_for_vblank(MMXGBE_VDU_BASE);
+#if DEBUG
+ mmxgbe_init();
+ hdmi_tx_init();
#endif
- vdu_set_fb(MMXGBE_VDU_BASE,
- (uintptr_t)FB2_BASE,
- &hdmi_video_mode,
- fb_cpp);
- }
-
mmxgbe_ns_access();
INFO("Init USB...\n");
INFO("Init VDec...\n");
mmvdec_init();
- INFO("Init Coresight...\n");
+ INFO("Init CoreSight...\n");
mmcoresight_init();
baikal_gic_driver_init();
baikal_gic_init();
+
+ bl31_splash();
}
void bl31_plat_enable_mmu(uint32_t flags)
{
enable_mmu_el3(flags);
}
-
-void bl31_plat_runtime_setup(void)
-{
- int fb_cpp;
- unsigned idx;
- struct cmu_desc *lvds_vdu_cmu = NULL;
-
- /* Set frequencies from device tree */
- for (idx = 0; ; ++idx) {
- struct cmu_desc *const cmu = cmu_desc_get_by_idx(idx);
- if (cmu == NULL || !cmu->base) {
- break;
- }
-
- INFO("%s: base=0x%08lx name=%s rate=%lu\n", __func__, cmu->base, cmu->name, cmu->fpllreq);
-
- if (cmu->base == MMAVLSP_CMU1_BASE) {
- lvds_vdu_cmu = cmu;
- continue;
- }
-
- cmu_pll_set_rate(cmu->base, cmu->frefclk, cmu->fpllreq);
- }
-
- if (!fdt_get_panel(&lvds_video_mode)) {
- fb_cpp = bmp_to_fb((uintptr_t)FB0_BASE, &lvds_video_mode,
- bl31_logo, 0, 0, 1);
- if (fb_cpp > 2) { /* we do not support 16-bit and lower color resolutions here */
- int h1, h2, w1, w2;
-
- vdu_set_fb(MMAVLSP_VDU_BASE,
- (uintptr_t)FB0_BASE,
- &lvds_video_mode,
- fb_cpp);
-
- /*
- * Put SDK version just behind the logo,
- * aligned to its right edge
- */
- bmp_get_dimensions(bl31_logo, &w1, &h1);
- bmp_get_dimensions(bl31_sdk_version_logo, &w2, &h2);
- bmp_to_fb((uintptr_t)FB0_BASE,
- &lvds_video_mode,
- bl31_sdk_version_logo,
- (w1 - w2) / 2,
- (h1 + h2) / 2,
- 0);
-
- if (lvds_vdu_cmu != NULL) {
- cmu_pll_set_rate(lvds_vdu_cmu->base,
- lvds_vdu_cmu->frefclk,
- lvds_video_mode.clock * 7);
- }
-
- vdu_init(MMAVLSP_VDU_BASE, (uintptr_t)FB0_BASE,
- &lvds_video_mode);
- }
- }
-}
--- /dev/null
+/*
+ * Copyright (c) 2023, Baikal Electronics, JSC. All rights reserved.
+ *
+ * This is bitmap data for 8x19 font from UEFI.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+const uint8_t font[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x18, 0x3C, 0x3C, 0x3C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x6C, 0x6C, 0x6C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x6C, 0x6C, 0x6C, 0xFE, 0x6C, 0x6C, 0x6C, 0xFE, 0x6C, 0x6C, 0x6C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x18, 0x18, 0x7C, 0xC6, 0xC6, 0x60, 0x38, 0x0C, 0x06, 0xC6, 0xC6, 0x7C, 0x18, 0x18, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xC6, 0xC6, 0x0C, 0x0C, 0x18, 0x18, 0x30, 0x30, 0x60, 0x60, 0xC6, 0xC6, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x78, 0xCC, 0xCC, 0xCC, 0x78, 0x76, 0xDC, 0xCC, 0xCC, 0xCC, 0xCC, 0x76, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x18, 0x18, 0x18, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x06, 0x0C, 0x0C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x0C, 0x0C, 0x06, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xC0, 0x60, 0x60, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x60, 0x60, 0xC0, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6C, 0x38, 0xFE, 0x38, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x7E, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x30, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x06, 0x06, 0x0C, 0x0C, 0x18, 0x18, 0x30, 0x30, 0x60, 0x60, 0xC0, 0xC0, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x38, 0x6C, 0xC6, 0xC6, 0xC6, 0xD6, 0xD6, 0xC6, 0xC6, 0xC6, 0x6C, 0x38, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x18, 0x38, 0x78, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x7E, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x7C, 0xC6, 0x06, 0x06, 0x06, 0x0C, 0x18, 0x30, 0x60, 0xC0, 0xC2, 0xFE, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x7C, 0xC6, 0x06, 0x06, 0x06, 0x3C, 0x06, 0x06, 0x06, 0x06, 0xC6, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x1C, 0x1C, 0x3C, 0x3C, 0x6C, 0x6C, 0xCC, 0xFE, 0x0C, 0x0C, 0x0C, 0x1E, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFE, 0xC0, 0xC0, 0xC0, 0xC0, 0xFC, 0x06, 0x06, 0x06, 0x06, 0xC6, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x3C, 0x60, 0xC0, 0xC0, 0xC0, 0xFC, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFE, 0xC6, 0x06, 0x06, 0x06, 0x0C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x7C, 0xC6, 0xC6, 0xC6, 0xC6, 0x7C, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x7C, 0xC6, 0xC6, 0xC6, 0xC6, 0x7E, 0x06, 0x06, 0x06, 0x06, 0x0C, 0x78, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x18, 0x18, 0x30, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x06, 0x0C, 0x18, 0x30, 0x60, 0xC0, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0xC0, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x0C, 0x18, 0x30, 0x60, 0xC0, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x7C, 0xC6, 0xC6, 0x0C, 0x0C, 0x18, 0x18, 0x18, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x7C, 0xC6, 0xC6, 0xC6, 0xDE, 0xDE, 0xDE, 0xDC, 0xC0, 0xC0, 0x7E, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x10, 0x38, 0x6C, 0xC6, 0xC6, 0xC6, 0xFE, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFC, 0x66, 0x66, 0x66, 0x66, 0x7C, 0x66, 0x66, 0x66, 0x66, 0x66, 0xFC, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x3C, 0x66, 0xC2, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC2, 0x66, 0x3C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xF8, 0x6C, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x6C, 0xF8, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFE, 0x66, 0x62, 0x60, 0x68, 0x78, 0x68, 0x60, 0x60, 0x62, 0x66, 0xFE, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFE, 0x66, 0x62, 0x60, 0x64, 0x7C, 0x64, 0x60, 0x60, 0x60, 0x60, 0xF0, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x3C, 0x66, 0xC2, 0xC0, 0xC0, 0xC0, 0xDE, 0xC6, 0xC6, 0xC6, 0x66, 0x3C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xFE, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFC, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0xFC, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x1E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0xCC, 0xCC, 0x78, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xE6, 0x66, 0x6C, 0x6C, 0x78, 0x70, 0x78, 0x6C, 0x6C, 0x66, 0x66, 0xE6, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xF0, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x62, 0x66, 0xFE, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xC6, 0xEE, 0xEE, 0xFE, 0xFE, 0xD6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xC6, 0xE6, 0xF6, 0xF6, 0xF6, 0xDE, 0xCE, 0xCE, 0xC6, 0xC6, 0xC6, 0xC6, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x7C, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFC, 0x66, 0x66, 0x66, 0x66, 0x66, 0x7C, 0x60, 0x60, 0x60, 0x60, 0xF0, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x7C, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xD6, 0xD6, 0x7C, 0x1C, 0x0E, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFC, 0x66, 0x66, 0x66, 0x66, 0x7C, 0x78, 0x6C, 0x6C, 0x66, 0x66, 0xE6, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x7C, 0xC6, 0xC6, 0xC6, 0x60, 0x38, 0x0C, 0x06, 0x06, 0xC6, 0xC6, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFC, 0xFC, 0xB4, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x78, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x6C, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xD6, 0xD6, 0xD6, 0xFE, 0x6C, 0x6C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xC6, 0xC6, 0xC6, 0x6C, 0x6C, 0x38, 0x6C, 0x6C, 0xC6, 0xC6, 0xC6, 0xC6, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0x78, 0x30, 0x30, 0x30, 0x30, 0x30, 0x78, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFE, 0xC6, 0x86, 0x0C, 0x0C, 0x18, 0x30, 0x60, 0xC0, 0xC2, 0xC6, 0xFE, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x1E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1E, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xC0, 0xC0, 0x60, 0x60, 0x30, 0x30, 0x18, 0x18, 0x0C, 0x0C, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xF0, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0xF0, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x10, 0x38, 0x6C, 0xC6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x30, 0x30, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x0C, 0x0C, 0x7C, 0xCC, 0xCC, 0xCC, 0x76, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xE0, 0x60, 0x60, 0x60, 0x7C, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0xC6, 0xC0, 0xC0, 0xC0, 0xC0, 0xC6, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x1C, 0x0C, 0x0C, 0x0C, 0x3C, 0x6C, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0x7E, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0xC6, 0xC6, 0xFE, 0xC0, 0xC0, 0xC6, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x1E, 0x33, 0x30, 0x30, 0x30, 0x78, 0x30, 0x30, 0x30, 0x30, 0x30, 0x78, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x76, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0x7C, 0x0C, 0xCC, 0x78, 0x00,
+ 0x00, 0x00, 0x00, 0xE0, 0x60, 0x60, 0x60, 0x7C, 0x76, 0x66, 0x66, 0x66, 0x66, 0x66, 0xE6, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x38, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x0C, 0x00, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x6C, 0x38, 0x00,
+ 0x00, 0x00, 0x00, 0xE0, 0x60, 0x60, 0x66, 0x6C, 0x78, 0x70, 0x78, 0x6C, 0x6C, 0x66, 0xE6, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x38, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEC, 0xEE, 0xFE, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x7C, 0x60, 0x60, 0xF0, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x76, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0x7C, 0x0C, 0x0C, 0x1E, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, 0x66, 0x60, 0x60, 0x60, 0x60, 0x60, 0xF0, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0xC6, 0xC0, 0x7C, 0x06, 0x06, 0xC6, 0x7C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x10, 0x30, 0x30, 0x30, 0xFC, 0x30, 0x30, 0x30, 0x30, 0x30, 0x36, 0x1C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0x76, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0x78, 0x30, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6, 0xC6, 0xC6, 0xD6, 0xD6, 0xFE, 0xEE, 0x6C, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6, 0x6C, 0x38, 0x38, 0x6C, 0x6C, 0xC6, 0xC6, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x7E, 0x06, 0x0C, 0xF8, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x86, 0x0C, 0x18, 0x30, 0x60, 0xC0, 0xFE, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x0E, 0x18, 0x18, 0x18, 0x18, 0x30, 0x18, 0x18, 0x18, 0x18, 0x18, 0x0E, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xE0, 0x30, 0x30, 0x30, 0x30, 0x18, 0x30, 0x30, 0x30, 0x30, 0x30, 0xE0, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x76, 0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
--- /dev/null
+/*
+ * Copyright (c) 2023, Baikal Electronics, JSC. All rights reserved.
+ *
+ * Font header file
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BM1000_FONT_H
+#define BM1000_FONT_H
+
+#include <stdint.h>
+
+#define FONT_WIDTH 8 /* witdh > 8 is not supported */
+#define FONT_HEIGHT 19
+#define FONT_FIRST_CHAR 0x20
+#define FONT_LAST_CHAR 0x7f
+
+extern const uint8_t font[];
+
+#endif /* BM1000_FONT_H */
*
* SPDX-License-Identifier: BSD-3-Clause
*
- * Parts of this file were based on sources as follows:
- *
- * Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
- * SPDX-License-Identifier: BSD-2-Clause-Patent
*/
#ifndef BM1000_HDMI_H
/* Clock dividers for MMAVLSP CMU0 clock channels, PLL frequency is assumed 1200 MHz */
#define MMAVLSP_CLK_7361963HZ 163
#define MMAVLSP_CLK_8MHZ 150
+#define MMAVLSP_CLK_10MHZ 120
#define MMAVLSP_CLK_25MHZ 48
+#define MMAVLSP_CLK_40MHZ 30
#define MMAVLSP_CLK_48MHZ 25
#define MMAVLSP_CLK_50MHZ 24
#define MMAVLSP_CLK_100MHZ 12
void mmavlsp_init(void)
{
const cmu_pll_ctl_vals_t mmavlsp_cmu0_pll_ctls = {
- 0, 0, 0x6000000000, 0, 0x2c, 0, 0x2c
- };
- const cmu_pll_ctl_vals_t mmavlsp_cmu1_pll_ctls = {
- 0x1, 0, 0x9a00000000, 0, 0x2c, 0, 0x2c
+ 0, 0, 0x6000000000, 0, -20, 0, -20
};
+#ifdef BAIKAL_LVDS_CLKEN_GPIO_PIN
+ gpio_out_rst(MMAVLSP_GPIO32_BASE, BAIKAL_LVDS_CLKEN_GPIO_PIN);
+ gpio_dir_set(MMAVLSP_GPIO32_BASE, BAIKAL_LVDS_CLKEN_GPIO_PIN);
+#endif
+
cmu_pll_on(MMAVLSP_CMU0_BASE, &mmavlsp_cmu0_pll_ctls);
cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_GPIO32, MMAVLSP_CLK_8MHZ);
cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_TIMER2, MMAVLSP_CLK_50MHZ);
cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_TIMER3, MMAVLSP_CLK_50MHZ);
cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_TIMER4, MMAVLSP_CLK_50MHZ);
- cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_DMAC, MMAVLSP_CLK_200MHZ);
+ cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_DMACLSP, MMAVLSP_CLK_200MHZ);
cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_SMBUS1, MMAVLSP_CLK_50MHZ);
cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_SMBUS2, MMAVLSP_CLK_50MHZ);
cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_HDA_SYS, MMAVLSP_CLK_100MHZ);
cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_HWA_AXI_MMU, MMAVLSP_CLK_400MHZ);
cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_VDU_AXI, MMAVLSP_CLK_300MHZ);
cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_SMMU, MMAVLSP_CLK_300MHZ);
-
- cmu_pll_on(MMAVLSP_CMU1_BASE, &mmavlsp_cmu1_pll_ctls);
-
-#ifdef BAIKAL_LVDS_CLKEN_GPIO_PIN
- gpio_out_rst(MMAVLSP_GPIO32_BASE, BAIKAL_LVDS_CLKEN_GPIO_PIN);
- gpio_dir_set(MMAVLSP_GPIO32_BASE, BAIKAL_LVDS_CLKEN_GPIO_PIN);
-#endif
+ cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_MSHC_AXI, MMAVLSP_CLK_200MHZ);
+ cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_MSHC_AHB, MMAVLSP_CLK_200MHZ);
+ cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_MSHC_TX_X2, MMAVLSP_CLK_400MHZ);
+ cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_MSHC_BCLK, MMAVLSP_CLK_40MHZ);
+ cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_MSHC_TMCLK, MMAVLSP_CLK_10MHZ);
+ cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_MSHC_CQETMCLK, MMAVLSP_CLK_10MHZ);
/* Deassert reset signals */
mmio_clrbits_32(MMAVLSP_GPR_MMRST1,
MMAVLSP_GPR_MMRST1_NIC_CFG_M_RST |
MMAVLSP_GPR_MMRST1_NIC_S_RST |
MMAVLSP_GPR_MMRST1_NIC_M_RST |
- MMAVLSP_GPR_MMRST1_DMAC_RST |
+ MMAVLSP_GPR_MMRST1_DMACLSP_RST |
MMAVLSP_GPR_MMRST1_SMMU_RST |
MMAVLSP_GPR_MMRST1_GPIO_RST |
MMAVLSP_GPR_MMRST1_UART1_RST |
};
CASSERT(ARRAY_SIZE(mmca57_bases) == PLATFORM_CLUSTER_COUNT, assert_mmca57_bases_size);
-unsigned mmca57_get_sclk_div(const uintptr_t base)
+unsigned int mmca57_get_sclk_div(const uintptr_t base)
{
uint32_t reg;
void mmca57_enable_core(const u_register_t mpidr)
{
- const unsigned cluster = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
- const unsigned core = mpidr & 0x3;
+ const unsigned int cluster = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+ const unsigned int core = mpidr & 0x3;
uint32_t reg;
assert(cluster < PLATFORM_CLUSTER_COUNT);
if (!cmu_pll_is_enabled(base)) {
int ret;
+ cmu_pll_set_gains(base, 0, -20, 0, -20);
ret = cmu_pll_enable(base);
if (ret) {
return;
mmio_write_32(base + MMCA57_CFG_RST, reg);
}
-void mmca57_reconf_sclken(const uintptr_t base, const unsigned div)
+void mmca57_reconf_sclken(const uintptr_t base, const unsigned int div)
{
uint32_t reg;
#include <stdint.h>
-unsigned mmca57_get_sclk_div(const uintptr_t base);
-void mmca57_enable_core(const u_register_t mpidr);
-void mmca57_reconf_sclken(const uintptr_t base, const unsigned div);
+unsigned int mmca57_get_sclk_div(const uintptr_t base);
+void mmca57_enable_core(const u_register_t mpidr);
+void mmca57_reconf_sclken(const uintptr_t base, const unsigned int div);
#endif /* BM1000_MMCA57_H */
void mmmali_init(void)
{
const cmu_pll_ctl_vals_t mmmali_cmu0_pll_ctls = {
- 0, 0, 0x6800000000, 0, 0x2c, 0, 0x2c
+ 0, 0, 0x6800000000, 0, -20, 0, -20
};
cmu_pll_on(MMMALI_CMU0_BASE, &mmmali_cmu0_pll_ctls);
{
uint32_t reg;
const cmu_pll_ctl_vals_t mmpcie_cmu0_pll_ctls = {
- 0, 0, 0x7800000000, 0, 0x2c, 0, 0x2c
+ 0, 0, 0x7800000000, 0, -20, 0, -20
};
cmu_pll_on(MMPCIE_CMU0_BASE, &mmpcie_cmu0_pll_ctls);
#include <bm1000_def.h>
#include <bm1000_private.h>
+#define MMUSB_CLK_50MHZ 16
+#define MMUSB_CLK_100MHZ 8
+#define MMUSB_CLK_133MHZ 6
+#define MMUSB_CLK_160MHZ 5
+#define MMUSB_CLK_200MHZ 4
+#define MMUSB_CLK_400MHZ 2
+
void mmusb_init(void)
{
uint32_t reg;
const cmu_pll_ctl_vals_t mmusb_cmu0_pll_ctls = {
- 1, 0, 0x8000000000, 0, 0x2c, 0, 0x2c /* PLL 800 MHz */
+ 1, 0, 0x8000000000, 0, -20, 0, -20 /* 800 MHz */
};
cmu_pll_on(MMUSB_CMU0_BASE, &mmusb_cmu0_pll_ctls);
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_SATA_REF, 8); /* 100 MHz axi clk controller #1 (50 - 100 MHz) */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_SATA0_AXI, 8); /* 100 MHz differential reference clock */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_SATA1_AXI, 8); /* 100 MHz axi clk controller #0 (50 - 100 MHz) */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB2_PHY0_REF, 16); /* 50 MHz max reference PHY #0 clock */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB2_PHY1_REF, 16); /* 50 MHz max reference PHY #1 clock */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB2_AXI, 16); /* 50 MHz axi clock */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB2_SOFITP, 8); /* 100 MHz reference clock for SOF and ITP counter (16.129 - 125 MHz) */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_PHY0_REF, 8); /* 100 MHz differential reference clock PHY #0 */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_PHY1_REF, 8); /* 100 MHz differential reference clock PHY #1 */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_PHY2_REF, 16); /* 50 MHz max reference PHY #2 clock */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_PHY3_REF, 16); /* 50 MHz max reference PHY #3 clock */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_AXI, 6); /* 133 MHz axi clock */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_SOFITP, 8); /* 100 MHz reference clock for SOF and ITP counter (16.129 - 125 MHz) */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_SUSPEND, 8); /* 100 MHz suspend clock for low power state (P3) (32 kHz - 125 MHz) */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_SMMU, 2); /* 400 MHz axi clk (200 - 400 MHz) */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_DMAC, 4); /* 200 MHz - temp value (250 MHz axi clk (100 - 250 MHz)) */
- cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_GIC, 5); /* 160 MHz */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_SATA_REF, MMUSB_CLK_100MHZ); /* 100 MHz axi clk controller #1 (50 - 100 MHz) */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_SATA0_AXI, MMUSB_CLK_100MHZ); /* 100 MHz differential reference clock */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_SATA1_AXI, MMUSB_CLK_100MHZ); /* 100 MHz axi clk controller #0 (50 - 100 MHz) */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB2_PHY0_REF, MMUSB_CLK_50MHZ); /* 50 MHz max reference PHY #0 clock */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB2_PHY1_REF, MMUSB_CLK_50MHZ); /* 50 MHz max reference PHY #1 clock */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB2_AXI, MMUSB_CLK_50MHZ); /* 50 MHz axi clock */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB2_SOFITP, MMUSB_CLK_100MHZ); /* 100 MHz reference clock for SOF and ITP counter (16.129 - 125 MHz) */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_PHY0_REF, MMUSB_CLK_100MHZ); /* 100 MHz differential reference clock PHY #0 */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_PHY1_REF, MMUSB_CLK_100MHZ); /* 100 MHz differential reference clock PHY #1 */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_PHY2_REF, MMUSB_CLK_50MHZ); /* 50 MHz max reference PHY #2 clock */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_PHY3_REF, MMUSB_CLK_50MHZ); /* 50 MHz max reference PHY #3 clock */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_AXI, MMUSB_CLK_133MHZ); /* 133 MHz axi clock */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_SOFITP, MMUSB_CLK_100MHZ); /* 100 MHz reference clock for SOF and ITP counter (16.129 - 125 MHz) */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_USB3_SUSPEND, MMUSB_CLK_100MHZ); /* 100 MHz suspend clock for low power state (P3) (32 kHz - 125 MHz) */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_SMMU, MMUSB_CLK_400MHZ); /* 400 MHz axi clk (200 - 400 MHz) */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_DMACM2M, MMUSB_CLK_200MHZ); /* 200 MHz - temp value (250 MHz axi clk (100 - 250 MHz)) */
+ cmu_clkch_enable_by_base(MMUSB_CMU0_CLKCHCTL_GIC, MMUSB_CLK_160MHZ); /* 160 MHz */
/* SATA clocks */
reg = mmio_read_32(MMUSB_GPR_SATAPHY_CLK);
mmio_write_32(MMUSB_GPR_MMRST, reg);
/* Enable non-secure access */
- mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_USB2, NIC_GPV_REGIONSEC_NONSECURE);
- mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_USB3, NIC_GPV_REGIONSEC_NONSECURE);
- mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_SATA0, NIC_GPV_REGIONSEC_NONSECURE);
- mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_SATA1, NIC_GPV_REGIONSEC_NONSECURE);
- mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_SMMU, NIC_GPV_REGIONSEC_NONSECURE);
- mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_GIC, NIC_GPV_REGIONSEC_NONSECURE);
- mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_DMACN, NIC_GPV_REGIONSEC_NONSECURE);
+ mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_USB2, NIC_GPV_REGIONSEC_NONSECURE);
+ mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_USB3, NIC_GPV_REGIONSEC_NONSECURE);
+ mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_SATA0, NIC_GPV_REGIONSEC_NONSECURE);
+ mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_SATA1, NIC_GPV_REGIONSEC_NONSECURE);
+ mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_SMMU, NIC_GPV_REGIONSEC_NONSECURE);
+ mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_GIC, NIC_GPV_REGIONSEC_NONSECURE);
+ mmio_write_32(MMUSB_NIC_CFG_GPV_REGIONSEC_DMACM2MN, NIC_GPV_REGIONSEC_NONSECURE);
/* CHC */
mmio_write_32(MMUSB_GPR_SATA0_AXI_SB, 0xa0000); /* ARDOMAIN 2 / AWDOMAIN 2 (0xa0000 = Coherent ReadOnce + WriteUnique) */
* by a clock channel to minimize jitter.
*/
const cmu_pll_ctl_vals_t mmvdec_cmu0_pll_ctls = {
- 0, 0, 0x6000000000, 0, 0x2c, 0, 0x2c
+ 0, 0, 0x6000000000, 0, -20, 0, -20
};
cmu_pll_on(MMVDEC_CMU0_BASE, &mmvdec_cmu0_pll_ctls);
void mmxgbe_init(void)
{
- const cmu_pll_ctl_vals_t mmxgbe_cmu0_pll_ctls = { 0, 0, 0x6400000000, 0, 0x2c, 0, 0x2c };
- const cmu_pll_ctl_vals_t mmxgbe_cmu1_pll_ctls = { 0, 0x6b, 0xca00000000, 0, 0x2c, 0, 0x2c }; /* 25.25 MHz */
+ const cmu_pll_ctl_vals_t mmxgbe_cmu0_pll_ctls = {
+ 0, 0, 0x6400000000, 0, -20, 0, -20
+ };
mmio_clrbits_32(MMXGBE_GPR_MMRST,
MMXGBE_GPR_MMRST_NICCFGS |
cmu_clkch_enable_by_base(MMXGBE_CMU0_CLKCHCTL_HDMI_AUDIO_ACLK, 10); /* 125.0 MHz */
cmu_clkch_enable_by_base(MMXGBE_CMU0_CLKCHCTL_HDMI_SFR0, 50); /* 25.0 MHz */
- cmu_pll_on(MMXGBE_CMU1_BASE, &mmxgbe_cmu1_pll_ctls);
- cmu_clkch_enable_by_base(MMXGBE_CMU1_CLKCHCTL_HDMI_SFR1, 1); /* 594.0 MHz */
-
/* Deassert XGMAC resets */
mmio_clrbits_32(MMXGBE_GPR_MMRST,
MMXGBE_GPR_MMRST_XGBE0PWRON |
/*
- * Copyright (c) 2018-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2018-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <drivers/arm/gicv3.h>
-#include <drivers/delay_timer.h>
#include <lib/psci/psci.h>
#include <lib/utils_def.h>
#include <plat/arm/common/plat_arm.h>
#include <baikal_gicv3.h>
#include <bm1000_private.h>
#if defined(BAIKAL_MBM10) || defined(BAIKAL_MBM20)
-#include <dw_i2c.h>
-#define MBM_BMC_I2C_BUS MMAVLSP_I2C1_BASE
-#define MBM_BMC_I2C_ADDR 0x08
-#define MBM_BMC_REG_PWROFF_RQ 0x05
-#define MBM_BMC_REG_PWROFF_RQ_OFF 0x01
-#define MBM_BMC_REG_PWROFF_RQ_RESET 0x02
+#include <mbm_bmc.h>
#endif
#include <platform_def.h>
static int bm1000_validate_power_state(unsigned int power_state, psci_power_state_t *req_state)
{
- unsigned i;
- unsigned state_id;
+ unsigned int i;
+ unsigned int state_id;
/*
* The table storing the valid idle power states. Ensure that the
* The table must be terminated by a NULL entry.
*/
static const unsigned int idle_states[] = {
- /* state-id - 0x01 */
+ /* state-id - 0x000 0001 */
bm1000_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN,
PLAT_LOCAL_STATE_RET,
MPIDR_AFFLVL0,
PSTATE_TYPE_STANDBY),
- /* state-id - 0x02 */
- bm1000_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN,
- PLAT_LOCAL_STATE_OFF,
- MPIDR_AFFLVL0,
- PSTATE_TYPE_POWERDOWN),
- /* state-id - 0x22 */
- bm1000_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF,
- PLAT_LOCAL_STATE_OFF,
- MPIDR_AFFLVL1,
- PSTATE_TYPE_POWERDOWN),
+ /* ending element of idle_states */
0
};
static int bm1000_validate_ns_entrypoint(uintptr_t entrypoint)
{
- unsigned region;
+ unsigned int region;
uint64_t region_descs[3][2];
int ret;
static int bm1000_pwr_domain_on(u_register_t mpidr)
{
volatile uint64_t *const hold_base = (uint64_t *)BAIKAL_HOLD_BASE;
- const unsigned pos = plat_core_pos_by_mpidr(mpidr);
+ const unsigned int pos = plat_core_pos_by_mpidr(mpidr);
if (hold_base[pos] == BAIKAL_HOLD_STATE_WAIT) {
/* It is cold boot of a secondary core */
static void bm1000_pwr_domain_suspend(const psci_power_state_t *target_state)
{
+ if (target_state->pwr_domain_state[MPIDR_AFFLVL0] == PLAT_LOCAL_STATE_RET) {
+ return;
+ }
+
+ /* Code shouldn't go futher till there are no idle_states[], containing 0x2 or 0x22 */
ERROR("%s: operation not supported\n", __func__);
panic();
}
static void bm1000_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
{
+ if (target_state->pwr_domain_state[MPIDR_AFFLVL0] == PLAT_LOCAL_STATE_RET) {
+ return;
+ }
+
+ /* Code shouldn't go futher till there are no idle_states[], containing 0x2 or 0x22 */
ERROR("%s: operation not supported\n", __func__);
panic();
}
{
dsb();
#if defined(BAIKAL_MBM10) || defined(BAIKAL_MBM20)
- const uint8_t offreq[] = {
- MBM_BMC_REG_PWROFF_RQ,
- MBM_BMC_REG_PWROFF_RQ_OFF
- };
-
- INFO("%s\n", __func__);
- i2c_txrx(MBM_BMC_I2C_BUS,
- MBM_BMC_I2C_ADDR, &offreq, sizeof(offreq), NULL, 0);
-
- mdelay(4000);
+ mbm_bmc_pwr_off();
#endif
ERROR("%s: operation not supported\n", __func__);
for (;;) {
{
dsb();
#if defined(BAIKAL_MBM10) || defined(BAIKAL_MBM20)
- const uint8_t rstreq[] = {
- MBM_BMC_REG_PWROFF_RQ,
- MBM_BMC_REG_PWROFF_RQ_RESET
- };
-
- INFO("%s\n", __func__);
- i2c_txrx(MBM_BMC_I2C_BUS,
- MBM_BMC_I2C_ADDR, &rstreq, sizeof(rstreq), NULL, 0);
-
- mdelay(4000);
+ mbm_bmc_pwr_rst();
#endif
ERROR("%s: operation not supported\n", __func__);
for (;;) {
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <lib/pmf/pmf.h>
#include <libfdt.h>
#include <baikal_pvt.h>
#include <baikal_scp.h>
#include <baikal_sip_svc.h>
#include <bm1000_cmu.h>
+#include <bm1000_def.h>
+#include <bm1000_efuse.h>
#include <bm1000_smmu.h>
#include <platform_def.h>
static int baikal_get_cmu_descriptors(void *fdt)
{
- unsigned cmuidx = 0;
+ unsigned int cmuidx = 0;
int offset = 0;
+ uint64_t fpllreq;
while (1) {
offset = fdt_next_node(fdt, offset, NULL);
/* clear */
cmu->base = 0;
- cmu->name = NULL;
cmu->frefclk = 0;
- cmu->fpllmin = 0;
- cmu->fpllmax = 0;
- cmu->fpllreq = 0;
cmu->deny_pll_reconf = false;
prop = fdt_getprop(fdt, cmu_offset, "reg", &proplen);
continue;
}
- cmu->fpllreq = fdt32_to_cpu(*prop);
+ fpllreq = fdt32_to_cpu(*prop);
prop = fdt_getprop(fdt, cmu_offset, "clock-indices", &proplen);
if (prop != NULL) {
cmu->deny_pll_reconf = true;
}
- cmu->name = fdt_getprop(fdt, cmu_offset, "clock-output-names", NULL);
- INFO("CMU @ base=0x%08lx name=%s clk=%lu freq=%lu reconf=%d min=%lu max=%lu chans=%d\n",
+ if (cmu->base != MMAVLSP_CMU1_BASE && cmu->base != MMXGBE_CMU1_BASE) {
+ cmu_pll_set_rate(cmu->base, cmu->frefclk, fpllreq);
+ }
+
+ INFO("CMU @ base=0x%08lx clk=%lu freq=%lu reconf=%d chans=%d\n",
cmu->base,
- cmu->name,
cmu->frefclk,
- cmu->fpllreq,
+ fpllreq,
cmu->deny_pll_reconf,
- cmu->fpllmin,
- cmu->fpllmax,
num_of_chans);
++cmuidx;
int ret;
void *fdt = (void *)(uintptr_t)BAIKAL_SEC_DTB_BASE;
+#if ENABLE_PMF
+ if (pmf_setup() != 0) {
+ return 1;
+ }
+#endif
ret = fdt_open_into(fdt, fdt, BAIKAL_DTB_MAX_SIZE);
if (ret < 0) {
ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
void *handle,
u_register_t flags)
{
+ uint32_t local_smc_fid = smc_fid;
uint64_t ret;
uint64_t data[4];
SMC_RET1(handle, SMC_UNK);
}
- switch (smc_fid) {
+ if (GET_SMC_CC(smc_fid) == SMC_32) {
+ /* 32-bit function, clear top parameter bits */
+ x1 = (uint32_t)x1;
+ x2 = (uint32_t)x2;
+ x3 = (uint32_t)x3;
+ x4 = (uint32_t)x4;
+
+ /*
+ * Convert SMC FID to SMC64 to support SMC32/SMC64.
+ * SMC64 calls are expected to be the 64-bit equivalent
+ * to the 32-bit call, where applicable (ARM DEN 0028E).
+ */
+ local_smc_fid |= SMC_64 << FUNCID_CC_SHIFT;
+ }
+
+ switch (local_smc_fid) {
case BAIKAL_SMC_FLASH_ERASE:
case BAIKAL_SMC_FLASH_INIT:
case BAIKAL_SMC_FLASH_POSITION:
SMC_RET3(handle, ret, data[0], data[1]);
}
break;
- case BAIKAL_SMC_PVT_ID:
+ case BAIKAL_SMC_PVT_CMD:
if (x1 == PVT_READ) {
- ret = (uint64_t)pvt_read_reg((uint32_t)x2, (uint32_t)x3);
+ ret = pvt_read_reg(x2, x3);
} else if (x1 == PVT_WRITE) {
- ret = (uint64_t)pvt_write_reg((uint32_t)x2, (uint32_t)x3, (uint32_t)x4);
+ ret = pvt_write_reg(x2, x3, x4);
} else {
ERROR("%s: unhandled PVT SMC, x1:0x%lx\n", __func__, x1);
ret = SMC_UNK;
}
break;
- case BAIKAL_SMC_VDEC_SMMU_SET_CACHE:
- ret = mmvdec_smmu_set_domain_cache(x1, x2, x3);
- break;
- case BAIKAL_SMC_VDEC_SMMU_GET_CACHE:
- ret = mmvdec_smmu_get_domain_cache();
- break;
- case BAIKAL_SMC_VDU_UPDATE:
- ret = scp_cmd('V', x1, x2);
- break;
- case BAIKAL_SMC_SCP_LOG_DISABLE:
- ret = scp_cmd('T', 0, 0);
- break;
- case BAIKAL_SMC_SCP_LOG_ENABLE:
- ret = scp_cmd('t', 0, 0);
- break;
- case BAIKAL_SMC_FLASH_LOCK:
- ret = scp_cmd('L', x1, 0);
- break;
- default:
+ case BAIKAL_SMC_CMU_CMD:
switch (x2) {
case BAIKAL_SMC_CMU_PLL_SET_RATE:
ret = cmu_pll_set_rate(x1, x4, x3);
ret = cmu_pll_is_enabled(x1);
break;
case BAIKAL_SMC_CMU_CLKCH_SET_RATE:
- ret = cmu_clkch_set_rate((uint32_t)x4, x1, x3);
+ ret = cmu_clkch_set_rate(x4, x1, x3);
break;
case BAIKAL_SMC_CMU_CLKCH_GET_RATE:
- ret = cmu_clkch_get_rate((uint32_t)x4, x1);
+ ret = cmu_clkch_get_rate(x4, x1);
break;
case BAIKAL_SMC_CMU_CLKCH_ENABLE:
- ret = cmu_clkch_enable((uint32_t)x4, x1);
+ ret = cmu_clkch_enable(x4, x1);
break;
case BAIKAL_SMC_CMU_CLKCH_DISABLE:
- ret = cmu_clkch_disable((uint32_t)x4, x1);
+ ret = cmu_clkch_disable(x4, x1);
break;
case BAIKAL_SMC_CMU_CLKCH_ROUND_RATE:
- ret = cmu_clkch_round_rate((uint32_t)x4, x1, x3);
+ ret = cmu_clkch_round_rate(x4, x1, x3);
break;
case BAIKAL_SMC_CMU_CLKCH_IS_ENABLED:
- ret = cmu_clkch_is_enabled((uint32_t)x4, x1);
+ ret = cmu_clkch_is_enabled(x4, x1);
break;
default:
- ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
+ ERROR("%s: unhandled CMU SMC, x2:0x%lx\n", __func__, x2);
ret = SMC_UNK;
break;
}
-
+ break;
+ case BAIKAL_SMC_VDEC_SMMU_SET_CACHE:
+ ret = mmvdec_smmu_set_domain_cache(x1, x2, x3);
+ break;
+ case BAIKAL_SMC_VDEC_SMMU_GET_CACHE:
+ ret = mmvdec_smmu_get_domain_cache();
+ break;
+ case BAIKAL_SMC_VDU_UPDATE:
+ ret = scp_cmd('V', x1, x2);
+ break;
+ case BAIKAL_SMC_SCP_LOG_DISABLE:
+ ret = scp_cmd('T', 0, 0);
+ break;
+ case BAIKAL_SMC_SCP_LOG_ENABLE:
+ ret = scp_cmd('t', 0, 0);
+ break;
+ case BAIKAL_SMC_EFUSE_GET_LOT:
+ ret = efuse_get_lot();
+ break;
+ case BAIKAL_SMC_EFUSE_GET_SERIAL:
+ ret = efuse_get_serial();
+ break;
+ case BAIKAL_SMC_EFUSE_GET_MAC:
+ ret = efuse_get_mac();
+ break;
+ case BAIKAL_SMC_FLASH_LOCK:
+ ret = scp_cmd('L', x1, 0);
+ break;
+ default:
+#if ENABLE_PMF
+ /* Dispatch PMF calls to PMF SMC handler and return its return value */
+ if (is_pmf_fid(smc_fid)) {
+ return pmf_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
+ }
+#endif
+ ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
+ ret = SMC_UNK;
break;
}
/*
* Copyright (c) 2020-2023, Baikal Electronics, JSC. All rights reserved.
*
- * Author: Pavel Parkhomenko <pavel.parkhomenko@baikalelectronics.ru>
+ * Author: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
+#include <lib/utils.h>
#include <libfdt.h>
+#include <stdio.h>
#include <baikal_def.h>
#include <baikal_fdt.h>
+#include <bm1000_cmu.h>
#include <bm1000_private.h>
#include <dw_gpio.h>
#include <platform_def.h>
#include "bm1000_splash.h"
#include "bm1000_vdu.h"
-#define BAIKAL_VDU_DEFAULT_BRIGHTNESS 0x7f /* 50% duty cycle */
+#define VDU_PLL_REF_CLOCK 27000000
+#define LVDS_VDU_AXI_CLOCK 300000000 /* set in accordance with bm1000_mmavlsp.c */
+#define BAIKAL_VDU_DEFAULT_BRIGHTNESS 0x7f /* 50% duty cycle */
#define BAIKAL_VDU_DEFAULT_PWM_FREQ 10000
-modeline_t lvds_video_mode = {148500000, 2, BAIKAL_LVDS_VESA_24,
- 1920, 88, 44, 148,
- 1080, 4, 5, 36};
-modeline_t hdmi_video_mode = {25250000, 0, 0, 640, 16, 96, 48, 480, 10, 2, 33};
-static int gpio_pin = -1;
-static int gpio_polarity = -1;
+const modeline_t lvds_video_mode = {148500000, 1920, 88, 44, 148, 1080, 4, 5, 36, 0, 0, 0,
+ 2, BAIKAL_LVDS_VESA_24, 16, 0, MMAVLSP_CMU1_BASE, VDU_PLL_REF_CLOCK, 1};
+const modeline_t hdmi_video_mode = {25250000, 640, 16, 96, 48, 480, 10, 2, 33, 0, 0, 0,
+ 0, 0, 0, 0, MMXGBE_CMU1_BASE, VDU_PLL_REF_CLOCK, 1};
+
+char sdk_version[SDK_VERSION_SIZE];
+char msg_buf[300];
#define FDT_GET_PANEL_TIMING(name, result) \
do { \
prop = fdt_getprop(fdt, node, "enable-gpios", &plen);
if (prop && plen == 3 * sizeof(*prop)) {
- gpio_pin = fdt32_to_cpu(*(prop + 1));
+ modeline->gpio_pin = fdt32_to_cpu(*(prop + 1));
if (!fdt32_to_cpu(*(prop + 2))) {
- gpio_polarity = 1;
+ modeline->gpio_polarity = 1;
} else {
- gpio_polarity = 0;
+ modeline->gpio_polarity = 0;
}
gpio_found = 1;
}
}
-void wait_for_vblank(uint64_t vdu_base)
-{
- uint32_t irq;
-
- do {
- irq = mmio_read_32(vdu_base + BAIKAL_VDU_ISR);
- } while (!(irq & BAIKAL_VDU_INTR_VCT));
-
- mmio_write_32(vdu_base + BAIKAL_VDU_ISR, BAIKAL_VDU_INTR_VCT);
-
- do {
- irq = mmio_read_32(vdu_base + BAIKAL_VDU_ISR);
- } while (!(irq & BAIKAL_VDU_INTR_VCT));
-}
-
-void vdu_set_fb(uint64_t vdu_base, uint32_t fb_base, modeline_t *mode, int fb_cpp)
+void vdu_set_fb(uint64_t vdu_base, uint32_t fb_base, const modeline_t *mode, int fb_cpp)
{
uint32_t ctl;
uint32_t fb_end;
mmio_write_32(vdu_base + BAIKAL_VDU_CR1, ctl);
}
-void vdu_init(uint64_t vdu_base, uint32_t fb_base, modeline_t *mode)
+void vdu_init(uint64_t vdu_base, uint32_t fb_base, const modeline_t *mode)
{
uint32_t ctl, pwmfr, gpio, hfp = mode->hfp, hsw = mode->hsync;
+ int gpio_pin = mode->gpio_pin, gpio_polarity = mode->gpio_polarity;
+ uint64_t clock;
+
+ /* Set up PLL */
+ clock = vdu_base == MMAVLSP_VDU_BASE ? mode->clock * 7 : mode->clock;
+ cmu_pll_set_rate(mode->cmu_base, mode->cmu_frefclk, clock);
+ if (!cmu_pll_is_enabled(mode->cmu_base)) {
+ cmu_pll_set_gains(mode->cmu_base, 0, -20, 0, -20);
+ cmu_pll_enable(mode->cmu_base);
+ }
+ if (vdu_base == MMXGBE_VDU_BASE) {
+ cmu_clkch_enable_by_base(MMXGBE_CMU1_CLKCHCTL_HDMI_SFR1, 1);
+ }
/* Set Timings */
if (vdu_base == MMAVLSP_VDU_BASE && mode->ports == 2) {
ctl = mmio_read_32(vdu_base + BAIKAL_VDU_CR1) & BAIKAL_VDU_CR1_BPP_MASK;
/* Set flags */
- ctl |= BAIKAL_VDU_CR1_LCE | BAIKAL_VDU_CR1_DEP | BAIKAL_VDU_CR1_FDW_16_WORDS;
+ ctl |= BAIKAL_VDU_CR1_LCE | BAIKAL_VDU_CR1_FDW_16_WORDS;
+
+ /* Setup polarities for HSYNC, VSYNC and DE */
+ if (mode->hspol_inv) {
+ ctl |= BAIKAL_VDU_CR1_HSP;
+ }
+
+ if (mode->vspol_inv) {
+ ctl |= BAIKAL_VDU_CR1_VSP;
+ }
+
+ if (!mode->depol_inv) {
+ ctl |= BAIKAL_VDU_CR1_DEP;
+ }
/* Set 18 or 24 bit output */
if (vdu_base == MMAVLSP_VDU_BASE) { /* LVDS VDU */
/* Hold PWM Clock Domain Reset, disable clocking */
mmio_write_32(vdu_base + BAIKAL_VDU_PWMFR, 0);
- pwmfr = BAIKAL_VDU_PWMFR_PWMFCD(mode->clock / BAIKAL_VDU_DEFAULT_PWM_FREQ - 1) | BAIKAL_VDU_PWMFR_PWMFCI;
+ pwmfr = BAIKAL_VDU_PWMFR_PWMFCD(LVDS_VDU_AXI_CLOCK / BAIKAL_VDU_DEFAULT_PWM_FREQ - 1);
mmio_write_32(vdu_base + BAIKAL_VDU_PWMFR, pwmfr);
mmio_write_32(vdu_base + BAIKAL_VDU_PWMDCR, BAIKAL_VDU_DEFAULT_BRIGHTNESS);
hdmi_phy_power_on();
}
-void hdmi_init_av_composer(modeline_t *mode)
+void hdmi_init_av_composer(const modeline_t *mode)
{
uint32_t val, mask;
mmio_write_32(BAIKAL_HDMI_FC_INVIDCONF, val);
}
-void hdmi_enable_video_path(modeline_t *mode)
+void hdmi_enable_video_path(const modeline_t *mode)
{
uint32_t val;
mmio_write_32(BAIKAL_HDMI_FC_VSYNCINWIDTH, (mode->vsync - mode->vfp) & 0xff);
}
-void bmp_get_dimensions(uint8_t *bmp_file, int *width, int *height)
+void bmp_get_dimensions(const uint8_t *bmp_file, int *width, int *height)
{
bmp_header_t bmp;
*height = bmp.height;
}
-int bmp_to_fb(uintptr_t fb, modeline_t *mode, uint8_t *bmp_file, int dx, int dy, int clear_screen)
+int bmp_get_cpp(const uint8_t *bmp_file)
+{
+ bmp_header_t bmp;
+
+ memcpy(&bmp, bmp_file + 2, sizeof(bmp)); /* skip 2-byte BMP signature */
+ if ((bmp.bpp != 16 && bmp.bpp != 24 && bmp.bpp != 32) ||
+ bmp.planes != 1) {
+ return 0;
+ }
+ if (bmp.bpp == 16) {
+ return 2;
+ } else { /* bmp.bpp == 24 or 32 */
+ return 4;
+ }
+}
+
+int bmp_to_fb(uintptr_t fb, const modeline_t *mode, const uint8_t *bmp_file, int dx, int dy, int clear_screen)
{
bmp_header_t bmp;
int fb_cpp;
int x_offs;
int y_offs;
int data_size;
- uint8_t *last_line;
- uint8_t *first_line;
- uint8_t *src;
- uint8_t *dst;
- uint8_t *s;
- uint8_t *d;
+ const uint8_t *last_line;
+ const uint8_t *first_line;
+ const uint8_t *src, *s;
+ uint8_t *dst, *d;
memcpy(&bmp, bmp_file + 2, sizeof(bmp)); /* skip 2-byte BMP signature */
line_width = bmp.width * bmp.bpp / 8;
fb_line_width = fb_width * fb_cpp;
fb_size = fb_line_width * fb_height;
if (clear_screen) {
- memset((void *)fb, 0, fb_size);
+ zero_normalmem((void *)fb, fb_size);
}
x_offs = (fb_width - bmp.width) / 2 + dx;
return fb_cpp;
}
-void hdmi_early_splash(uint8_t *bmp_file)
+void fb_print(void *fb_base, const modeline_t *mode, int fb_cpp, int row, int col, const char *s)
+{
+ int i, j, ch, line_width, char_width, max_cols, max_rows;
+ const uint8_t *f;
+ unsigned int color;
+ uint8_t *pix;
+ int x = col;
+ int y = row;
+
+ if (!fb_base || !mode || !s || (fb_cpp != 2 && fb_cpp != 4) || FONT_WIDTH > 8) {
+ return;
+ }
+
+ line_width = mode->hact * fb_cpp;
+ char_width = FONT_WIDTH * fb_cpp;
+ max_cols = mode->hact / FONT_WIDTH;
+ max_rows = mode->vact / FONT_HEIGHT;
+ while ((ch = *s++) && x < max_cols && y < max_rows) {
+ if (ch == '\n') {
+ x = 0;
+ y++;
+ } else if (ch >= FONT_FIRST_CHAR && ch <= FONT_LAST_CHAR) {
+ pix = fb_base + y * FONT_HEIGHT * line_width + x * char_width;
+ f = &font[(ch - FONT_FIRST_CHAR) * FONT_HEIGHT];
+ for (i = 0; i < FONT_HEIGHT; i++) {
+ for (j = 1 << (FONT_WIDTH - 1); j > 0; j >>= 1) {
+ color = (*f & j) ? 0xffffffff : 0;
+ if (fb_cpp == 2) {
+ *((uint16_t *)pix) = color;
+ } else { /* fb_cpp == 4 */
+ *((uint32_t *)pix) = color;
+ }
+ pix += fb_cpp;
+ }
+ pix += line_width - char_width;
+ f++;
+ }
+ x++;
+ }
+ }
+ flush_dcache_range((uintptr_t)fb_base, line_width * mode->vact);
+}
+
+void print_sdk_version(uintptr_t fb_base, const modeline_t *mode, int w1, int h1, const char *version)
+{
+ int w2 = strlen(version) * FONT_WIDTH;
+ int h2 = FONT_HEIGHT;
+ int col = ((mode->hact - w1) / 2 + w1 - w2) / FONT_WIDTH;
+ int row = ((mode->vact - h1) / 2 + h1 + h2) / FONT_HEIGHT;
+
+ fb_print((void *) fb_base, mode, 4, row, col, version);
+}
+
+void early_splash(uintptr_t vdu_base, uintptr_t fb_base, const modeline_t *mode, int fb_cpp, const char *msg)
+{
+ zero_normalmem((void *)fb_base, mode->hact * mode->vact * fb_cpp);
+ if (msg) {
+ fb_print((void *) fb_base, mode, fb_cpp, 0, 0, msg);
+ }
+ vdu_set_fb(vdu_base, fb_base, mode, fb_cpp);
+ vdu_init(vdu_base, fb_base, mode);
+}
+
+void hdmi_tx_init(void)
{
- int fb_cpp;
-#ifdef BAIKAL_HDMI_CLKEN_GPIO_PIN
- gpio_out_rst(MMAVLSP_GPIO32_BASE, BAIKAL_HDMI_CLKEN_GPIO_PIN);
- gpio_dir_set(MMAVLSP_GPIO32_BASE, BAIKAL_HDMI_CLKEN_GPIO_PIN);
-#endif
hdmi_init_av_composer(&hdmi_video_mode);
hdmi_phy_configure();
hdmi_enable_video_path(&hdmi_video_mode);
- if (bmp_file) {
- fb_cpp = bmp_to_fb((uintptr_t)FB1_BASE, &hdmi_video_mode, bmp_file, 0, 0, 1);
- vdu_set_fb(MMXGBE_VDU_BASE, FB1_BASE, &hdmi_video_mode, fb_cpp);
+}
+
+void lvds_early_splash(const char *msg)
+{
+ early_splash(MMAVLSP_VDU_BASE, FB0_BASE, &lvds_video_mode, 4, msg);
+}
+
+void hdmi_early_splash(const char *msg)
+{
+ hdmi_tx_init();
+ early_splash(MMXGBE_VDU_BASE, FB1_BASE, &hdmi_video_mode, 4, msg);
+}
+
+void display_logo_and_version(uintptr_t vdu_base, uintptr_t fb_base, const modeline_t *mode, const uint8_t *logo)
+{
+ int w1 = 0, h1 = 0;
+ uint32_t reg;
+
+ reg = mmio_read_32(vdu_base + BAIKAL_VDU_CR1);
+ reg &= ~BAIKAL_VDU_CR1_LCE;
+ mmio_write_32(vdu_base + BAIKAL_VDU_CR1, reg);
+
+ /* We do not support 16-bit and lower color resolutions here */
+ if (bmp_get_cpp(logo) == 4) {
+ /* Put SDK version just below the logo, aligned to its right edge */
+ bmp_to_fb(fb_base, mode, logo, 0, 0, 1);
+ bmp_get_dimensions(logo, &w1, &h1);
+ } else {
+ zero_normalmem((void *)fb_base, mode->hact * mode->vact * 4);
}
+#ifdef SDK_VERSION
+ print_sdk_version(fb_base, mode, w1, h1, sdk_version);
+#endif
+ vdu_set_fb(vdu_base, fb_base, mode, 4);
- vdu_init(MMXGBE_VDU_BASE, FB1_BASE, &hdmi_video_mode);
+ reg = mmio_read_32(vdu_base + BAIKAL_VDU_CR1);
+ reg |= BAIKAL_VDU_CR1_LCE;
+ mmio_write_32(vdu_base + BAIKAL_VDU_CR1, reg);
}
/*
* Copyright (c) 2020-2021, Baikal Electronics, JSC. All rights reserved.
*
- * Author: Pavel Parkhomenko <pavel.parkhomenko@baikalelectronics.ru>
+ * Author: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
+#include "bm1000_font.h"
+
+#define SDK_VERSION_SIZE 40
+
typedef enum {
BAIKAL_LVDS_JEIDA_18,
BAIKAL_LVDS_VESA_24
typedef struct {
uint32_t clock;
- int ports;
- lvds_data_mapping_t data_mapping;
uint32_t hact;
uint32_t hfp;
uint32_t hsync;
uint32_t vfp;
uint32_t vsync;
uint32_t vbp;
+ uint32_t hspol_inv;
+ uint32_t vspol_inv;
+ uint32_t depol_inv;
+ int ports; /* LVDS only */
+ lvds_data_mapping_t data_mapping; /* LVDS only */
+ int gpio_pin; /* LVDS only */
+ int gpio_polarity; /* LVDS only */
+ uintptr_t cmu_base;
+ uint64_t cmu_frefclk;
+ int enabled;
} modeline_t;
-extern modeline_t hdmi_video_mode;
-extern modeline_t lvds_video_mode;
-
typedef struct {
/* 2-byte signature is omitted (placed just before file_size) */
uint32_t file_size;
uint16_t bpp : 16;
} bmp_header_t;
-void hdmi_early_splash(uint8_t *bmp_file);
-void bmp_get_dimensions(uint8_t *bmp_file, int *width, int *height);
-int bmp_to_fb(uintptr_t fb, modeline_t *mode, uint8_t *bmp_file, int dx, int dy, int clear_screen);
-void vdu_init(uint64_t vdu_base, uint32_t fb_base, modeline_t *mode);
-void vdu_set_fb(uint64_t vdu_base, uint32_t fb_base, modeline_t *mode, int fb_cpp);
-void wait_for_vblank(uint64_t vdu_base);
+extern const modeline_t hdmi_video_mode;
+extern const modeline_t lvds_video_mode;
+extern char sdk_version[];
+
+void hdmi_tx_init(void);
+void print_sdk_version(uintptr_t fb_base, const modeline_t *mode, int w1, int h1, const char *version);
+void early_splash(uintptr_t vdu_base, uintptr_t fb_base, const modeline_t *mode, int fb_cpp, const char *msg);
+void lvds_early_splash(const char *msg);
+void hdmi_early_splash(const char *msg);
+void bmp_get_dimensions(const uint8_t *bmp_file, int *width, int *height);
+int bmp_get_cpp(const uint8_t *bmp_file);
+int bmp_to_fb(uintptr_t fb, const modeline_t *mode, const uint8_t *bmp_file, int dx, int dy, int clear_screen);
+void vdu_init(uint64_t vdu_base, uint32_t fb_base, const modeline_t *mode);
+void vdu_set_fb(uint64_t vdu_base, uint32_t fb_base, const modeline_t *mode, int fb_cpp);
int fdt_get_panel(modeline_t *modeline);
+void display_logo_and_version(uintptr_t vdu_base, uintptr_t fb_base, const modeline_t *mode, const uint8_t *logo);
#endif /* BM1000_SPLASH_H */
*
* SPDX-License-Identifier: BSD-3-Clause
*
- * Parts of this file were based on sources as follows:
- * Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
- * SPDX-License-Identifier: BSD-2-Clause-Patent
*/
#ifndef BM1000_VDU_H
/* Register: HTR */
#define HOR_AXIS_PANEL(hbp, hfp, hsw, hor_res) (uint32_t) \
- ((((uint32_t)(hsw) - 1) << 24) | \
- (uint32_t)((hbp) << 16) | \
- ((uint32_t)((hor_res) / 16) << 8) | \
- ((uint32_t)(hfp) << 0))
+ (((uint32_t)((hsw) - 1) << 24) | \
+ ((uint32_t)(hbp) << 16) | \
+ ((uint32_t)((hor_res) / 16) << 8) | \
+ ((uint32_t)(hfp) << 0))
/* Register: VTR1 */
#define VER_AXIS_PANEL(vbp, vfp, vsw) (uint32_t) \
(((uint32_t)(vbp) << 16) | \
- ( (uint32_t)(vfp) << 8) | \
- ( (uint32_t)(vsw) << 0))
+ ((uint32_t)(vfp) << 8) | \
+ ((uint32_t)(vsw) << 0))
/* Register: HVTER */
#define TIMINGS_EXT(hbp, hfp, hsw, vbp, vfp, vsw) (uint32_t) \
- (((uint32_t)(vsw / 256) << 24) | \
- ( (uint32_t)(hsw / 256) << 16) | \
- ( (uint32_t)(vbp / 256) << 12) | \
- ( (uint32_t)(vfp / 256) << 8) | \
- ( (uint32_t)(hbp / 256) << 4) | \
- ( (uint32_t)(hfp / 256) << 0))
+ (((uint32_t)((vsw) / 256) << 24) | \
+ ((uint32_t)((hsw) / 256) << 16) | \
+ ((uint32_t)((vbp) / 256) << 12) | \
+ ((uint32_t)((vfp) / 256) << 8) | \
+ ((uint32_t)((hbp) / 256) << 4) | \
+ ((uint32_t)((hfp) / 256) << 0))
#define BAIKAL_VDU_CR1_FDW_4_WORDS (0 << 16)
#define BAIKAL_VDU_CR1_FDW_8_WORDS (1 << 16)
static void cmu_pll_div_get(const uintptr_t base, struct plldivs *const plldivs);
static int cmu_pll_div_calc(const uint64_t frefclk, const uint64_t fpllreq, struct plldivs *const plldivs);
static int cmu_pll_div_set(const struct cmu_desc *const cmu, const uint64_t frefclk, const uint64_t fpllreq);
-static int cmu_clkch_div_calc(const struct cmu_desc *const cmu, const unsigned clkch, uint64_t fclkchreq);
-static int cmu_clkch_div_get(const struct cmu_desc *const cmu, const unsigned clkch);
-static uintptr_t cmu_clkch_get_reg(const uintptr_t base, const unsigned clkch);
-static int cmu_clkch_div_set(const struct cmu_desc *const cmu, const unsigned clkch, uint32_t div);
-static struct cmu_desc *const cmu_desc_get_by_base(const uintptr_t base);
+static int cmu_clkch_div_calc(const struct cmu_desc *const cmu, const unsigned int clkch, uint64_t fclkchreq);
+static int cmu_clkch_div_get(const struct cmu_desc *const cmu, const unsigned int clkch);
+static uintptr_t cmu_clkch_get_reg(const uintptr_t base, const unsigned int clkch);
+static int cmu_clkch_div_set(const struct cmu_desc *const cmu, const unsigned int clkch, uint32_t div);
+static struct cmu_desc *cmu_desc_get_by_base(const uintptr_t base);
static int cmu_pll_lock_debounce(const uintptr_t base);
static int cmu_set_core_rate(const struct cmu_desc *const cmu, const uint64_t frefclk, const uint64_t fpllreq);
static int cmu_set_periph_rate(const struct cmu_desc *const cmu, uint64_t frefclk, const uint64_t fpllreq);
const int ret = (mmio_read_32(base + CMU_PLL_CTL0) & CMU_PLL_CTL0_CTL_EN) &&
(mmio_read_32(base + CMU_PLL_CTL6) & CMU_PLL_CTL6_SWEN);
- INFO("%s: base=0x%08lx %s\n", __func__, base, ret ? "enabled" : "disabled");
+ VERBOSE("%s: base=0x%08lx %s\n", __func__, base, ret ? "enabled" : "disabled");
return ret;
}
int err;
if (cmu_pll_is_enabled(base)) {
- INFO("%s: base=0x%08lx already enabled\n", __func__, base);
+ VERBOSE("%s: base=0x%08lx already enabled\n", __func__, base);
return 0;
}
err = cmu_pll_lock_debounce(base);
if (err) {
- ERROR("%s: base=0x%08lx timeout\n", __func__, base);
return err;
}
- INFO("%s: base=0x%08lx enable\n", __func__, base);
+ VERBOSE("%s: base=0x%08lx enable\n", __func__, base);
mmio_setbits_32(base + CMU_PLL_CTL6, CMU_PLL_CTL6_SWEN);
mmio_clrbits_32(base + CMU_PLL_CTL6, CMU_PLL_CTL6_SWRST);
return 0;
int cmu_pll_disable(const uintptr_t base)
{
- INFO("%s: base=0x%08lx disable\n", __func__, base);
+ VERBOSE("%s: base=0x%08lx disable\n", __func__, base);
mmio_clrbits_32(base + CMU_PLL_CTL0, CMU_PLL_CTL0_CTL_EN);
return 0;
}
cmu_pll_div_get(base, &plldivs);
fpll = (frefclk * plldivs.intnf) / (plldivs.nr * plldivs.od);
- INFO("%s: base=0x%08lx rate=%lu\n", __func__, base, fpll);
+ VERBOSE("%s: base=0x%08lx rate=%lu\n", __func__, base, fpll);
return fpll;
}
}
fpll = (frefclk * plldivs.intnf) / (plldivs.nr * plldivs.od);
- INFO("%s: base=0x%08lx rate=%lu\n", __func__, base, fpll);
+ VERBOSE("%s: base=0x%08lx rate=%lu\n", __func__, base, fpll);
return fpll;
}
int cmu_pll_set_rate(const uintptr_t base, uint64_t frefclk, const uint64_t fpllreq)
{
int err;
- struct cmu_desc *const cmu = cmu_desc_get_by_base(base);
+ struct cmu_desc *cmu;
+ struct cmu_desc cmu_default;
if (base == MMAVLSP_CMU0_BASE) {
- INFO("%s: base=0x%08lx skip\n", __func__, base);
+ VERBOSE("%s: base=0x%08lx skip\n", __func__, base);
return -ENXIO;
}
+ cmu = cmu_desc_get_by_base(base);
if (!cmu) {
- return -ENXIO;
+ VERBOSE("%s: base=0x%08lx, descriptor not found\n", __func__, base);
+ cmu = &cmu_default;
+ cmu->base = base;
+ cmu->deny_pll_reconf = false;
+ cmu->frefclk = frefclk;
+ if (cmu->frefclk == 0) {
+ VERBOSE("%s: base=0x%08lx, frefclk not set\n", __func__, base);
+ return -ENXIO;
+ }
}
if (!frefclk) {
}
if (fpllreq == cmu_pll_get_rate(base, frefclk)) {
- INFO("%s: base=0x%08lx rate=%lu already set\n", __func__, base, fpllreq);
+ VERBOSE("%s: base=0x%08lx rate=%lu already set\n", __func__, base, fpllreq);
return 0;
}
err = cmu_set_periph_rate(cmu, frefclk, fpllreq);
}
- INFO("%s: base=0x%08lx name=%s rate=%lu%s\n",
- __func__, base, cmu->name, fpllreq, err ? ", fail" : "");
+ VERBOSE("%s: base=0x%08lx rate=%lu%s\n",
+ __func__, base, fpllreq, err ? ", fail" : "");
return err;
}
-int cmu_clkch_is_enabled(const uintptr_t base, const unsigned clkch)
+int cmu_clkch_is_enabled(const uintptr_t base, const unsigned int clkch)
{
int ret;
uintptr_t clkch_reg = cmu_clkch_get_reg(base, clkch);
}
ret = (mmio_read_32(clkch_reg) & CMU_CLKCH_CTL_CLK_EN) && cmu_pll_is_enabled(base);
- INFO("%s: base=0x%08lx ch=%u %s\n", __func__, base, clkch, ret ? "enabled" : "disabled");
+ VERBOSE("%s: base=0x%08lx ch=%u %s\n", __func__, base, clkch, ret ? "enabled" : "disabled");
return ret;
}
-int cmu_clkch_enable(const uintptr_t base, const unsigned clkch)
+int cmu_clkch_enable(const uintptr_t base, const unsigned int clkch)
{
uintptr_t clkch_reg;
uint64_t timeout;
}
if (cmu_clkch_is_enabled(base, clkch)) {
- INFO("%s: base=0x%08lx ch=%u already enabled\n", __func__, base, clkch);
+ VERBOSE("%s: base=0x%08lx ch=%u already enabled\n", __func__, base, clkch);
return 0;
}
mmio_setbits_32(clkch_reg, CMU_CLKCH_CTL_CLK_EN);
for (timeout = timeout_init_us(100000); !timeout_elapsed(timeout);) {
if (mmio_read_32(clkch_reg) & CMU_CLKCH_CTL_CLK_RDY) {
- INFO("%s: base=0x%08lx ch=%u enable\n", __func__, base, clkch);
+ VERBOSE("%s: base=0x%08lx ch=%u enable\n", __func__, base, clkch);
mmio_clrbits_32(clkch_reg, CMU_CLKCH_CTL_SWRST);
return 0;
}
return -ETIMEDOUT;
}
-int cmu_clkch_disable(const uintptr_t base, const unsigned clkch)
+int cmu_clkch_disable(const uintptr_t base, const unsigned int clkch)
{
uintptr_t clkch_reg = cmu_clkch_get_reg(base, clkch);
return -ENXIO;
}
- INFO("%s: base=0x%08lx ch=%u disable\n", __func__, base, clkch);
+ VERBOSE("%s: base=0x%08lx ch=%u disable\n", __func__, base, clkch);
mmio_clrbits_32(clkch_reg, CMU_CLKCH_CTL_CLK_EN);
return 0;
}
-int64_t cmu_clkch_get_rate(const uintptr_t base, const unsigned clkch)
+int64_t cmu_clkch_get_rate(const uintptr_t base, const unsigned int clkch)
{
const struct cmu_desc *const cmu = cmu_desc_get_by_base(base);
uint32_t div;
}
rate = fpll / div;
- INFO("%s: rate=%ld\n", __func__, rate);
+ VERBOSE("%s: rate=%ld\n", __func__, rate);
return rate;
}
-int64_t cmu_clkch_round_rate(const uintptr_t base, const unsigned clkch, const uint64_t fclkchreq)
+int64_t cmu_clkch_round_rate(const uintptr_t base, const unsigned int clkch, const uint64_t fclkchreq)
{
const struct cmu_desc *const cmu = cmu_desc_get_by_base(base);
int64_t ret;
ret = cmu_pll_round_rate(base, cmu->frefclk, fclkchreq);
}
- INFO("%s: base=0x%08lx ch=%u rate=%lu round=%ld\n",
- __func__, base, clkch, fclkchreq, ret);
+ VERBOSE("%s: base=0x%08lx ch=%u rate=%lu round=%ld\n",
+ __func__, base, clkch, fclkchreq, ret);
return ret;
}
-int cmu_clkch_set_rate(const uintptr_t base, const unsigned clkch, const uint64_t fclkchreq)
+int cmu_clkch_set_rate(const uintptr_t base, const unsigned int clkch, const uint64_t fclkchreq)
{
int ret = 0;
const struct cmu_desc *const cmu = cmu_desc_get_by_base(base);
}
if (fclkchreq == cmu_clkch_get_rate(base, clkch)) {
- INFO("%s: base=0x%08lx rate=%lu already set\n", __func__, base, fclkchreq);
+ VERBOSE("%s: base=0x%08lx rate=%lu already set\n", __func__, base, fclkchreq);
return 0;
}
ret = cmu_pll_set_rate(base, cmu->frefclk, fclkchreq);
}
- INFO("%s: base=0x%08lx ch=%u rate=%lu\n", __func__, base, clkch, fclkchreq);
+ VERBOSE("%s: base=0x%08lx ch=%u rate=%lu\n", __func__, base, clkch, fclkchreq);
return ret;
}
clkfhi = mmio_read_32(base + CMU_PLL_CTL2) & CMU_PLL_CTL2_CLKFHI_MASK;
plldivs->intnf = ((clkfhi << CLKFHI_SHIFT) + (clkflo << CLKFLO_SHIFT)) >> NF_INT_SHIFT;
- INFO("%s: base=0x%08lx nr=%u od=%u nf=%u\n",
+ VERBOSE("%s: base=0x%08lx nr=%u od=%u nf=%u\n",
__func__, base, plldivs->nr, plldivs->od, plldivs->intnf);
}
struct plldivs *const plldivs)
{
if (!frefclk || !fpllreq || !plldivs) {
- return -ENXIO;;
+ return -ENXIO;
}
uint64_t fout = 0;
plldivs->nr = nr2;
plldivs->od = od2;
plldivs->intnf = intnf2;
- INFO("%s: nr=%u od=%u nf=%u err=%d rate=%lu\n",
+ VERBOSE("%s: nr=%u od=%u nf=%u err=%d rate=%lu\n",
__func__, nr2, od2, intnf2, err2, fout);
return 0;
} else {
return 0;
}
-static int cmu_clkch_div_get(const struct cmu_desc *const cmu, const unsigned clkch)
+static int cmu_clkch_div_get(const struct cmu_desc *const cmu, const unsigned int clkch)
{
uintptr_t clkch_reg;
uint32_t div;
return -ENXIO;
}
- INFO("%s: base=0x%08lx ch=%u rate=%lu div=%u\n",
+ VERBOSE("%s: base=0x%08lx ch=%u rate=%lu div=%u\n",
__func__, cmu->base, clkch, fpll / div, div);
return div;
}
static int cmu_clkch_div_calc(const struct cmu_desc *const cmu,
- const unsigned clkch,
+ const unsigned int clkch,
uint64_t fclkchreq)
{
uintptr_t clkch_reg;
div *= CMU_MSHC_DIV;
}
- INFO("%s: base=0x%08lx ch=%u rate=%lu div=%d\n",
+ VERBOSE("%s: base=0x%08lx ch=%u rate=%lu div=%d\n",
__func__, cmu->base, clkch, fclkchreq, div);
return div;
}
-static int cmu_clkch_div_set(const struct cmu_desc *const cmu, const unsigned clkch, uint32_t div)
+static int cmu_clkch_div_set(const struct cmu_desc *const cmu, const unsigned int clkch, uint32_t div)
{
uintptr_t clkch_reg;
uint64_t timeout;
for (timeout = timeout_init_us(100000); !timeout_elapsed(timeout);) {
if (mmio_read_32(clkch_reg) & CMU_CLKCH_CTL_LOCK_CLKDIV) {
- INFO("%s: base=0x%08lx ch=%u div=%u\n", __func__, cmu->base, clkch, div);
+ VERBOSE("%s: base=0x%08lx ch=%u div=%u\n", __func__, cmu->base, clkch, div);
return 0;
}
}
uint32_t od = pllinit->clkod + 1;
uint32_t nr = pllinit->clkr + 1;
- INFO("%s: base=0x%08lx nr=%u od=%u nf=%lu\n", __func__, base, nr, od, nf >> NF_INT_SHIFT);
+ VERBOSE("%s: base=0x%08lx nr=%u od=%u nf=%lu\n", __func__, base, nr, od, nf >> NF_INT_SHIFT);
cmu_pll_set_nr(base, nr);
cmu_pll_set_od(base, od);
cmu_pll_set_nf(base, nf);
-
- mmio_clrsetbits_32(base + CMU_PLL_CTL4,
- CMU_PLL_CTL4_IIGAIN_LGMLT_MASK |
- CMU_PLL_CTL4_IPGAIN_LGMLT_MASK |
- CMU_PLL_CTL4_IGAIN_LGMLT_MASK |
- CMU_PLL_CTL4_PGAIN_LGMLT_MASK,
- CMU_PLL_CTL4_IIGAIN_LGMLT_SET(pllinit->iigain) |
- CMU_PLL_CTL4_IPGAIN_LGMLT_SET(pllinit->ipgain) |
- CMU_PLL_CTL4_IGAIN_LGMLT_SET(pllinit->igain) |
- CMU_PLL_CTL4_PGAIN_LGMLT_SET(pllinit->pgain));
+ cmu_pll_set_gains(base,
+ pllinit->pgain,
+ pllinit->igain,
+ pllinit->ipgain,
+ pllinit->iigain);
}
static int cmu_set_core_rate(const struct cmu_desc *const cmu,
if (!frefclk) {
frefclk = cmu->frefclk;
}
-
- /*
+#if 0
if (!cmu_pll_is_enabled(cmu->base)) {
return cmu_pll_div_set(cmu, frefclk, fpllreq);
}
- */
- /*
mmio_clrbits_32(cmu->base + CMU_PLL_CTL6, CMU_PLL_CTL6_SWEN);
mmio_setbits_32(cmu->base + CMU_PLL_CTL0, CMU_PLL_CTL0_CTL_EN);
mmio_clrbits_32(cmu->base + CMU_PLL_CTL0, CMU_PLL_CTL0_BYPASS);
- */
-
+#endif
err = cmu_pll_div_set(cmu, frefclk, fpllreq);
if (err) {
return err;
}
mmio_setbits_32(cmu->base + CMU_PLL_CTL0, CMU_PLL_CTL0_RST);
- /*
+#if 0
err = cmu_pll_lock_debounce(cmu->base);
if (err) {
return err;
}
- */
- /*
mmio_setbits_32(cmu->base + CMU_PLL_CTL6, CMU_PLL_CTL6_SWEN);
mmio_clrbits_32(cmu->base + CMU_PLL_CTL6, CMU_PLL_CTL6_SWRST);
- */
-
+#endif
return 0;
}
-static struct cmu_desc *const cmu_desc_get_by_base(const uintptr_t base)
+static struct cmu_desc *cmu_desc_get_by_base(const uintptr_t base)
{
int idx;
}
}
- INFO("%s: base=0x%08lx fail\n", __func__, base);
+ VERBOSE("%s: base=0x%08lx fail\n", __func__, base);
return NULL;
}
-static uintptr_t cmu_clkch_get_reg(const uintptr_t base, const unsigned clkch)
+static uintptr_t cmu_clkch_get_reg(const uintptr_t base, const unsigned int clkch)
{
return base + CMU_CLKCH0_CTL + clkch * 0x10;
}
return -ETIMEDOUT;
}
-struct cmu_desc *const cmu_desc_get_by_idx(const unsigned idx)
+struct cmu_desc *cmu_desc_get_by_idx(const unsigned int idx)
{
- static struct cmu_desc cmus[20];
+ static struct cmu_desc cmus[60];
+
if (idx >= ARRAY_SIZE(cmus)) {
return NULL;
}
}
/* TODO: rework, it is silimar to {cmu_clkch_div_set() + cmu_clkch_enable()} */
-void cmu_clkch_enable_by_base(const uintptr_t base, const unsigned div)
+void cmu_clkch_enable_by_base(const uintptr_t base, const unsigned int div)
{
uint64_t timeout;
+#ifdef BAIKAL_QEMU
+ if (base == MMCA57_0_PVT_CLKCHCTL ||
+ base == MMCA57_1_PVT_CLKCHCTL ||
+ base == MMCA57_2_PVT_CLKCHCTL ||
+ base == MMCA57_3_PVT_CLKCHCTL) {
+ return;
+ }
+#endif
mmio_clrbits_32(base, CMU_CLKCH_CTL_CLK_EN);
mmio_clrsetbits_32(base,
CMU_CLKCH_CTL_VAL_CLKDIV_MASK,
}
}
- INFO("%s: base=0x%08lx enable\n", __func__, base);
+ VERBOSE("%s: base=0x%08lx enable\n", __func__, base);
mmio_clrbits_32(base, CMU_CLKCH_CTL_SWRST);
}
int err;
if (base == MMAVLSP_CMU0_BASE) {
- INFO("%s: base=0x%08lx skip\n", __func__, base);
+ VERBOSE("%s: base=0x%08lx skip\n", __func__, base);
return;
}
return;
}
- INFO("%s: base=0x%08lx enable\n", __func__, base);
+ VERBOSE("%s: base=0x%08lx enable\n", __func__, base);
mmio_setbits_32(base + CMU_PLL_CTL6, CMU_PLL_CTL6_SWEN);
mmio_clrbits_32(base + CMU_PLL_CTL6, CMU_PLL_CTL6_SWRST);
}
-static void cmu_pll_set_od(const uintptr_t base, const uint32_t od)
-{
- assert(od >= OD_MIN);
- assert(od <= OD_MAX);
-
- mmio_clrsetbits_32(base +
- CMU_PLL_CTL0,
- CMU_PLL_CTL0_CLKOD_MASK,
- CMU_PLL_CTL0_CLKOD_SET(od - 1));
-}
-
-static void cmu_pll_set_nr(const uintptr_t base, const uint32_t nr)
+void cmu_pll_set_gains(const uintptr_t base,
+ const int8_t pgain,
+ const int8_t igain,
+ const int8_t ipgain,
+ const int8_t iigain)
{
- assert(nr >= NR_MIN);
- assert(nr <= NR_MAX);
+ assert(pgain >= -32 && pgain <= 31);
+ assert(igain >= -32 && igain <= 31);
+ assert(ipgain >= -32 && ipgain <= 31);
+ assert(iigain >= -32 && iigain <= 31);
- mmio_clrsetbits_32(base +
- CMU_PLL_CTL0,
- CMU_PLL_CTL0_CLKR_MASK,
- CMU_PLL_CTL0_CLKR_SET(nr - 1));
+ mmio_clrsetbits_32(base + CMU_PLL_CTL4,
+ CMU_PLL_CTL4_PGAIN_LGMLT_MASK |
+ CMU_PLL_CTL4_IGAIN_LGMLT_MASK |
+ CMU_PLL_CTL4_IPGAIN_LGMLT_MASK |
+ CMU_PLL_CTL4_IIGAIN_LGMLT_MASK,
+ CMU_PLL_CTL4_PGAIN_LGMLT_SET(pgain) |
+ CMU_PLL_CTL4_IGAIN_LGMLT_SET(igain) |
+ CMU_PLL_CTL4_IPGAIN_LGMLT_SET(ipgain) |
+ CMU_PLL_CTL4_IIGAIN_LGMLT_SET(iigain));
}
static void cmu_pll_set_nf(const uintptr_t base, const uint64_t nf)
mmio_write_32(base + CMU_PLL_CTL3, ctl3);
}
}
+
+static void cmu_pll_set_nr(const uintptr_t base, const uint32_t nr)
+{
+ assert(nr >= NR_MIN);
+ assert(nr <= NR_MAX);
+
+ mmio_clrsetbits_32(base +
+ CMU_PLL_CTL0,
+ CMU_PLL_CTL0_CLKR_MASK,
+ CMU_PLL_CTL0_CLKR_SET(nr - 1));
+}
+
+static void cmu_pll_set_od(const uintptr_t base, const uint32_t od)
+{
+ assert(od >= OD_MIN);
+ assert(od <= OD_MAX);
+
+ mmio_clrsetbits_32(base +
+ CMU_PLL_CTL0,
+ CMU_PLL_CTL0_CLKOD_MASK,
+ CMU_PLL_CTL0_CLKOD_SET(od - 1));
+}
#include <stdbool.h>
#include <stdint.h>
-struct cmu_desc {
+struct __attribute__((__packed__)) cmu_desc {
uintptr_t base;
- const char *name;
uint64_t frefclk;
- uint64_t fpllmin;
- uint64_t fpllmax;
- uint64_t fpllreq;
bool deny_pll_reconf;
};
-typedef struct cmu_pll_ctl_vals {
+typedef struct __attribute__((__packed__)) {
uint16_t clkod;
uint16_t clkr;
uint64_t clkf;
- uint8_t pgain;
- uint8_t igain;
- uint8_t ipgain;
- uint8_t iigain;
+ int8_t pgain;
+ int8_t igain;
+ int8_t ipgain;
+ int8_t iigain;
} cmu_pll_ctl_vals_t;
-struct cmu_desc *const cmu_desc_get_by_idx(const unsigned idx);
+struct cmu_desc *cmu_desc_get_by_idx(const unsigned int idx);
/* PLL functions */
int64_t cmu_pll_get_rate (const uintptr_t base, uint64_t frefclk);
int cmu_pll_is_enabled(const uintptr_t base);
void cmu_pll_on (const uintptr_t base, const cmu_pll_ctl_vals_t *const pllinit);
int64_t cmu_pll_round_rate(const uintptr_t base, uint64_t frefclk, const uint64_t fpllreq);
+void cmu_pll_set_gains (const uintptr_t base,
+ const int8_t pgain,
+ const int8_t igain,
+ const int8_t ipgain,
+ const int8_t iigain);
/* Clock channel functions */
-int64_t cmu_clkch_get_rate (const uintptr_t base, const unsigned clkch);
-int cmu_clkch_set_rate (const uintptr_t base, const unsigned clkch, const uint64_t fclkchreq);
-int cmu_clkch_disable (const uintptr_t base, const unsigned clkch);
-int cmu_clkch_enable (const uintptr_t base, const unsigned clkch);
-void cmu_clkch_enable_by_base(const uintptr_t base, const unsigned div);
-int cmu_clkch_is_enabled (const uintptr_t base, const unsigned clkch);
-int64_t cmu_clkch_round_rate (const uintptr_t base, const unsigned clkch, const uint64_t fclkchreq);
+int64_t cmu_clkch_get_rate (const uintptr_t base, const unsigned int clkch);
+int cmu_clkch_set_rate (const uintptr_t base, const unsigned int clkch, const uint64_t fclkchreq);
+int cmu_clkch_disable (const uintptr_t base, const unsigned int clkch);
+int cmu_clkch_enable (const uintptr_t base, const unsigned int clkch);
+void cmu_clkch_enable_by_base(const uintptr_t base, const unsigned int div);
+int cmu_clkch_is_enabled (const uintptr_t base, const unsigned int clkch);
+int64_t cmu_clkch_round_rate (const uintptr_t base, const unsigned int clkch, const uint64_t fclkchreq);
#endif /* BM1000_CMU_H */
--- /dev/null
+/*
+ * Copyright (c) 2023, Baikal Electronics, JSC. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <baikal_scp.h>
+#include <bm1000_efuse.h>
+
+int64_t efuse_get_lot(void)
+{
+ int err;
+
+ err = scp_cmd('I', 0, 0);
+ if (err) {
+ return err;
+ }
+
+ return *(uint64_t *)scp_buf();
+}
+
+int32_t efuse_get_mac(void)
+{
+ int err;
+
+ err = scp_cmd('M', 0, 0);
+ if (err) {
+ return err;
+ }
+
+ return *(uint32_t *)scp_buf();
+}
+
+int32_t efuse_get_serial(void)
+{
+ int err;
+
+ err = scp_cmd('N', 0, 0);
+ if (err) {
+ return err;
+ }
+
+ return *(uint32_t *)scp_buf();
+}
--- /dev/null
+/*
+ * Copyright (c) 2023, Baikal Electronics, JSC. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BM1000_EFUSE_H
+#define BM1000_EFUSE_H
+
+#include <stdint.h>
+
+int64_t efuse_get_lot(void);
+int32_t efuse_get_mac(void);
+int32_t efuse_get_serial(void);
+
+#endif /* BM1000_EFUSE_H */
scp->offset = arg0 + BAIKAL_SCP_MAX_SIZE;
scp->size = (uint16_t)arg1;
break;
+ case 'I':
+ case 'M':
+ case 'N':
case 'T':
case 't':
scp->op = op;
#define SCP_FLASH_MAX_CHUNK_SIZE UL(1024)
-void scp_flash_init(void)
+int scp_flash_init(void)
{
- scp_cmd('T', 0, 0); /* disable trace */
+ return scp_cmd('T', 0, 0); /* disable trace */
}
int scp_flash_erase(uint32_t addr, size_t size)
#include <stddef.h>
#include <stdint.h>
-void scp_flash_init(void);
-int scp_flash_erase(uint32_t addr, size_t size);
-int scp_flash_read( uint32_t addr, void *buf, size_t size);
-int scp_flash_write(uint32_t addr, void *data, size_t size);
+int scp_flash_init(void);
+int scp_flash_erase(uint32_t addr, size_t size);
+int scp_flash_read(uint32_t addr, void *buf, size_t size);
+int scp_flash_write(uint32_t addr, void *data, size_t size);
#endif /* BM1000_SCP_FLASH_H */
/*
- * Copyright (c) 2020-2021, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2020-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define FIFO_SIZE U(16)
-#define SCL_CLK_DIV 499
-CASSERT(SCL_CLK_DIV < 1024, assert_smbus_scl_clk_div);
-
-unsigned smbus_txrx(const uintptr_t base,
- const unsigned targetaddr,
- const void *const txbuf,
- const unsigned txbufsize,
- void *const rxbuf,
- const unsigned rxbufsize)
+unsigned int smbus_txrx(const uintptr_t base,
+ const unsigned int iclk,
+ const enum smbus_sht sht,
+ const unsigned int sclclk,
+ const unsigned int targetaddr,
+ const void *const txbuf,
+ const unsigned int txbufsize,
+ void *const rxbuf,
+ const unsigned int rxbufsize)
{
volatile struct smbus_regs *const smbusregs = (volatile struct smbus_regs *const)base;
- unsigned rxedsize = 0;
+ const unsigned int sclclkdiv = iclk / sclclk - 1;
+ unsigned int rxedsize = 0;
uint8_t *const rxptr = (uint8_t *)rxbuf;
const uint8_t *const txptr = (uint8_t *)txbuf;
assert(smbusregs != NULL);
+ assert(sclclk >= 10000);
+ assert((sht == SMBUS_SHT_100KHZ && sclclk <= 100000) ||
+ (sht == SMBUS_SHT_400KHZ && sclclk <= 400000));
+ assert(sclclkdiv <= 1023);
assert(targetaddr <= 0x7f);
assert(txbuf != NULL || !txbufsize);
assert(rxbuf != NULL || !rxbufsize);
smbusregs->cr1 = CR1_IRT;
smbusregs->cr1 = 0;
smbusregs->cr2 = 0;
- smbusregs->scd1 = SCL_CLK_DIV & 0xff;
- smbusregs->scd2 = SCD2_SHT | (SCL_CLK_DIV >> 8);
+ smbusregs->scd1 = (sclclkdiv & 0xff);
+ smbusregs->scd2 = (sclclkdiv >> 8) | (sht == SMBUS_SHT_100KHZ ? SCD2_SHT : 0);
smbusregs->adr1 = targetaddr;
smbusregs->imr1 = 0;
smbusregs->imr2 = 0;
smbusregs->cr1 = CR1_IEB;
if (txbufsize > 0) {
- unsigned txedsize;
+ unsigned int txedsize;
smbusregs->cr1 |= CR1_TRS;
for (txedsize = 0; txedsize < txbufsize;) {
- unsigned bytecount;
+ unsigned int bytecount;
bool holdbus = false;
bytecount = txbufsize - txedsize;
while (!(smbusregs->isr1 &
(ISR1_TCS | ISR1_ALD | ISR1_RNK)) &&
- !(smbusregs->isr2 & ISR2_MSH));
+ !(smbusregs->isr2 & ISR2_MSH))
+ ;
if (smbusregs->isr1 & (ISR1_ALD | ISR1_RNK)) {
goto exit;
}
for (rxedsize = 0; rxedsize < rxbufsize;) {
- unsigned bytecount = MIN(rxbufsize - rxedsize, FIFO_SIZE);
+ unsigned int bytecount = MIN(rxbufsize - rxedsize, FIFO_SIZE);
smbusregs->isr1 = ISR1_TCS | ISR1_FFE |
ISR1_ALD | ISR1_RNK |
smbusregs->cr2 = CR2_FTE;
while ((smbusregs->cr2 & CR2_FTE) &&
- !(smbusregs->isr1 & (ISR1_TCS | ISR1_ALD | ISR1_RNK)));
+ !(smbusregs->isr1 & (ISR1_TCS | ISR1_ALD | ISR1_RNK)))
+ ;
if (smbusregs->isr1 & (ISR1_ALD | ISR1_RNK)) {
goto exit;
/*
- * Copyright (c) 2020-2021, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2020-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BM1000_SMBUS_H
#define BM1000_SMBUS_H
-unsigned smbus_txrx(const uintptr_t base,
- const unsigned targetaddr,
- const void *const txbuf,
- const unsigned txbufsize,
- void *const rxbuf,
- const unsigned rxbufsize);
+enum smbus_sht {
+ SMBUS_SHT_400KHZ = 0,
+ SMBUS_SHT_100KHZ = 1
+};
+
+unsigned int smbus_txrx(const uintptr_t base,
+ const unsigned int iclk,
+ const enum smbus_sht sht,
+ const unsigned int sclclk,
+ const unsigned int targetaddr,
+ const void *const txbuf,
+ const unsigned int txbufsize,
+ void *const rxbuf,
+ const unsigned int rxbufsize);
#endif /* BM1000_SMBUS_H */
/*
- * Copyright (c) 2014-2021, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2014-2023, Baikal Electronics, JSC. All rights reserved.
*
* Author: Alexey Malahov <Alexey.Malahov@baikalelectronics.com>
*
#include <stdint.h>
+#include <bm1000_def.h>
+
#define DDRC_MSTR 0x0 /* Master Register */
#define DDRC_STAT 0x4 /* Operating Mode Status Register */
#define DDRC_MRCTRL0 0x10 /* Mode Register Read/Write Control Register 0 */
#define DDR_SINGLE_MODE 0
#define DDR_DUAL_MODE 1
-#define DDR_CTRL_BASE_PORT0 UL(0x0e200000)
-#define DDR_CTRL_BASE_PORT1 UL(0x22200000)
-#define DDR_CTRL_BASE_OFF (DDR_CTRL_BASE_PORT1 - DDR_CTRL_BASE_PORT0)
-
-#define DDR_PHY_BASE_PORT0 UL(0x0e210000)
-#define DDR_PHY_BASE_PORT1 UL(0x22210000)
-#define DDR_PHY_BASE_OFF (DDR_PHY_BASE_PORT1 - DDR_PHY_BASE_PORT0)
-
-#define DDR_CTRL(p) (DDR_CTRL_BASE_PORT0 + (p) * DDR_CTRL_BASE_OFF)
-#define DDR_PHY(p) (DDR_PHY_BASE_PORT0 + (p) * DDR_PHY_BASE_OFF)
-
-#define _READ_MEMORY_REG(r) (*((volatile uint32_t*) (r)))
-#define _WRITE_MEMORY_REG(r, v) (*((volatile uint32_t*) (r)) = v)
-
-/* Macros to read/write DDR Memory Controller (uMCTL2) registers */
-#define BM_DDRC_WRITE(p, r, v) _WRITE_MEMORY_REG(DDR_CTRL(p) + (r), v)
-#define BM_DDRC_READ(p, r) _READ_MEMORY_REG(DDR_CTRL(p) + (r))
+#define DDR_CTRL_BASE_OFF (MMDDR1_CTRL_BASE - MMDDR0_CTRL_BASE)
+#define DDR_PHY_BASE_OFF (MMDDR1_PHY_BASE - MMDDR0_PHY_BASE)
-/* Macros to read/write DDR4 multiPHY Utility Block (PUB) registers */
-#define BM_DDR_PUB_WRITE(p, r, v) _WRITE_MEMORY_REG(DDR_PHY(p) + (r), v)
-#define BM_DDR_PUB_READ(p, r) _READ_MEMORY_REG(DDR_PHY(p) + (r))
+#define DDR_CTRL(p) (MMDDR0_CTRL_BASE + ((unsigned long)p) * DDR_CTRL_BASE_OFF)
+#define DDR_PHY(p) (MMDDR0_PHY_BASE + ((unsigned long)p) * DDR_PHY_BASE_OFF)
/* DCU Command Cache line fields */
#define DCU_DFIELD_DATA 0 /* field width: 5 */
/*
- * Copyright (c) 2021, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2021-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
#include <ndelay.h>
+#include <baikal_def.h>
#include "ddr_baikal.h"
#include "ddr_lcru.h"
#include "ddr_master.h"
-static void baikal_ddrc_set_registers(const unsigned port, struct ctl_content *ddrc)
+/* Macros to read/write DDR Memory Controller (uMCTL2) registers */
+#define BM_DDRC_READ(p, r) mmio_read_32(DDR_CTRL(p) + (r))
+#define BM_DDRC_WRITE(p, r, v) mmio_write_32(DDR_CTRL(p) + (r), v)
+
+/* Macros to read/write DDR4 multiPHY Utility Block (PUB) registers */
+#define BM_DDR_PUB_READ(p, r) mmio_read_32(DDR_PHY(p) + (r))
+#define BM_DDR_PUB_WRITE(p, r, v) mmio_write_32(DDR_PHY(p) + (r), v)
+
+static void baikal_ddrc_set_registers(const unsigned int port, struct ctl_content *ddrc)
{
BM_DDRC_WRITE(port, DDRC_MSTR, ddrc->MSTR_);
BM_DDRC_WRITE(port, DDRC_DFIUPD2, ddrc->DFIUPD2_);
}
-static void baikal_ddrphy_set_registers(const unsigned port, struct phy_content *phy)
+static void baikal_ddrphy_set_registers(const unsigned int port, struct phy_content *phy)
{
BM_DDR_PUB_WRITE(port, DDR_PUB_DCR, phy->DCR_);
if (phy->dbus_half) {
uint32_t DXnGCR0_val = BM_DDR_PUB_READ(port, DDR_PUB_DX4GCR0);
+
DXnGCR0_val &= ~(0x1U);
BM_DDR_PUB_WRITE(port, DDR_PUB_DX4GCR0, DXnGCR0_val);
BM_DDR_PUB_WRITE(port, DDR_PUB_DX5GCR0, DXnGCR0_val);
uint64_t timeout;
uint32_t tMRD = BM_DDR_PUB_READ(port, DDR_PUB_DTPR1) & 0x1f;
uint64_t cmu_cmd = 0; /* supposed content of cache */
- cmu_cmd |= ((uint64_t)tMRD << DCU_DFIELD_DTP) |\
- (1ULL << DCU_DFIELD_TAG) |\
- (1ULL << DCU_DFIELD_CMD) |\
- (mr_num << DCU_DFIELD_BANK) |\
+
+ cmu_cmd |= ((uint64_t)tMRD << DCU_DFIELD_DTP) |
+ (1ULL << DCU_DFIELD_TAG) |
+ (1ULL << DCU_DFIELD_CMD) |
+ (mr_num << DCU_DFIELD_BANK) |
(mr_value << DCU_DFIELD_ADDR);
/* initiate write to cache by writing to DCUAR & DCUDR: */
for (timeout = timeout_init_us(10000);;) {
const uint32_t reg = BM_DDR_PUB_READ(port, DDR_PUB_DCUSR0);
+
if (reg & 0x1) {
break;
} else if (timeout_elapsed(timeout)) {
}
#endif
-static int baikal_ddrphy_pir_training(const unsigned port, uint32_t mode)
+static int baikal_ddrphy_pir_training(const unsigned int port, uint32_t mode)
{
int ret = 0;
uint64_t timeout;
for (timeout = timeout_init_us(10000);;) {
const uint32_t reg = BM_DDR_PUB_READ(port, DDR_PUB_PGSR0);
+
if (reg & 0x1) {
break;
} else if (timeout_elapsed(timeout)) {
return ret;
}
-static int baikal_ddrphy_vref_training(const unsigned port, unsigned clock_mhz)
+static int baikal_ddrphy_vref_training(const unsigned int port, unsigned int clock_mhz)
{
uint32_t vtcr0_val = BM_DDR_PUB_READ(port, DDR_PUB_VTCR0);
+
vtcr0_val &= ~GENMASK(31, 29);
vtcr0_val |= GENMASK(31, 29) & ((3 * clock_mhz / 640) << 29); /* Number of ctl_clk supposed to be (> 150ns) during DRAM VREF training */
vtcr0_val &= ~GENMASK(5, 0);
vtcr0_val |= 0x8; /* DRAM Vref initial value (this one is for DDR0 channel speedbin DDR4-2133) */
#ifdef BAIKAL_DUAL_CHANNEL_MODE
uint32_t dram_vref_val = BM_DDR_PUB_READ(port, DDR_PUB_MR6) & 0x3f;
+
if (dram_vref_val) {
vtcr0_val |= dram_vref_val;
}
/* D4MV I/Os with PVREF_DAC settings (PUB DataBook p.353) */
uint32_t vtcr1_val = BM_DDR_PUB_READ(port, DDR_PUB_VTCR1);
+
vtcr1_val &= ~GENMASK(7, 5);
vtcr1_val |= GENMASK(7, 5) & ((clock_mhz / 160) << 5); /* Number of ctl_clk supposed to be (> 200ns) during Host IO VREF training */
vtcr1_val &= ~(0x1U << 8);
/* 4.4.8.6 Steps to Run VREF Training (PUB DataBook p.363) */
const uint32_t dtcr0_stored = BM_DDR_PUB_READ(port, DDR_PUB_DTCR0);
uint32_t dtcr0_val = dtcr0_stored;
+
dtcr0_val &= ~GENMASK(31, 28); /* Disable refresh during training */
BM_DDR_PUB_WRITE(port, DDR_PUB_DTCR0, dtcr0_val);
return ret;
}
-static int baikal_ddrphy_dram_init(const unsigned port, unsigned clock_mhz)
+static int baikal_ddrphy_dram_init(const unsigned int port, unsigned int clock_mhz)
{
int ret = 0;
uint64_t timeout;
} else {
ret = baikal_ddrphy_pir_training(port, DDR_PUB_PIR_DRAM_STEP0);
}
+
if (ret) {
return ret;
}
#ifdef BAIKAL_DUAL_CHANNEL_MODE
uint32_t dram_vref_val = BM_DDR_PUB_READ(port, DDR_PUB_MR6) & 0x3f;
+
if (dram_vref_val) {
run_dram_vref_tarining(port);
}
* During DDR4 write leveling training rtt_wr in MR2 register must be zeroed.
*/
const uint16_t mr2_val = BM_DDR_PUB_READ(port, DDR_PUB_MR2);
+
if (mr2_val & GENMASK(11, 9)) {
dcu_load_mode_command(port, 2, mr2_val & ~GENMASK(11, 9));
}
/* Enable DFI update request */
uint32_t dsgcr_val = BM_DDR_PUB_READ(port, DDR_PUB_DSGCR);
+
dsgcr_val |= DDR_PUB_DSGCR_PUREN;
BM_DDR_PUB_WRITE(port, DDR_PUB_DSGCR, dsgcr_val);
for (timeout = timeout_init_us(10000);;) {
const uint32_t reg = BM_DDRC_READ(port, DDRC_STAT);
+
if ((reg & 0x3) == 0x1) {
break;
} else if (timeout_elapsed(timeout)) {
if (!info->ecc_on) {
/* disable unused 9-th data byte */
uint32_t tmp = BM_DDR_PUB_READ(port, DDR_PUB_DX8GCR0);
+
tmp &= ~(1 << 0);
BM_DDR_PUB_WRITE(port, DDR_PUB_DX8GCR0, tmp);
}
if (ret) {
return ret;
}
-
#ifdef BAIKAL_DUAL_CHANNEL_MODE
/* set internal Vref values */
if (info->PHY_HOST_VREF) {
- uint32_t DXnGCR5_val = (info->PHY_HOST_VREF << 24) \
- | (info->PHY_HOST_VREF << 16) \
- | (info->PHY_HOST_VREF << 8) \
+ uint32_t DXnGCR5_val = (info->PHY_HOST_VREF << 24)
+ | (info->PHY_HOST_VREF << 16)
+ | (info->PHY_HOST_VREF << 8)
| (info->PHY_HOST_VREF);
for (int i = 0; i <= 8; i++) {
/* all registers lie at constant offsets from one another: */
- BM_DDR_PUB_WRITE(port, DDR_PUB_DX0GCR5 + \
+ BM_DDR_PUB_WRITE(port, DDR_PUB_DX0GCR5 +
(DDR_PUB_DX1GCR5 - DDR_PUB_DX0GCR5) * i,
DXnGCR5_val);
}
#define LCRU_DDR(port) (MMDDR0_BASE + (port) * (MMDDR1_BASE - MMDDR0_BASE))
-static const cmu_pll_ctl_vals_t pll_ddr_1600 = {4, 0, 0xa000000000, 0, 0x2c, 0, 0x2c};
-static const cmu_pll_ctl_vals_t pll_ddr_1866 = {2, 0, 0x7000000000, 0, 0x2c, 0, 0x2c};
-static const cmu_pll_ctl_vals_t pll_ddr_2133 = {2, 0, 0x8000000000, 0, 0x2c, 0, 0x2c};
-static const cmu_pll_ctl_vals_t pll_ddr_2400 = {2, 0, 0x9000000000, 0, 0x2c, 0, 0x2c};
-static const cmu_pll_ctl_vals_t pll_ddr_2666 = {2, 0, 0xa000000000, 0, 0x2c, 0, 0x2c};
+static const cmu_pll_ctl_vals_t pll_ddr_1600 = {4, 0, 0xa000000000, 0, -20, 0, -20};
+static const cmu_pll_ctl_vals_t pll_ddr_1866 = {2, 0, 0x7000000000, 0, -20, 0, -20};
+static const cmu_pll_ctl_vals_t pll_ddr_2133 = {2, 0, 0x8000000000, 0, -20, 0, -20};
+static const cmu_pll_ctl_vals_t pll_ddr_2400 = {2, 0, 0x9000000000, 0, -20, 0, -20};
+static const cmu_pll_ctl_vals_t pll_ddr_2666 = {2, 0, 0xa000000000, 0, -20, 0, -20};
void ddr_lcru_clkch_rst(int port, uint32_t ra, int set)
{
- uint32_t reg = mmio_read_32(LCRU_DDR(port) + ra);
-
if (set) {
- reg |= LCRU_CMU_SWRST; /* set reset */
+ mmio_setbits_32(LCRU_DDR(port) + ra, LCRU_CMU_SWRST);
} else {
- reg &= ~LCRU_CMU_SWRST; /* clear reset */
+ mmio_clrbits_32(LCRU_DDR(port) + ra, LCRU_CMU_SWRST);
}
-
- mmio_write_32(LCRU_DDR(port) + ra, reg);
}
void ddr_lcru_dual_mode(int port, int mode)
/*
- * Copyright (c) 2021, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2021-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define TZC_RATTRIBUTE_OFS 0x110
#define TZC_REIDACCESS_OFS 0x114
-int ddr_odt_configuration(const unsigned port, const uint16_t crc_val, struct ddr_configuration *const data);
+int ddr_odt_configuration(const unsigned int port, const uint16_t crc_val, struct ddr_configuration *const data);
-static void tzc_set_transparent(const unsigned conf)
+static void tzc_set_transparent(const unsigned int conf)
{
if (conf & 0x1) {
mmio_write_32(MMTZC0_TZC400_BASE + TZC_GATEKEEPER_OFS, 0xf);
} else {
data.single_ddr = 1;
}
-
#if !ECC_ENABLE
data.ecc_on = false;
#endif
-
#if DBUS_HALF
data.dbus_half = true;
#endif
-
if (ddr_odt_configuration(port, spd_crc, &data)) {
goto error;
}
if (ddr_lcru_initport(port, data.clock_mhz)) {
goto failed;
}
+
if (ddr_init(port, dual_mode, &data)) {
goto failed;
}
int dram_init(void)
{
int ret = 0;
- unsigned conf = 0;
+ unsigned int conf = 0;
extern struct spd_container spd_content;
+#ifdef BAIKAL_QEMU
+ return 0;
+#endif
if (ddr_read_spd(0) != NULL) {
if (spd_content.content[0].mem_type == SPD_MEMTYPE_DDR4) {
INFO("DIMM0: DDR4 SDRAM is detected\n");
}
if (conf & 0x1) {
- ret = ddr_port_init(0, &spd_content, (conf & 0x2));
+ ret = ddr_port_init(0, &spd_content, conf & 0x2);
} else {
ddr_lcru_disable(0);
}
}
if (conf & 0x2) {
- ret = ddr_port_init(1, &spd_content, (conf & 0x1));
+ ret = ddr_port_init(1, &spd_content, conf & 0x1);
}
if (ret) {
/*
- * Copyright (c) 2021, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2021-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdbool.h>
#include <stdint.h>
+#include <baikal_def.h>
+
enum ddr_speed_bin {DDR4_1600, DDR4_1866, DDR4_2133, DDR4_2400, DDR4_2666};
struct ddr_configuration {
uint32_t tRAS; /* ACT to PRE command period */
uint32_t tRC; /* ACT to ACT or REF command period */
uint32_t tRCD; /* ACT to internal read or write delay time */
- uint32_t tWTR_S; /* Write to Read time for different bank
- group */
+ uint32_t tWTR_S; /* Write to Read time for different bank group */
uint32_t tWTR_L; /* Write to Read time for same bank group */
- uint32_t tRRD_S; /* ACTIVATE to ACTIVATE Command delay to
- different bank group */
- uint32_t tRRD_L; /* ACTIVATE to ACTIVATE Command delay to
- same bank group */
+ uint32_t tRRD_S; /* ACTIVATE to ACTIVATE Command delay to different bank group */
+ uint32_t tRRD_L; /* ACTIVATE to ACTIVATE Command delay to same bank group */
uint32_t tFAW; /* Four Activate Window delay time */
uint32_t tRFC1; /* Refresh Cycle time in 1x mode */
uint32_t tRFC4; /* Refresh Cycle time in 4x mode */
uint32_t tREFI; /* Periodic Refresh Interval */
uint32_t tRTP; /* Read to Precharge for autoprecharge */
- uint32_t tWR_CRC_DM; /* Write Recovery time when CRC and DM
- are enabled */
- uint32_t tWTR_S_CRC_DM; /* Write to Read time for different bank group
- with both CRC and DM enabled */
- uint32_t tWTR_L_CRC_DM; /* Write to Read time for same bank group
- with both CRC and DM enabled */
+ uint32_t tWR_CRC_DM; /* Write Recovery time when CRC and DM are enabled */
+ uint32_t tWTR_S_CRC_DM; /* Write to Read time for different bank group with both CRC and DM enabled */
+ uint32_t tWTR_L_CRC_DM; /* Write to Read time for same bank group with both CRC and DM enabled */
uint32_t tDLLK; /* DLL Locking time */
uint32_t tXP; /* Exit Power Down with DLL on */
uint32_t tMOD; /* Mode Register Set time */
- uint32_t tCCD_S; /* CAS_n to CAS_n command Delay for different
- bank group */
- uint32_t tCCD_L; /* CAS_n to CAS_n command Delay for same bank
- group */
- uint32_t tCKSRX; /* Valid Clock Requirement before Self Refresh
- Exit or Power-Down Exit or Reset Exit */
+ uint32_t tCCD_S; /* CAS_n to CAS_n command Delay for different bank group */
+ uint32_t tCCD_L; /* CAS_n to CAS_n command Delay for same bank group */
+ uint32_t tCKSRX; /* Valid Clock Requirement before Self Refresh Exit or Power-Down Exit or Reset Exit */
uint32_t tCKE; /* CKE minimum pulse width */
- uint32_t tMRD_PDA; /* Mode Register Set command cycle time
- in PDA mode */
+ uint32_t tMRD_PDA; /* Mode Register Set command cycle time in PDA mode */
uint32_t tRASmax; /* Maximum ACT to PRE command period */
uint32_t tMPX_S; /* CS setup time to CKE */
uint32_t tMPX_LH; /* CS_n Low hold time to CKE rising edge */
uint32_t tCPDED; /* Command pass disable delay */
- uint32_t tXS; /* Exit Self Refresh to commands not requiring
- a locked DLL */
+ uint32_t tXS; /* Exit Self Refresh to commands not requiring a locked DLL */
uint32_t tXS_FAST; /* Exit Self Refresh to ZQCL,ZQCS and MRS */
- uint32_t tXS_ABORT; /* SRX to commands not requiring a locked DLL
- in Self Refresh ABORT */
- uint32_t tXSDLL; /* Exit Self Refresh to tXSDLL commands
- requiring a locked DLL */
- uint32_t tXMP; /* Exit MPSM to commands not requiring
- a locked DLL */
- uint32_t tXMPDLL; /* Exit MPSM to commands requiring
- a locked DLL */
+ uint32_t tXS_ABORT; /* SRX to commands not requiring a locked DLL in Self Refresh ABORT */
+ uint32_t tXSDLL; /* Exit Self Refresh to tXSDLL commands requiring a locked DLL */
+ uint32_t tXMP; /* Exit MPSM to commands not requiring a locked DLL */
+ uint32_t tXMPDLL; /* Exit MPSM to commands requiring a locked DLL */
uint32_t tCKMPE; /* Valid clock requirement after MPSM entry */
uint32_t CL; /* CAS Latency */
uint32_t CWL; /* CAS Write Latency */
- uint32_t WCL; /* Write Command Latency when CRC and DM
- are both enabled */
+ uint32_t WCL; /* Write Command Latency when CRC and DM are both enabled */
uint32_t PL; /* C/A Parity Latency */
uint32_t AL; /* Additive Latency */
uint32_t RL; /* Read Latency */
uint32_t RTT_NOM; /* NOM pullup impedance */
uint32_t RTT_WR; /* WR pullup impedance */
uint32_t DIC; /* output driver impedance */
-#if defined(BAIKAL_DUAL_CHANNEL_MODE)
+#ifdef BAIKAL_DUAL_CHANNEL_MODE
uint32_t PHY_HOST_VREF;
uint32_t PHY_DRAM_VREF;
#endif
if (data->single_ddr) {
/* for single DDR Controller in SoC we have normal address regions */
- ddrc->SARBASE0_ *= 2; /* region address 2..4 GiB (UMCTL2_SARMINSIZE=256MB) */
+ ddrc->SARBASE0_ *= 2; /* region address 2..4 GiB (UMCTL2_SARMINSIZE = 256 MiB) */
ddrc->SARSIZE0_ = (ddrc->SARSIZE0_ + 1) * 2 - 1; /* region size 2 GiB */
ddrc->SARBASE1_ *= 2; /* region address 34..64 GiB */
ddrc->SARSIZE1_ = (ddrc->SARSIZE1_ + 1) * 2 - 1; /* region size 30 GiB */
ddrc->DFITMG0_ |= GENMASK(5, 0) & (data->WL - 2 + !!data->registered_dimm);
ddrc->DFITMG0_ &= ~GENMASK(28, 24);
- ddrc->DFITMG0_ |= GENMASK(28, 24) & ((2 + 2 + !!data->registered_dimm) << 24); /* see PHY DataBook, Table7-1 (p.648) + 2*DWC_PIPE_DFI2PHY */
+ ddrc->DFITMG0_ |= GENMASK(28, 24) & ((2 + 2 + !!data->registered_dimm) << 24); /* see PHY DataBook, Table7-1 (p.648) + 2 * DWC_PIPE_DFI2PHY */
#if DDR_CRC_ENABLE
ddrc->DRAMTMG0_ &= ~GENMASK(30, 24);
ddrc->DRAMTMG0_ |= GENMASK(30, 24) & (((data->WL + 4 + data->tWR_CRC_DM) / 2) << 24); /* WL + BL/2 + WR_CRC_DM (this formula is valid for CRC&DM on) */
ddrc->DRAMTMG0_ &= ~GENMASK(5, 0);
ddrc->DRAMTMG0_ |= GENMASK(5, 0) & (data->tRAS / 2);
ddrc->DRAMTMG0_ &= ~GENMASK(14, 8);
- ddrc->DRAMTMG0_ |= GENMASK(14, 8) & (((data->tRASmax / 1024 - 1) / 2) << 8); /* (tRAS(max)/1024)-1)/2 */
+ ddrc->DRAMTMG0_ |= GENMASK(14, 8) & (((data->tRASmax / 1024 - 1) / 2) << 8); /* (tRAS(max) / 1024) - 1) / 2 */
ddrc->DRAMTMG1_ &= ~GENMASK(20, 16);
ddrc->DRAMTMG1_ |= GENMASK(20, 16) & (DIV_ROUND_UP_2EVAL(data->tXP + data->PL, 2) << 16);
ddrc->DRAMTMG1_ &= ~GENMASK(13, 8);
ddrc->DRAMTMG2_ |= GENMASK(13, 8) & (DIV_ROUND_UP_2EVAL(data->RL + 4 + 1 + 1 - data->WL + rsl, 2) << 8); /* DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL */
#if DDR_CRC_ENABLE
ddrc->DRAMTMG2_ &= ~GENMASK(5, 0);
- ddrc->DRAMTMG2_ |= GENMASK(5, 0) & DIV_ROUND_UP_2EVAL(data->CWL + data->PL + 4 + data->tWTR_L_CRC_DM, 2); /* DDR4: CWL + PL + BL/2 + tWTR_L_CRC_DM(tWTR_L+5) (this formula is valid for CRC&DM on) */
+ ddrc->DRAMTMG2_ |= GENMASK(5, 0) & DIV_ROUND_UP_2EVAL(data->CWL + data->PL + 4 + data->tWTR_L_CRC_DM, 2); /* DDR4: CWL + PL + BL / 2 + tWTR_L_CRC_DM(tWTR_L + 5) (this formula is valid for CRC&DM on) */
#else
ddrc->DRAMTMG2_ &= ~GENMASK(5, 0);
ddrc->DRAMTMG2_ |= GENMASK(5, 0) & DIV_ROUND_UP_2EVAL(data->CWL + data->PL + 4 + data->tWTR_L, 2); /* DDR4: CWL + PL + BL/2 + tWTR_L */
#endif
ddrc->DRAMTMG3_ &= ~GENMASK(17, 12);
- ddrc->DRAMTMG3_ |= GENMASK(17, 12) & (DIV_ROUND_UP_2EVAL(data->tMOD + data->PL, 2) << 12); /* tMRD. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. */
+ ddrc->DRAMTMG3_ |= GENMASK(17, 12) & (DIV_ROUND_UP_2EVAL(data->tMOD + data->PL, 2) << 12); /* tMRD. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD + PL) instead. */
ddrc->DRAMTMG3_ &= ~GENMASK(9, 0);
- ddrc->DRAMTMG3_ |= GENMASK(9, 0) & DIV_ROUND_UP_2EVAL(data->tMOD + data->PL + !!data->registered_dimm, 2); /* tMOD. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. */
+ ddrc->DRAMTMG3_ |= GENMASK(9, 0) & DIV_ROUND_UP_2EVAL(data->tMOD + data->PL + !!data->registered_dimm, 2); /* tMOD. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD + PL) instead. */
ddrc->DRAMTMG4_ &= ~GENMASK(28, 24);
ddrc->DRAMTMG4_ |= GENMASK(28, 24) & (((data->tRCD > data->AL) ? DIV_ROUND_UP_2EVAL(data->tRCD - data->AL, 2) : 1) << 24); /* tRCD - AL */
ddrc->DRAMTMG4_ &= ~GENMASK(19, 16);
ddrc->DRAMTMG5_ &= ~GENMASK(19, 16);
ddrc->DRAMTMG5_ |= GENMASK(19, 16) & (DIV_ROUND_UP_2EVAL(CLOCK_NS(10) + data->PL, 2) << 16); /* DDR4: max (10 ns, 5 tCK) (+ PL(parity latency)(*)) */
/* NOTICE: Only if CRCPARCTL1_ bit<12> = 0, this register should be increased by PL.
- * Note: val=9, but S_ Hudchenko example have val=6 */
+ * Note: val=9, but S_ Hudchenko example have val=6
+ */
ddrc->DRAMTMG5_ &= ~GENMASK(13, 8);
ddrc->DRAMTMG5_ |= GENMASK(13, 8) & (DIV_ROUND_UP_2EVAL(data->tCKE + 1 + data->PL, 2) << 8); /* DDR4: tCKE + 1 (+ PL(parity latency)(*)) */
/* NOTICE: Only if CRCPARCTL1_ bit<12> = 0, this register should be increased by PL.
- * Note: val=6, but S_Hudchenko example have val=4 */
+ * Note: val=6, but S_Hudchenko example have val=4
+ */
ddrc->DRAMTMG5_ &= ~GENMASK(4, 0);
ddrc->DRAMTMG5_ |= GENMASK(4, 0) & DIV_ROUND_UP_2EVAL(data->tCKE, 2);
ddrc->DRAMTMG8_ &= ~GENMASK(30, 24);
/* RC03 Command_Address and CS Driver Control */
uint8_t ca_drv = (data->registered_ca_stren >> 4) & 0x3;
uint8_t cs_drv = (data->registered_ca_stren >> 6) & 0x3;
+
phy->RDIMMGCR0_ &= ~GENMASK(15, 12);
phy->RDIMMGCR0_ |= GENMASK(15, 12) & (((cs_drv << 2) | ca_drv) << 12);
/* RC04 ODT and CKE Driver Control */
uint8_t cke_drv = (data->registered_ca_stren) & 0x3;
uint8_t odt_drv = (data->registered_ca_stren >> 2) & 0x3;
+
phy->RDIMMGCR0_ &= ~GENMASK(19, 16);
phy->RDIMMGCR0_ |= GENMASK(19, 16) & (((cke_drv << 2) | odt_drv) << 16);
/* RC05 Clock Driver Control */
uint8_t y0y2_drv = (data->registered_clk_stren) & 0x3;
uint8_t y1y3_drv = (data->registered_clk_stren >> 2) & 0x3;
+
phy->RDIMMGCR0_ &= ~GENMASK(23, 20);
phy->RDIMMGCR0_ |= GENMASK(23, 20) & (((y0y2_drv << 2) | y1y3_drv) << 20);
#else
phy->MR6_ = (data->tCCD_L - 4) << 10;
#endif
-
/* data training configuration */
phy->DTCR0_ |= 1 << 6; /* use MPR for DQS training (DDR4) */
phy->DTCR0_ &= ~GENMASK(31, 28);
uint32_t DTCR1_;
uint32_t DSGCR_;
uint32_t ZQCR_;
- unsigned dbus_half;
+ unsigned int dbus_half;
};
void phy_set_default_vals(struct phy_content *phy);
/*
- * Copyright (c) 2021, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2021-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
+#include <baikal_def.h>
#include "ddr_main.h"
enum {
uint32_t rtt_park;
};
-#if defined(BAIKAL_DBM10) || defined(BAIKAL_DBM20)
+#if defined(BAIKAL_DBM10) || defined(BAIKAL_DBM20) || defined(BAIKAL_QEMU)
static const struct odt_settings dram_odt_set_0[] = {
{ 0, 1, 2, 4 }, /* 1-rank (default) */
{ 0, 1, 2, 4 }, /* 2-rank (default) */
};
#endif
-int ddr_odt_configuration(const unsigned port,
+int ddr_odt_configuration(const unsigned int port,
const uint16_t crc_val,
struct ddr_configuration *const data)
{
- unsigned odt_set;
-#if defined(BAIKAL_DUAL_CHANNEL_MODE)
+ unsigned int odt_set;
+#ifdef BAIKAL_DUAL_CHANNEL_MODE
if (data->dimms == 2) {
goto dual_channel;
}
odt_set = ODT_SET_1RANK;
}
- if (!port) {
- data->RTT_PARK = dram_odt_set_0[odt_set].rtt_park;
- data->RTT_NOM = dram_odt_set_0[odt_set].rtt_nom;
- data->RTT_WR = dram_odt_set_0[odt_set].rtt_wr;
- data->DIC = dram_odt_set_0[odt_set].dic;
+ if (port == 0) {
+ data->RTT_PARK = dram_odt_set_0[odt_set].rtt_park;
+ data->RTT_NOM = dram_odt_set_0[odt_set].rtt_nom;
+ data->RTT_WR = dram_odt_set_0[odt_set].rtt_wr;
+ data->DIC = dram_odt_set_0[odt_set].dic;
} else {
- data->RTT_PARK = dram_odt_set_1[odt_set].rtt_park;
- data->RTT_NOM = dram_odt_set_1[odt_set].rtt_nom;
- data->RTT_WR = dram_odt_set_1[odt_set].rtt_wr;
- data->DIC = dram_odt_set_1[odt_set].dic;
+ data->RTT_PARK = dram_odt_set_1[odt_set].rtt_park;
+ data->RTT_NOM = dram_odt_set_1[odt_set].rtt_nom;
+ data->RTT_WR = dram_odt_set_1[odt_set].rtt_wr;
+ data->DIC = dram_odt_set_1[odt_set].dic;
}
return 0;
-#if defined(BAIKAL_DUAL_CHANNEL_MODE)
+#ifdef BAIKAL_DUAL_CHANNEL_MODE
dual_channel:
/***********************************************************************
* Due to high speed of the DDR4 Standard configuring controllers to
break;
}
}
+
if (port == 1) {
switch (crc_val) {
case 0xd8f1: /* MTA9ASF2G72AZ */
/*
- * Copyright (c) 2021-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2021-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
};
#endif
-void* ddr_read_spd(const unsigned dimm_idx)
+void *ddr_read_spd(const unsigned int dimm_idx)
{
extern struct spd_container spd_content;
uint8_t *p = (uint8_t *)&spd_content.content[dimm_idx];
#ifndef BAIKAL_DIMM_SPD_STATIC
- unsigned page;
+ unsigned int page;
int rxsize = 0;
const uint8_t spd_bus_addrs[] = {DIMM0_SPD_ADDR, DIMM1_SPD_ADDR};
uint8_t startaddr = 0;
#ifdef BAIKAL_DUAL_CHANNEL_MODE
uint8_t channel_bytes[SPD_PAGE_SIZE / 2];
#endif
-
assert(dimm_idx < ARRAY_SIZE(spd_bus_addrs));
for (page = 0; page < SPD_FULL_SIZE / SPD_PAGE_SIZE; ++page) {
int rxpsize;
- BAIKAL_SPD_BUS_HANDLER(BAIKAL_DIMM_SPD_DEV, SPD_SPA0 + page,
- &startaddr, sizeof(startaddr), NULL, 0);
- rxpsize = BAIKAL_SPD_BUS_HANDLER(BAIKAL_DIMM_SPD_DEV, spd_bus_addrs[dimm_idx],
- &startaddr, sizeof(startaddr), p + rxsize, SPD_PAGE_SIZE);
+ BAIKAL_SPD_TXRX(SPD_SPA0 + page, &startaddr, sizeof(startaddr), NULL, 0);
+ rxpsize = BAIKAL_SPD_TXRX(spd_bus_addrs[dimm_idx], &startaddr, sizeof(startaddr),
+ p + rxsize, SPD_PAGE_SIZE);
if (rxpsize != SPD_PAGE_SIZE) {
break;
}
rxsize += rxpsize;
}
- BAIKAL_SPD_BUS_HANDLER(BAIKAL_DIMM_SPD_DEV, SPD_SPA0, &startaddr, sizeof(startaddr), NULL, 0);
+ BAIKAL_SPD_TXRX(SPD_SPA0, &startaddr, sizeof(startaddr), NULL, 0);
if (rxsize != SPD_FULL_SIZE) {
return NULL;
ERROR("DIMM%u: SPD CRC checksum fail\n", dimm_idx);
return NULL;
}
-
#ifdef BAIKAL_DUAL_CHANNEL_MODE
- /*
- * Check if 2 DIMMs are inserted into the slots related to a single port
- */
- rxsize = BAIKAL_SPD_BUS_HANDLER(BAIKAL_DIMM_SPD_DEV, spd_bus_addrs[dimm_idx] + 1,
- &startaddr, sizeof(startaddr), &channel_bytes, SPD_PAGE_SIZE / 2);
+ /* Check if 2 DIMMs are inserted into the slots related to a single port */
+ rxsize = BAIKAL_SPD_TXRX(spd_bus_addrs[dimm_idx] + 1, &startaddr, sizeof(startaddr),
+ &channel_bytes, SPD_PAGE_SIZE / 2);
if (rxsize != SPD_PAGE_SIZE / 2) {
goto _exit;
}
if ((channel_bytes[126] != p[126]) || (channel_bytes[127] != p[127])) {
- ERROR("DDR PORT%d: can't work in 2-channel mode with DIMMs that differ\n", dimm_idx);
+ ERROR("Can't work in 2-channel mode with DIMMs that differ\n");
return NULL;
}
spd_content.dual_channel[dimm_idx] = 'y';
- /*
- * Read serial and part numbers from second DIMM
- */
- BAIKAL_SPD_BUS_HANDLER(BAIKAL_DIMM_SPD_DEV, SPD_SPA0 + 1, &startaddr, sizeof(startaddr), NULL, 0);
+ /* Read serial and part numbers from the second DIMM */
+ BAIKAL_SPD_TXRX(SPD_SPA0 + 1, &startaddr, sizeof(startaddr), NULL, 0);
startaddr = 69;
- rxsize = BAIKAL_SPD_BUS_HANDLER(BAIKAL_DIMM_SPD_DEV, spd_bus_addrs[dimm_idx] + 1,
- &startaddr, sizeof(startaddr), &channel_bytes, 24);
+ rxsize = BAIKAL_SPD_TXRX(spd_bus_addrs[dimm_idx] + 1, &startaddr, sizeof(startaddr),
+ &channel_bytes, 24);
if (rxsize == 24) {
spd_content.extra[dimm_idx].serial_number = *(uint32_t *)channel_bytes;
memcpy(spd_content.extra[dimm_idx].part_number, &channel_bytes[4], 20);
}
- BAIKAL_SPD_BUS_HANDLER(BAIKAL_DIMM_SPD_DEV, SPD_SPA0, &startaddr, sizeof(startaddr), NULL, 0);
+
+ BAIKAL_SPD_TXRX(SPD_SPA0, &startaddr, sizeof(startaddr), NULL, 0);
_exit:
#endif
return p;
uint8_t mod_thickness;
/* 130 (Unbuffered) Reference Raw Card Used */
uint8_t ref_raw_card;
- /* 131 (Unbuffered) Address Mapping from
- Edge Connector to DRAM */
+ /* 131 (Unbuffered) Address Mapping from Edge Connector to DRAM */
uint8_t addr_mapping;
/* 132~253 (Unbuffered) Reserved */
uint8_t res_132[254 - 132];
#define DDR4_SPD_MODULETYPE_16B_SO_DIMM 0x0c
#define DDR4_SPD_MODULETYPE_32B_SO_DIMM 0x0d
-void* ddr_read_spd(const unsigned dimm_idx);
+void *ddr_read_spd(const unsigned int dimm_idx);
#endif /* DDR_SPD_H */
--- /dev/null
+/*
+ * Copyright (c) 2023, Baikal Electronics, JSC. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+
+#include <baikal_def.h>
+#include <dw_i2c.h>
+#include <mbm_bmc.h>
+
+#define MBM_BMC_I2C_BUS MMAVLSP_I2C1_BASE
+#define MBM_BMC_I2C_ADDR 0x08
+#define MBM_BMC_REG_PWROFF_RQ 0x05
+#define MBM_BMC_REG_PWROFF_RQ_OFF 0x01
+#define MBM_BMC_REG_PWROFF_RQ_RESET 0x02
+
+void mbm_bmc_pwr_off(void)
+{
+ const uint8_t offreq[] = {
+ MBM_BMC_REG_PWROFF_RQ,
+ MBM_BMC_REG_PWROFF_RQ_OFF
+ };
+
+ INFO("BMC: power off\n");
+ i2c_txrx(MBM_BMC_I2C_BUS, BAIKAL_I2C_ICLK_FREQ,
+ MBM_BMC_I2C_ADDR, &offreq, sizeof(offreq), NULL, 0);
+
+ mdelay(4000);
+}
+
+void mbm_bmc_pwr_rst(void)
+{
+ const uint8_t rstreq[] = {
+ MBM_BMC_REG_PWROFF_RQ,
+ MBM_BMC_REG_PWROFF_RQ_RESET
+ };
+
+ INFO("BMC: power reset\n");
+ i2c_txrx(MBM_BMC_I2C_BUS, BAIKAL_I2C_ICLK_FREQ,
+ MBM_BMC_I2C_ADDR, &rstreq, sizeof(rstreq), NULL, 0);
+
+ mdelay(4000);
+}
--- /dev/null
+/*
+ * Copyright (c) 2023, Baikal Electronics, JSC. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MBM_BMC_H
+#define MBM_BMC_H
+
+void mbm_bmc_pwr_off(void);
+void mbm_bmc_pwr_rst(void);
+
+#endif /* MBM_BMC_H */
{
void *fdt = (void *)(uintptr_t)BAIKAL_SEC_DTB_BASE;
int memoff;
- unsigned region;
+ unsigned int region;
const uint32_t *prop;
int proplen;
int ret;
/*
- * Copyright (c) 2021-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2021-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define BAIKAL_BOOT_SPI_SUBSECTOR (4 * 1024)
#define BAIKAL_BOOT_SPI_SIZE (32 * 1024 * 1024)
+#define BAIKAL_I2C_ICLK_FREQ 100000000
+#define BAIKAL_SMBUS_ICLK_FREQ 50000000
#define SYS_COUNTER_FREQ_IN_TICKS ULL(50000000)
#if defined(BAIKAL_DBM10)
# define BAIKAL_DDR_CUSTOM_CLOCK_FREQ 800
-# define BAIKAL_SPD_BUS_HANDLER i2c_txrx
-# define BAIKAL_DIMM_SPD_DEV MMAVLSP_I2C2_BASE
+# define BAIKAL_SPD_TXRX(targetaddr, txbuf, txbufsize, rxbuf, rxbufsize) \
+ i2c_txrx(MMAVLSP_I2C2_BASE, BAIKAL_I2C_ICLK_FREQ, \
+ targetaddr, txbuf, txbufsize, rxbuf, rxbufsize)
#elif defined(BAIKAL_DBM20)
+# define BAIKAL_DUAL_CHANNEL_MODE
# define BAIKAL_DDR_CUSTOM_CLOCK_FREQ 1200
-# define BAIKAL_SPD_BUS_HANDLER smbus_txrx
-# define BAIKAL_DIMM_SPD_DEV MMAVLSP_SMBUS1_BASE
+# define BAIKAL_SPD_TXRX(targetaddr, txbuf, txbufsize, rxbuf, rxbufsize) \
+ smbus_txrx(MMAVLSP_SMBUS1_BASE, \
+ BAIKAL_SMBUS_ICLK_FREQ, SMBUS_SHT_100KHZ, 100000, \
+ targetaddr, txbuf, txbufsize, rxbuf, rxbufsize)
#elif defined(BAIKAL_MBM10) || defined(BAIKAL_MBM20)
# define BAIKAL_DDR_CUSTOM_CLOCK_FREQ 1200
-# define BAIKAL_SPD_BUS_HANDLER smbus_txrx
-# define BAIKAL_DIMM_SPD_DEV MMAVLSP_SMBUS1_BASE
+# define BAIKAL_SPD_TXRX(targetaddr, txbuf, txbufsize, rxbuf, rxbufsize) \
+ smbus_txrx(MMAVLSP_SMBUS1_BASE, \
+ BAIKAL_SMBUS_ICLK_FREQ, SMBUS_SHT_100KHZ, 100000, \
+ targetaddr, txbuf, txbufsize, rxbuf, rxbufsize)
# define BAIKAL_LVDS_CLKEN_GPIO_PIN 17
# define BAIKAL_HDMI_CLKEN_GPIO_PIN 18
#elif defined(BAIKAL_QEMU)
+ #define BAIKAL_DIMM_SPD_STATIC
# undef SYS_COUNTER_FREQ_IN_TICKS
# define SYS_COUNTER_FREQ_IN_TICKS ULL((1000 * 1000 * 1000) / 16)
#endif
#define MMAVLSP_CMU0_CLKCHCTL_TIMER2 (MMAVLSP_CMU0_BASE + CMU_CLKCHCTL_OFFSET(9))
#define MMAVLSP_CMU0_CLKCHCTL_TIMER3 (MMAVLSP_CMU0_BASE + CMU_CLKCHCTL_OFFSET(10))
#define MMAVLSP_CMU0_CLKCHCTL_TIMER4 (MMAVLSP_CMU0_BASE + CMU_CLKCHCTL_OFFSET(11))
-#define MMAVLSP_CMU0_CLKCHCTL_DMAC (MMAVLSP_CMU0_BASE + CMU_CLKCHCTL_OFFSET(12))
+#define MMAVLSP_CMU0_CLKCHCTL_DMACLSP (MMAVLSP_CMU0_BASE + CMU_CLKCHCTL_OFFSET(12))
#define MMAVLSP_CMU0_CLKCHCTL_SMBUS1 (MMAVLSP_CMU0_BASE + CMU_CLKCHCTL_OFFSET(13))
#define MMAVLSP_CMU0_CLKCHCTL_SMBUS2 (MMAVLSP_CMU0_BASE + CMU_CLKCHCTL_OFFSET(14))
#define MMAVLSP_CMU0_CLKCHCTL_HDA_SYS (MMAVLSP_CMU0_BASE + CMU_CLKCHCTL_OFFSET(15))
#define MMAVLSP_GPR_MMRST1_NIC_CFG_M_RST BIT(1)
#define MMAVLSP_GPR_MMRST1_NIC_S_RST BIT(2)
#define MMAVLSP_GPR_MMRST1_NIC_M_RST BIT(3)
-#define MMAVLSP_GPR_MMRST1_DMAC_RST BIT(6)
+#define MMAVLSP_GPR_MMRST1_DMACLSP_RST BIT(6)
#define MMAVLSP_GPR_MMRST1_SMMU_RST BIT(7)
#define MMAVLSP_GPR_MMRST1_GPIO_RST BIT(10)
#define MMAVLSP_GPR_MMRST1_UART1_RST BIT(11)
#define MMAVLSP_SMBUS1_BASE (MMAVLSP_BASE + 0x270000)
#define MMAVLSP_SMBUS2_BASE (MMAVLSP_BASE + 0x280000)
#define MMAVLSP_VDU_BASE (MMAVLSP_BASE + 0x2d0000)
+#define MMAVLSP_EMMC_BASE (MMAVLSP_BASE + 0x2e0000)
#define MMCA57_0_BASE U(0x28000000)
#define MMCA57_0_CMU0_BASE (MMCA57_0_BASE)
#define MMDDR0_NIC_CFG_GPV_REGIONSEC_CTRLR (MMDDR0_NIC_CFG_GPV_BASE + 0x08)
#define MMDDR0_NIC_CFG_GPV_REGIONSEC_PHY (MMDDR0_NIC_CFG_GPV_BASE + 0x0c)
#define MMDDR0_CTRL_BASE (MMDDR0_BASE + 0x200000)
+#define MMDDR0_PHY_BASE (MMDDR0_BASE + 0x210000)
#define MMDDR1_BASE U(0x22000000)
#define MMDDR1_CMU0_BASE (MMDDR1_BASE)
#define MMDDR1_NIC_CFG_GPV_REGIONSEC_CTRLR (MMDDR1_NIC_CFG_GPV_BASE + 0x08)
#define MMDDR1_NIC_CFG_GPV_REGIONSEC_PHY (MMDDR1_NIC_CFG_GPV_BASE + 0x0c)
#define MMDDR1_CTRL_BASE (MMDDR1_BASE + 0x200000)
+#define MMDDR1_PHY_BASE (MMDDR1_BASE + 0x210000)
#define MMMALI_BASE U(0x2a000000)
#define MMMALI_CMU0_BASE (MMMALI_BASE)
#define MMUSB_CMU0_CLKCHCTL_USB3_SOFITP (MMUSB_CMU0_BASE + CMU_CLKCHCTL_OFFSET(12))
#define MMUSB_CMU0_CLKCHCTL_USB3_SUSPEND (MMUSB_CMU0_BASE + CMU_CLKCHCTL_OFFSET(13))
#define MMUSB_CMU0_CLKCHCTL_SMMU (MMUSB_CMU0_BASE + CMU_CLKCHCTL_OFFSET(14))
-#define MMUSB_CMU0_CLKCHCTL_DMAC (MMUSB_CMU0_BASE + CMU_CLKCHCTL_OFFSET(15))
+#define MMUSB_CMU0_CLKCHCTL_DMACM2M (MMUSB_CMU0_BASE + CMU_CLKCHCTL_OFFSET(15))
#define MMUSB_CMU0_CLKCHCTL_GIC (MMUSB_CMU0_BASE + CMU_CLKCHCTL_OFFSET(16))
#define MMUSB_GPR_BASE (MMUSB_BASE + 0x50000)
#define MMUSB_GPR_MMRST (MMUSB_GPR_BASE + 0x00)
#define MMUSB_NIC_CFG_GPV_REGIONSEC_SATA1 (MMUSB_NIC_CFG_GPV_BASE + 0x14)
#define MMUSB_NIC_CFG_GPV_REGIONSEC_SMMU (MMUSB_NIC_CFG_GPV_BASE + 0x18)
#define MMUSB_NIC_CFG_GPV_REGIONSEC_GIC (MMUSB_NIC_CFG_GPV_BASE + 0x1c)
-#define MMUSB_NIC_CFG_GPV_REGIONSEC_DMACS (MMUSB_NIC_CFG_GPV_BASE + 0x20)
-#define MMUSB_NIC_CFG_GPV_REGIONSEC_DMACN (MMUSB_NIC_CFG_GPV_BASE + 0x24)
+#define MMUSB_NIC_CFG_GPV_REGIONSEC_DMACM2MS (MMUSB_NIC_CFG_GPV_BASE + 0x20)
+#define MMUSB_NIC_CFG_GPV_REGIONSEC_DMACM2MN (MMUSB_NIC_CFG_GPV_BASE + 0x24)
#define MMUSB_USB2_BASE (MMUSB_BASE + 0x400000)
#define MMUSB_USB3_BASE (MMUSB_BASE + 0x500000)
#define MMUSB_SATA0_BASE (MMUSB_BASE + 0x600000)
/* Input 25 MHz, but recommended freq is 1.19 MHz => 21 is div */
#define PVT_CLKCH_DIV 21
+#define MMAVLSP_PLL_FREQ ULL(1200000000)
+
#endif /* BM1000_DEF_H */
/*
- * Copyright (c) 2018-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2018-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define BAIKAL_SEC_DTB_BASE (SEC_DRAM_BASE + BL1_XLAT_SIZE)
#define BAIKAL_NS_DTB_BASE NS_DRAM0_BASE
#define BAIKAL_NS_IMAGE_OFFSET NS_DRAM1_BASE
+#define BAIKAL_NS_IMAGE_MAX_SIZE NS_DRAM1_SIZE
/*
* BL1 specific defines.
#define DEV_QOS_OVERRIDE_EN BIT(2)
/* Parts of the boot image */
+#define BAIKAL_BOOT_OFFSET 0
+#define BAIKAL_BOOT_MAX_SIZE (8 * 1024 * 1024)
+
#define BAIKAL_SCP_MAX_SIZE (512 * 1024)
#define BAIKAL_BL1_MAX_SIZE (256 * 1024)
#define BAIKAL_DTB_MAX_SIZE (256 * 1024)
#define BAIKAL_VAR_MAX_SIZE (768 * 1024)
-#define BAIKAL_FIP_MAX_SIZE (BAIKAL_FAT_OFFSET - BAIKAL_BL1_MAX_SIZE - BAIKAL_DTB_MAX_SIZE - BAIKAL_VAR_MAX_SIZE)
+#define BAIKAL_FIP_MAX_SIZE (BAIKAL_BOOT_MAX_SIZE - BAIKAL_FIP_OFFSET)
#define BAIKAL_BL1_OFFSET 0
#define BAIKAL_DTB_OFFSET (BAIKAL_BL1_OFFSET + BAIKAL_BL1_MAX_SIZE)
#define BAIKAL_VAR_OFFSET (BAIKAL_DTB_OFFSET + BAIKAL_DTB_MAX_SIZE)
#define BAIKAL_FIP_OFFSET (BAIKAL_VAR_OFFSET + BAIKAL_VAR_MAX_SIZE)
-#define BAIKAL_FAT_OFFSET (8 * 1024 * 1024)
+#define BAIKAL_FAT_OFFSET (BAIKAL_FIP_OFFSET + BAIKAL_FIP_MAX_SIZE)
+
+#define BAIKAL_SD_FIRMWARE
+#define BAIKAL_SD_FIRMWARE_DEBUG
+#define BAIKAL_SD_FIRMWARE_OFFSET (2048 * 512) /* dev/mmcblk0p1: LBA 2048 */
#endif /* PLATFORM_DEF_H */
include lib/libfdt/libfdt.mk
include lib/xlat_tables_v2/xlat_tables.mk
+$(eval $(call add_define_val,SDK_VERSION,$(SDK_VERSION)))
+
USE_COHERENT_MEM := 1
PLAT_INCLUDES := -Iinclude/plat/arm/common/aarch64 \
-Iplat/baikal/bm1000/include \
-Iplat/baikal/common/include
-PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \
+PLAT_BL_COMMON_SOURCES := drivers/mmc/mmc.c \
+ drivers/ti/uart/aarch64/16550_console.S \
plat/baikal/bm1000/aarch64/bm1000_helpers.S \
plat/baikal/bm1000/bm1000_common.c \
+ plat/baikal/bm1000/bm1000_font.c \
+ plat/baikal/bm1000/bm1000_mmavlsp.c \
+ plat/baikal/bm1000/bm1000_mmca57.c \
+ plat/baikal/bm1000/bm1000_mmxgbe.c \
plat/baikal/bm1000/drivers/bm1000_scp.c \
plat/baikal/bm1000/drivers/bm1000_scp_flash.c \
plat/baikal/common/aarch64/baikal_helpers.S \
plat/baikal/common/baikal_bootflash.c \
plat/baikal/common/baikal_console.c \
+ plat/baikal/common/baikal_mshc.c \
plat/baikal/common/dw_gpio.c \
plat/baikal/common/dw_spi_flash.c \
${XLAT_TABLES_LIB_SRCS}
$(eval $(call add_define,BAIKAL_DBM10))
else ifeq ($(BAIKAL_TARGET),dbm20)
$(eval $(call add_define,BAIKAL_DBM20))
-$(eval $(call add_define,BAIKAL_DUAL_CHANNEL_MODE))
else ifeq ($(BAIKAL_TARGET),mbm10)
$(eval $(call add_define,BAIKAL_MBM10))
else ifeq ($(BAIKAL_TARGET),mbm20)
BL1_SOURCES += drivers/arm/ccn/ccn.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
- drivers/io/io_dummy.c \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
lib/cpus/aarch64/cortex_a57.S \
plat/arm/common/arm_ccn.c \
- plat/baikal/bm1000/bm1000_bl1_logo.c \
plat/baikal/bm1000/bm1000_bl1_setup.c \
- plat/baikal/bm1000/bm1000_mmxgbe.c \
plat/baikal/bm1000/bm1000_splash.c \
plat/baikal/bm1000/drivers/bm1000_cmu.c \
plat/baikal/bm1000/drivers/bm1000_smbus.c \
plat/baikal/bm1000/drivers/ddr/ddr_lcru.c \
plat/baikal/bm1000/drivers/ddr/ddr_main.c \
plat/baikal/bm1000/drivers/ddr/ddr_master.c \
+ plat/baikal/bm1000/drivers/ddr/ddr_odt_settings.c\
+ plat/baikal/bm1000/drivers/ddr/ddr_spd.c \
plat/baikal/common/baikal_bl1_stack.c \
plat/baikal/common/baikal_common.c \
plat/baikal/common/baikal_io_storage.c \
plat/baikal/common/dw_i2c.c \
plat/baikal/common/memtest.c \
plat/baikal/common/ndelay.c
-ifneq ($(BAIKAL_TARGET),qemu-m)
-BL1_SOURCES += plat/baikal/bm1000/drivers/ddr/ddr_odt_settings.c\
- plat/baikal/bm1000/drivers/ddr/ddr_spd.c
-endif
-override BL1_LINKERFILE := plat/baikal/common/bl1.ld.S
+override BL1_DEFAULT_LINKER_SCRIPT_SOURCE := plat/baikal/common/bl1.ld.S
BL2_SOURCES += common/desc_image_load.c \
- drivers/io/io_dummy.c \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
lib/cpus/aarch64/cortex_a57.S \
plat/arm/common/arm_ccn.c \
plat/baikal/bm1000/bm1000_bl31_logo.c \
- plat/baikal/bm1000/bm1000_bl31_sdk_version_logo.c\
plat/baikal/bm1000/bm1000_bl31_setup.c \
- plat/baikal/bm1000/bm1000_mmavlsp.c \
- plat/baikal/bm1000/bm1000_mmca57.c \
plat/baikal/bm1000/bm1000_mmcoresight.c \
plat/baikal/bm1000/bm1000_mmmali.c \
plat/baikal/bm1000/bm1000_mmpcie.c \
plat/baikal/bm1000/bm1000_mmusb.c \
plat/baikal/bm1000/bm1000_mmvdec.c \
- plat/baikal/bm1000/bm1000_mmxgbe.c \
plat/baikal/bm1000/bm1000_pm.c \
plat/baikal/bm1000/bm1000_sip_svc.c \
plat/baikal/bm1000/bm1000_splash.c \
plat/baikal/bm1000/bm1000_topology.c \
plat/baikal/bm1000/drivers/bm1000_cmu.c \
+ plat/baikal/bm1000/drivers/bm1000_efuse.c \
plat/baikal/bm1000/drivers/bm1000_smmu.c \
+ plat/baikal/bm1000/drivers/mbm_bmc.c \
plat/baikal/bm1000/dt.c \
plat/baikal/common/baikal_bl31_setup.c \
plat/baikal/common/baikal_common.c \
${GICV3_SOURCES} \
$(LIBFDT_SRCS)
+ifeq (${ENABLE_PMF}, 1)
+BL31_SOURCES += lib/pmf/pmf_smc.c
+endif
+
ifeq ($(notdir $(CC)),armclang)
TF_CFLAGS_aarch64 += -mcpu=cortex-a57
else ifneq ($(findstring clang,$(notdir $(CC))),)
ERRATA_A57_833471 := 0
ERRATA_A57_859972 := 1
ERRATA_A57_1319537 := 1
+
+BL1_CPPFLAGS += -march=armv8-a+crc
+BL2_CPPFLAGS += -march=armv8-a+crc
+BL2U_CPPFLAGS += -march=armv8-a+crc
+BL31_CPPFLAGS += -march=armv8-a+crc
+BL32_CPPFLAGS += -march=armv8-a+crc
/*
- * Copyright (c) 2020-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2020-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
int dram_init(void);
static uint64_t trusted_mailbox[1 + PLATFORM_CORE_COUNT]
- __attribute__ ((used, section(".trusted_mailbox")));
+ __section(".trusted_mailbox") __used;
CASSERT(sizeof(trusted_mailbox) == BAIKAL_TRUSTED_MAILBOX_SIZE,
assert_trusted_mailbox_size);
err = memtest_rand64(BL1_XLAT_BASE, BL1_XLAT_SIZE, sizeof(uint64_t), read_cntpct_el0());
#if DEBUG
- err |= memtest_rand8( BL1_XLAT_BASE, BL1_XLAT_SIZE, sizeof(uint8_t), read_cntpct_el0());
+ err |= memtest_rand8(BL1_XLAT_BASE, BL1_XLAT_SIZE, sizeof(uint8_t), read_cntpct_el0());
#endif
if (err) {
ERROR("%s: DRAM error\n", __func__);
u_register_t arg3)
{
meminfo_t *mem_layout = (meminfo_t *)arg1;
+
baikal_console_boot_init();
/* Setup the BL2 memory layout */
/*
- * Copyright (c) 2020-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2020-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <baikal_def.h>
#include <baikal_gicv3.h>
#include <bs1000_cmu.h>
+#include <bs1000_coresight.h>
#include <bs1000_dimm_spd.h>
+#include <bs1000_gmac.h>
#include <bs1000_scp_lcru.h>
#include <bs1000_usb.h>
-#include <bs1000_coresight.h>
-#include <bs1000_gmac.h>
#include "bs1000_pcie.h"
mmio_write_32(NIC_LSP_CFG_UART_S, NIC_GPV_REGIONSEC_NONSECURE);
mmio_write_32(NIC_LSP_CFG_WDT, NIC_GPV_REGIONSEC_NONSECURE);
- mmio_write_32(DDR0_NIC_CFG_CTRL, NIC_GPV_REGIONSEC_NONSECURE);
- mmio_write_32(DDR1_NIC_CFG_CTRL, NIC_GPV_REGIONSEC_NONSECURE);
- mmio_write_32(DDR2_NIC_CFG_CTRL, NIC_GPV_REGIONSEC_NONSECURE);
- mmio_write_32(DDR3_NIC_CFG_CTRL, NIC_GPV_REGIONSEC_NONSECURE);
- mmio_write_32(DDR4_NIC_CFG_CTRL, NIC_GPV_REGIONSEC_NONSECURE);
- mmio_write_32(DDR5_NIC_CFG_CTRL, NIC_GPV_REGIONSEC_NONSECURE);
+ mmio_write_32(DDR0_NIC_CFG_CTRL, NIC_GPV_REGIONSEC_NONSECURE);
+ mmio_write_32(DDR1_NIC_CFG_CTRL, NIC_GPV_REGIONSEC_NONSECURE);
+ mmio_write_32(DDR2_NIC_CFG_CTRL, NIC_GPV_REGIONSEC_NONSECURE);
+ mmio_write_32(DDR3_NIC_CFG_CTRL, NIC_GPV_REGIONSEC_NONSECURE);
+ mmio_write_32(DDR4_NIC_CFG_CTRL, NIC_GPV_REGIONSEC_NONSECURE);
+ mmio_write_32(DDR5_NIC_CFG_CTRL, NIC_GPV_REGIONSEC_NONSECURE);
bs1000_coresight_init();
pcie_init();
void ca75_core_enable(const u_register_t mpidr)
{
- const unsigned cluster = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK;
- const unsigned core = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+ const unsigned int cluster = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK;
+ const unsigned int core = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
assert(cluster < PLATFORM_CLUSTER_COUNT);
assert(core < PLATFORM_MAX_CPUS_PER_CLUSTER);
void ca75_core_warm_reset(const u_register_t mpidr)
{
- const unsigned cluster = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK;
- const unsigned core = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+ const unsigned int cluster = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK;
+ const unsigned int core = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
assert(cluster < PLATFORM_CLUSTER_COUNT);
assert(core < PLATFORM_MAX_CPUS_PER_CLUSTER);
while ((mmio_read_32(base + CA75_GPR_DSU_CORE0_PMU_STS + 8 * core) &
(CA75_GPR_DSU_CORE_PMU_STS_PACCEPT |
CA75_GPR_DSU_CORE_PMU_STS_PDENY)) !=
- CA75_GPR_DSU_CORE_PMU_STS_PACCEPT);
+ CA75_GPR_DSU_CORE_PMU_STS_PACCEPT)
+ ;
/* Deassert PREQ */
mmio_clrbits_32(base + CA75_GPR_DSU_CORE0_PMU_CTL + 8 * core,
/* Wait for PACCEPT == 0 */
while (mmio_read_32(base + CA75_GPR_DSU_CORE0_PMU_STS + 8 * core) &
- CA75_GPR_DSU_CORE_PMU_STS_PACCEPT);
+ CA75_GPR_DSU_CORE_PMU_STS_PACCEPT)
+ ;
/* Assert core warm reset */
mmio_setbits_32(base + CA75_GPR_RST_CTL,
while ((mmio_read_32(base + CA75_GPR_DSU_CORE0_PMU_STS + 8 * core) &
(CA75_GPR_DSU_CORE_PMU_STS_PACCEPT |
CA75_GPR_DSU_CORE_PMU_STS_PDENY)) !=
- CA75_GPR_DSU_CORE_PMU_STS_PACCEPT);
+ CA75_GPR_DSU_CORE_PMU_STS_PACCEPT)
+ ;
/* Deassert PREQ */
mmio_clrbits_32(base + CA75_GPR_DSU_CORE0_PMU_CTL + 8 * core,
/* Wait for PACCEPT == 0 */
while (mmio_read_32(base + CA75_GPR_DSU_CORE0_PMU_STS + 8 * core) &
- CA75_GPR_DSU_CORE_PMU_STS_PACCEPT);
+ CA75_GPR_DSU_CORE_PMU_STS_PACCEPT)
+ ;
}
/*
- * Copyright (c) 2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2022-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/utils_def.h>
+#include <baikal_def.h>
#include <bs1000_def.h>
#include <crc.h>
#include <dw_i2c.h>
static uint8_t spd_data[DIMM_NUM][SPD_MAXSIZE];
-const void* baikal_dimm_spd_get(const unsigned dimm_idx)
+const void *baikal_dimm_spd_get(const unsigned int dimm_idx)
{
if (dimm_idx >= ARRAY_SIZE(spd_data)) {
return NULL;
void baikal_dimm_spd_read(void)
{
- unsigned dimm_idx;
+ unsigned int dimm_idx;
for (dimm_idx = 0; dimm_idx < ARRAY_SIZE(spd_data); ++dimm_idx) {
const uintptr_t base = dimm_idx < 6 ? I2C2_BASE : I2C3_BASE;
uint8_t *buf = spd_data[dimm_idx];
int rxsize;
- const unsigned spd_addr = 0x50 + dimm_idx % 6;
+ const unsigned int spd_addr = 0x50 + dimm_idx % 6;
uint8_t startaddr = 0;
memset(buf, 0xff, sizeof(spd_data[0]));
- i2c_txrx(base, SPD_SPA0,
+ i2c_txrx(base, BAIKAL_I2C_ICLK_FREQ,
+ SPD_SPA0,
&startaddr, sizeof(startaddr),
NULL, 0);
- rxsize = i2c_txrx(base, spd_addr,
+ rxsize = i2c_txrx(base, BAIKAL_I2C_ICLK_FREQ,
+ spd_addr,
&startaddr, sizeof(startaddr),
buf, 128);
if (rxsize == 128 &&
crc16(buf, 126, 0) == spd_get_baseconf_crc(buf)) {
- const unsigned bytes_used = buf[0] & 0xf;
+ const unsigned int bytes_used = buf[0] & 0xf;
if (bytes_used > 1 && bytes_used < 5) {
buf += rxsize;
startaddr += rxsize;
- rxsize = i2c_txrx(base, spd_addr,
+ rxsize = i2c_txrx(base, BAIKAL_I2C_ICLK_FREQ,
+ spd_addr,
&startaddr, sizeof(startaddr),
buf, 128);
if (rxsize == 128 && bytes_used > 2) {
buf += rxsize;
startaddr = 0;
- i2c_txrx(base, SPD_SPA1,
+ i2c_txrx(base, BAIKAL_I2C_ICLK_FREQ,
+ SPD_SPA1,
&startaddr, sizeof(startaddr),
NULL, 0);
- i2c_txrx(base, spd_addr,
+ i2c_txrx(base, BAIKAL_I2C_ICLK_FREQ,
+ spd_addr,
&startaddr, sizeof(startaddr),
buf, bytes_used == 3 ? 128 : 256);
- i2c_txrx(base, SPD_SPA0,
+ i2c_txrx(base, BAIKAL_I2C_ICLK_FREQ,
+ SPD_SPA0,
&startaddr, sizeof(startaddr),
NULL, 0);
}
static uint64_t baikal_detect_sdram_capacity(void)
{
- unsigned dimm_idx;
+ unsigned int dimm_idx;
uint64_t total_capacity = 0;
for (dimm_idx = 0; ; ++dimm_idx) {
{
void *fdt = (void *)BAIKAL_SEC_DTB_BASE;
uint64_t region_descs[4][2];
- unsigned region_num;
+ unsigned int region_num;
int ret;
uint64_t total_capacity;
void pcie_init(void)
{
void *fdt = (void *)(uintptr_t)BAIKAL_SEC_DTB_BASE;
- unsigned idx;
+ unsigned int idx;
int node = -1;
const uintptr_t pcie_dbis[14] = {
PCIE4_NIC_SLV_P3
};
- unsigned pcie_lanes[ARRAY_SIZE(pcie_dbis)];
- unsigned pcie_types[ARRAY_SIZE(pcie_dbis)];
+ unsigned int pcie_lanes[ARRAY_SIZE(pcie_dbis)];
+ unsigned int pcie_types[ARRAY_SIZE(pcie_dbis)];
if (fdt_open_into(fdt, fdt, BAIKAL_DTB_MAX_SIZE)) {
return;
/* Configure PCIe in accordance with FDT */
for (;;) {
bool endpoint;
- unsigned lanes = 0;
+ unsigned int lanes = 0;
const uint32_t *prop;
int proplen;
uint64_t reg;
0x2);
} else {
ERROR("PCIe3: incorrect subsystem mode\n");
+ plat_panic_handler();
}
} else if (pcie_types[9] > 0) {
if (pcie_lanes[6] <= 8 &&
0x3);
} else {
ERROR("PCIe3: incorrect subsystem mode\n");
+ plat_panic_handler();
}
} else if (pcie_types[8] > 0) {
if (pcie_lanes[6] <= 8 &&
0x1);
} else {
ERROR("PCIe3: incorrect subsystem mode\n");
+ plat_panic_handler();
}
} else if (pcie_types[6] > 0) {
if (pcie_lanes[6] <= 16) {
PCIE_GPR_SS_MODE_CTL_SSMODE_MASK);
} else {
ERROR("PCIe3: incorrect subsystem mode\n");
+ plat_panic_handler();
}
}
0x2);
} else {
ERROR("PCIe4: incorrect subsystem mode\n");
+ plat_panic_handler();
}
} else if (pcie_types[13] > 0) {
if (pcie_lanes[10] <= 8 &&
0x3);
} else {
ERROR("PCIe4: incorrect subsystem mode\n");
+ plat_panic_handler();
}
} else if (pcie_types[12] > 0) {
if (pcie_lanes[10] <= 8 &&
0x1);
} else {
ERROR("PCIe4: incorrect subsystem mode\n");
+ plat_panic_handler();
}
} else if (pcie_types[10] > 0) {
if (pcie_lanes[10] <= 16) {
PCIE_GPR_SS_MODE_CTL_SSMODE_MASK);
} else {
ERROR("PCIe4: incorrect subsystem mode\n");
+ plat_panic_handler();
+ }
+ }
+
+ /* Set ITS target address */
+ for (idx = 0; idx < ARRAY_SIZE(pcie_dbis); ++idx) {
+ if (pcie_types[idx] != PCIE_TYPE_RC) {
+ continue;
+ }
+
+ switch (pcie_dbis[idx]) {
+ case PCIE0_P0_DBI_BASE:
+ case PCIE0_P1_DBI_BASE:
+ mmio_write_32(PCIE0_GPR_ITS0_TRGTADDR_CTL, GITS0_TRANSLATER >> 16);
+ break;
+ case PCIE1_P0_DBI_BASE:
+ case PCIE1_P1_DBI_BASE:
+ mmio_write_32(PCIE1_GPR_ITS0_TRGTADDR_CTL, GITS2_TRANSLATER >> 16);
+ break;
+ case PCIE2_P0_DBI_BASE:
+ case PCIE2_P1_DBI_BASE:
+ mmio_write_32(PCIE2_GPR_ITS0_TRGTADDR_CTL, GITS4_TRANSLATER >> 16);
+ break;
+ case PCIE3_P0_DBI_BASE:
+ mmio_write_32(PCIE3_GPR_ITS0_TRGTADDR_CTL, GITS6_TRANSLATER >> 16);
+ break;
+ case PCIE3_P1_DBI_BASE:
+ mmio_write_32(PCIE3_GPR_ITS1_TRGTADDR_CTL, GITS7_TRANSLATER >> 16);
+ break;
+ case PCIE3_P2_DBI_BASE:
+ mmio_write_32(PCIE3_GPR_ITS2_TRGTADDR_CTL, GITS8_TRANSLATER >> 16);
+ break;
+ case PCIE3_P3_DBI_BASE:
+ mmio_write_32(PCIE3_GPR_ITS3_TRGTADDR_CTL, GITS9_TRANSLATER >> 16);
+ break;
+ case PCIE4_P0_DBI_BASE:
+ mmio_write_32(PCIE4_GPR_ITS0_TRGTADDR_CTL, GITS11_TRANSLATER >> 16);
+ break;
+ case PCIE4_P1_DBI_BASE:
+ mmio_write_32(PCIE4_GPR_ITS1_TRGTADDR_CTL, GITS12_TRANSLATER >> 16);
+ break;
+ case PCIE4_P2_DBI_BASE:
+ mmio_write_32(PCIE4_GPR_ITS2_TRGTADDR_CTL, GITS13_TRANSLATER >> 16);
+ break;
+ case PCIE4_P3_DBI_BASE:
+ mmio_write_32(PCIE4_GPR_ITS3_TRGTADDR_CTL, GITS14_TRANSLATER >> 16);
+ break;
}
}
/*
- * Copyright (c) 2020-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2020-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
static int bs1000_validate_power_state(unsigned int power_state, psci_power_state_t *req_state)
{
- unsigned i;
- unsigned state_id;
+ unsigned int i;
+ unsigned int state_id;
/*
* The table storing the valid idle power states. Ensure that the
* The table must be terminated by a NULL entry.
*/
static const unsigned int idle_states[] = {
- /* state-id - 0x01 */
+ /* state-id - 0x000 0001 */
bs1000_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN,
PLAT_LOCAL_STATE_RET,
MPIDR_AFFLVL0,
PSTATE_TYPE_STANDBY),
- /* state-id - 0x02 */
- bs1000_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN,
- PLAT_LOCAL_STATE_OFF,
- MPIDR_AFFLVL0,
- PSTATE_TYPE_POWERDOWN),
- /* state-id - 0x22 */
- bs1000_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF,
- PLAT_LOCAL_STATE_OFF,
- MPIDR_AFFLVL1,
- PSTATE_TYPE_POWERDOWN),
+ /* Ending element of idle_states */
0
};
static int bs1000_pwr_domain_on(u_register_t mpidr)
{
volatile uint64_t *const hold_base = (uint64_t *)BAIKAL_HOLD_BASE;
- const unsigned pos = plat_core_pos_by_mpidr(mpidr);
+ const unsigned int pos = plat_core_pos_by_mpidr(mpidr);
if (hold_base[pos] == BAIKAL_HOLD_STATE_WAIT) {
/* It is cold boot of a secondary core */
static void bs1000_pwr_domain_suspend(const psci_power_state_t *target_state)
{
ERROR("%s: operation not supported\n", __func__);
- panic();
}
static void bs1000_pwr_domain_on_finish(const psci_power_state_t *target_state)
static void bs1000_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
{
ERROR("%s: operation not supported\n", __func__);
- panic();
}
static void __dead2 bs1000_system_off(void)
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <lib/pmf/pmf.h>
+
#include <baikal_pvt.h>
#include <baikal_sip_svc.h>
#include <bs1000_cmu.h>
#include <bs1000_def.h>
#include <bs1000_scp_lcru.h>
-static uint64_t baikal_lsp_mux_handler(uint64_t mode)
+static int baikal_sip_setup(void)
{
- uint32_t val;
- int err;
-
- err = scp_lcru_read(SCP_GPR_LSP_CTL, &val);
- if (err)
- return err;
-
- val &= ~SCP_GPR_LSP_CTL_SEL_PERIPH_MASK;
- val |= (uint32_t)mode << SCP_GPR_LSP_CTL_SEL_PERIPH_SHIFT;
- err = scp_lcru_write(SCP_GPR_LSP_CTL, val);
-
- return err;
+#if ENABLE_PMF
+ if (pmf_setup() != 0) {
+ return 1;
+ }
+#endif
+ return cmu_desc_init();
}
static uintptr_t sip_smc_handler(uint32_t smc_fid,
void *handle,
u_register_t flags)
{
+ uint32_t local_smc_fid = smc_fid;
uint64_t ret;
uint64_t data[4];
SMC_RET1(handle, SMC_UNK);
}
- switch (smc_fid) {
+ if (GET_SMC_CC(smc_fid) == SMC_32) {
+ /* 32-bit function, clear top parameter bits */
+ x1 = (uint32_t)x1;
+ x2 = (uint32_t)x2;
+ x3 = (uint32_t)x3;
+ x4 = (uint32_t)x4;
+
+ /*
+ * Convert SMC FID to SMC64 to support SMC32/SMC64.
+ * SMC64 calls are expected to be the 64-bit equivalent
+ * to the 32-bit call, where applicable (ARM DEN 0028E).
+ */
+ local_smc_fid |= SMC_64 << FUNCID_CC_SHIFT;
+ }
+
+ switch (local_smc_fid) {
case BAIKAL_SMC_FLASH_ERASE:
case BAIKAL_SMC_FLASH_INIT:
case BAIKAL_SMC_FLASH_POSITION:
SMC_RET3(handle, ret, data[0], data[1]);
}
break;
- case BAIKAL_SMC_PVT_ID:
+ case BAIKAL_SMC_PVT_CMD:
if (x1 == PVT_READ) {
- ret = (uint64_t)pvt_read_reg((uint32_t)x2, (uint32_t)x3);
+ ret = pvt_read_reg(x2, x3);
} else if (x1 == PVT_WRITE) {
- ret = (uint64_t)pvt_write_reg((uint32_t)x2, (uint32_t)x3, (uint32_t)x4);
+ ret = pvt_write_reg(x2, x3, x4);
} else {
ERROR("%s: unhandled PVT SMC, x1:0x%lx\n", __func__, x1);
ret = SMC_UNK;
ret = baikal_smc_gmac_handler(smc_fid, x1, x2, x3, x4);
break;
case BAIKAL_SMC_LSP_MUX:
- ret = baikal_lsp_mux_handler(x1);
+ ret = scp_lcru_clrsetbits(SCP_GPR_LSP_CTL,
+ SCP_GPR_LSP_CTL_SEL_PERIPH_MASK,
+ x1 << SCP_GPR_LSP_CTL_SEL_PERIPH_SHIFT);
break;
default:
+#if ENABLE_PMF
+ /* Dispatch PMF calls to PMF SMC handler and return its return value */
+ if (is_pmf_fid(smc_fid)) {
+ return pmf_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
+ }
+#endif
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
ret = SMC_UNK;
break;
OEN_SIP_START,
OEN_SIP_END,
SMC_TYPE_FAST,
- cmu_desc_init,
+ baikal_sip_setup,
sip_smc_handler
);
#define cmu_clken_t cmu_clkdiv_t
-static const char *noname="";
+static const char *noname = "";
static const struct clk_ops ops_clkref = {
.get = cmu_clkref_get_rate,
{
struct clk_desc *clk;
int idx;
+
for (idx = 0; ; idx++) {
clk = cmu_desc_get_by_idx(idx);
if (!clk) {
break;
}
+
if (clk->base == base) {
return clk;
}
}
+
return NULL;
}
struct clk_desc *cmu_desc_create(void *fdt, int offs, int index)
{
- static int next = 0;
+ static int next;
uintptr_t base = 0;
const fdt32_t *prop;
int proplen;
int cnt0 = proplen / sizeof(uint32_t);
int cnt1 = fdt_stringlist_count(fdt, offs, "clock-output-names");
int cnt = cnt0 > cnt1 ? cnt0 : cnt1;
+
if (cnt < 0) {
cnt = 1;
}
+
if (index > cnt - 1) {
return NULL;
}
+
if (cnt0 > 0) {
base += fdt32_to_cpu(prop[index]) * 0x10;
} else if (cnt1 > 0) {
if (proplen > 0) {
int phandle = fdt32_to_cpu(prop[0]);
int idx = 0;
+
if (proplen > sizeof(uint32_t)) {
idx = fdt32_to_cpu(prop[1]);
}
+
int offs2 = fdt_node_offset_by_phandle(fdt, phandle);
+
clk->parent = cmu_desc_create(fdt, offs2, idx);
if (clk->parent == NULL) {
return NULL;
prop = fdt_getprop(fdt, offs, "clock-frequency", &proplen);
if (proplen > 0) {
uint64_t freq = fdt32_to_cpu(*prop);
+
if (freq != clk->ops->get(base)) {
clk->ops->set(base, freq);
}
int i;
void *fdt = (void *)(uintptr_t)BAIKAL_NS_DTB_BASE;
int ret = fdt_open_into(fdt, fdt, BAIKAL_DTB_MAX_SIZE);
+
if (ret < 0) {
ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
return -1;
}
+
for (;;) {
offs = fdt_next_node(fdt, offs, NULL);
if (offs < 0) {
break;
}
+
if (!fdt_node_check_compatible(fdt, offs, "baikal,bs1000-cmu")) {
for (i = 0; ; i++) {
- if (NULL == cmu_desc_create(fdt, offs, i)) {
+ if (cmu_desc_create(fdt, offs, i) == NULL) {
break;
}
}
}
}
+
return 0;
}
static int reg_write(uintptr_t addr, uint32_t value)
{
- if ((addr > SCP_LCRU_BASE) &&
- (addr < SCP_LCRU_BASE + SCP_LCRU_SIZE)) {
+ if ((addr >= SCP_LCRU_BASE) &&
+ (addr < SCP_LCRU_BASE + SCP_LCRU_SIZE)) {
int ret = scp_lcru_write(addr, value);
+
if (ret < 0) {
return ret;
}
if ((addr >= SCP_LCRU_BASE) &&
(addr < SCP_LCRU_BASE + SCP_LCRU_SIZE)) {
int ret = scp_lcru_read(addr, value);
+
if (ret < 0) {
return ret;
}
int cmu_log2(int a)
{
int n = 0;
+
while (a >>= 1) {
n++;
}
+
return n;
}
int64_t cmu_get_ref(uintptr_t base)
{
struct clk_desc *clk = cmu_desc_get_by_base(base);
+
if (!clk) {
return -1;
}
+
struct clk_desc *parent = clk->parent;
+
if (!parent) {
return -2;
}
+
int64_t freq = parent->ops->get(parent->base);
+
return freq;
}
/* fout = 2 * (fref * NF) / (NR * OD) */
int NR, NF, OD;
cmu_pll_t *pll = div;
+
NF = pll->divf + 1;
NR = pll->divr + 1;
OD = 1 << pll->divq;
if (!NR || !OD) {
return -1;
}
+
return 2 * (fref * NF) / (NR * OD);
}
int64_t cmu_pll_div_set(uintptr_t base, void *div)
{
uint32_t raw;
- cmu_pll_t *reg = (void*)&raw;
+ cmu_pll_t *reg = (void *)&raw;
cmu_pll_t *new = div;
int ret;
int64_t cmu_pll_div_get(uintptr_t base, void *div)
{
int ret;
+
ret = reg_read(base, div);
if (ret < 0) {
return ret;
}
+
return 0;
}
return -1;
}
- cmu_pll_t *pll = (void*)div;
+ cmu_pll_t *pll = (void *)div;
int divq; /* [1-7] :: {2, 4, 8, 16, 32, 64, 128} */
int divr; /* [0-63] */
int divf; /* [0-511] */
/* fout = fref / (VAL_CLKDIV + 1) */
cmu_clkch_t *reg = div;
int dd = reg->val_clkdiv + 1;
+
if (!dd || reg->val_clkdiv > VAL_CLKDIV_MAX) {
return -1;
}
+
return fref / dd;
}
int64_t cmu_clkch_div_set(uintptr_t base, void *div)
{
uint32_t raw;
- cmu_clkch_t *reg = (void*)&raw;
+ cmu_clkch_t *reg = (void *)&raw;
cmu_clkch_t *new = div;
int ret;
+
ret = reg_read(base, &raw);
if (ret < 0) {
return ret;
}
+
reg->val_clkdiv = new->val_clkdiv;
ret = reg_write(base, raw);
if (ret < 0) {
return ret;
}
+
return 0;
}
int64_t cmu_clkch_div_get(uintptr_t base, void *div)
{
int ret;
+
ret = reg_read(base, div);
if (ret < 0) {
return ret;
}
+
return 0;
}
div0 = fref / freq - 1;
for (val_clkdiv = div0 - 1; val_clkdiv <= div0 + 1; val_clkdiv++) {
int dd = val_clkdiv + 1;
+
if (!dd || dd < 0 || val_clkdiv > VAL_CLKDIV_MAX) {
continue;
}
/* fout = fref / 2^(DIV_VAL - 1) */
cmu_clkdiv_t *reg = div;
int dd = 1 << (reg->div_val - 1);
+
if (!dd || reg->div_val < 1 || reg->div_val > DIV_VAL_MAX) {
return -1;
}
+
return fref / dd;
}
int64_t cmu_clkdiv_div_set(uintptr_t base, void *div)
{
uint32_t raw;
- cmu_clkdiv_t *reg = (void*)&raw;
+ cmu_clkdiv_t *reg = (void *)&raw;
cmu_clkdiv_t *new = div;
int ret;
+
ret = reg_read(base, &raw);
if (ret < 0) {
return ret;
}
+
reg->div_val = new->div_val;
ret = reg_write(base, raw);
if (ret < 0) {
return ret;
}
+
return 0;
}
int64_t cmu_clkdiv_div_get(uintptr_t base, void *div)
{
int ret;
+
ret = reg_read(base, div);
if (ret < 0) {
return ret;
div0 = cmu_log2(fref / freq) + 1;
for (div_val = div0 - 1; div_val <= div0 + 1; div_val++) {
int dd = 1 << (div_val - 1);
+
if (!dd || div_val < 1 || div_val > DIV_VAL_MAX) {
continue;
}
/* fout = fref / DIV_VAL */
cmu_clkdiv_t *reg = div;
int dd = reg->div_val;
+
if (!dd || reg->div_val > DIV_VAL_MAX) {
return -1;
}
+
return fref / dd;
}
int64_t cmu_clken_div_set(uintptr_t base, void *div)
{
uint32_t raw;
- cmu_clkdiv_t *reg = (void*)&raw;
+ cmu_clkdiv_t *reg = (void *)&raw;
cmu_clkdiv_t *new = div;
int ret;
+
ret = reg_read(base, &raw);
if (ret < 0) {
return ret;
int64_t cmu_clken_div_get(uintptr_t base, void *div)
{
int ret;
+
ret = reg_read(base, div);
if (ret < 0) {
return ret;
div0 = fref / freq;
for (div_val = div0 - 1; div_val <= div0 + 1; div_val++) {
int dd = div_val;
+
if (!dd || dd < 0 || div_val > DIV_VAL_MAX) {
continue;
}
*/
uint32_t raw;
int ret;
+
ret = reg_read(SCP_GPR_BOOT_INFO_STS, &raw);
if (ret < 0) {
return ret;
int64_t freq;
cmu_pll_t div;
int64_t fref = cmu_get_ref(base);
+
if (fref < 0) {
return -1;
}
+
if (cmu_pll_div_get(base, &div)) {
return -1;
}
+
freq = cmu_pll_calc(fref, &div);
return freq;
}
int64_t cmu_pll_set_rate(uintptr_t base, int64_t freq)
{
uint32_t raw;
- cmu_pll_t *reg = (void*)&raw;
+ cmu_pll_t *reg = (void *)&raw;
int ret;
/* 1. SWEN = 0 */
/* 5. set_div */
cmu_pll_t div;
int64_t fref = cmu_get_ref(base);
+
if (fref < 0) {
return -1;
}
+
if (cmu_pll_div_calc(freq, fref, &div) < 0) {
return -1;
}
+
if (cmu_pll_div_set(base, &div)) {
return -1;
}
/* 8. LOCK? */
#ifndef BAIKAL_QEMU
int try = 100;
+
do {
ret = reg_read(base, &raw);
if (ret < 0) {
{
/* SWEN = 0 */
uint32_t raw;
- cmu_pll_t *reg = (void*)&raw;
+ cmu_pll_t *reg = (void *)&raw;
int ret;
+
ret = reg_read(base, &raw);
if (ret < 0) {
return ret;
}
+
reg->swen = 0;
ret = reg_write(base, raw);
if (ret < 0) {
return ret;
}
+
return 0;
}
{
/* SWEN = 1 */
uint32_t raw;
- cmu_pll_t *reg = (void*)&raw;
+ cmu_pll_t *reg = (void *)&raw;
int ret;
+
ret = reg_read(base, &raw);
if (ret < 0) {
return ret;
}
+
reg->swen = 1;
ret = reg_write(base, raw);
if (ret < 0) {
return ret;
}
+
return 0;
}
{
/* return SWEN */
uint32_t raw;
- cmu_pll_t *reg = (void*)&raw;
+ cmu_pll_t *reg = (void *)&raw;
int ret;
ret = reg_read(base, &raw);
{
cmu_pll_t div;
int64_t fref = cmu_get_ref(base);
+
if (fref < 0) {
return -1;
}
+
if (cmu_pll_div_calc(freq, fref, &div) < 0) {
return -1;
}
+
int64_t calc = cmu_pll_calc(fref, &div);
+
return calc;
}
int64_t freq;
cmu_clkch_t div;
int64_t fref = cmu_get_ref(base);
+
if (fref < 0) {
return -1;
}
+
if (cmu_clkch_div_get(base, &div)) {
return -1;
}
int64_t cmu_clkch_set_rate(uintptr_t base, int64_t freq)
{
uint32_t raw;
- cmu_clkch_t *reg = (void*)&raw;
+ cmu_clkch_t *reg = (void *)&raw;
int ret;
/* 1. CLKEN = 0 */
/* 2. wait CLKRDY = 0 */
#ifndef BAIKAL_QEMU
int try = 100;
+
do {
ret = reg_read(base, &raw);
if (ret < 0) {
/* 3. set dividers */
cmu_clkch_t div;
int64_t fref = cmu_get_ref(base);
+
if (fref < 0) {
return -1;
}
+
if (cmu_clkch_div_calc(freq, fref, &div) < 0) {
return -1;
}
+
if (cmu_clkch_div_set(base, &div)) {
return -1;
}
{
/* CLKEN = 0 */
uint32_t raw;
- cmu_clkch_t *reg = (void*)&raw;
+ cmu_clkch_t *reg = (void *)&raw;
int ret;
+
ret = reg_read(base, &raw);
if (ret < 0) {
return ret;
}
+
reg->clk_en = 0;
ret = reg_write(base, raw);
if (ret < 0) {
return ret;
}
+
return 0;
}
{
/* CLKEN = 1 */
uint32_t raw;
- cmu_clkch_t *reg = (void*)&raw;
+ cmu_clkch_t *reg = (void *)&raw;
int ret;
+
ret = reg_read(base, &raw);
if (ret < 0) {
return ret;
}
+
reg->clk_en = 1;
ret = reg_write(base, raw);
if (ret < 0) {
return ret;
}
+
return 0;
}
{
/* return CLKEN */
uint32_t raw;
- cmu_clkch_t *reg = (void*)&raw;
+ cmu_clkch_t *reg = (void *)&raw;
int ret;
+
ret = reg_read(base, &raw);
if (ret < 0) {
return ret;
}
+
return reg->clk_en;
}
{
cmu_clkch_t div;
int64_t fref = cmu_get_ref(base);
+
if (fref < 0) {
return -1;
}
+
if (cmu_clkch_div_calc(freq, fref, &div) < 0) {
return -1;
}
+
int64_t calc = cmu_clkch_calc(fref, &div);
+
return calc;
}
int64_t freq;
cmu_clkdiv_t div;
int64_t fref = cmu_get_ref(base);
+
if (fref < 0) {
return -1;
}
+
if (cmu_clkdiv_div_get(base, &div)) {
return -1;
}
+
freq = cmu_clkdiv_calc(fref, &div);
return freq;
}
int ret;
uint32_t raw;
int64_t fref;
- cmu_clkdiv_t *reg = (void*) &raw;
+ cmu_clkdiv_t *reg = (void *)&raw;
cmu_clkdiv_t cur;
cmu_clkdiv_t new;
#ifndef BAIKAL_QEMU
/* wait */
int try = 1000;
+
do {
ret = reg_read(base, &raw);
if (ret < 0) {
{
/* CLKEN = 0 */
uint32_t raw;
- cmu_clkdiv_t *reg = (void*)&raw;
+ cmu_clkdiv_t *reg = (void *)&raw;
int ret;
+
ret = reg_read(base, &raw);
if (ret < 0) {
return ret;
}
+
reg->clk_en = 0;
ret = reg_write(base, raw);
if (ret < 0) {
return ret;
}
+
return 0;
}
{
/* CLKEN = 1 */
uint32_t raw;
- cmu_clkdiv_t *reg = (void*)&raw;
+ cmu_clkdiv_t *reg = (void *)&raw;
int ret;
+
ret = reg_read(base, &raw);
if (ret < 0) {
return ret;
}
+
reg->clk_en = 1;
ret = reg_write(base, raw);
if (ret < 0) {
return ret;
}
+
return 0;
}
{
/* return CLKEN */
uint32_t raw;
- cmu_clkdiv_t *reg = (void*)&raw;
+ cmu_clkdiv_t *reg = (void *)&raw;
int ret;
ret = reg_read(base, &raw);
{
cmu_clkdiv_t div;
int64_t fref = cmu_get_ref(base);
+
if (fref < 0) {
return -1;
}
+
if (cmu_clkdiv_div_calc(freq, fref, &div) < 0) {
return -1;
}
+
int64_t calc = cmu_clkdiv_calc(fref, &div);
+
return calc;
}
int64_t freq = 0;
cmu_clken_t div;
int64_t fref = cmu_get_ref(base);
+
if (fref < 0) {
return -1;
}
+
if (cmu_clken_div_get(base, &div)) {
return -1;
}
+
freq = cmu_clken_calc(fref, &div);
return freq;
}
int64_t cmu_clken_set_rate(uintptr_t base, int64_t freq)
{
uint32_t raw;
- cmu_clken_t *reg = (void*)&raw;
+ cmu_clken_t *reg = (void *)&raw;
int ret;
/* 1. CLKEN = 0 */
/* 2. set dividers */
cmu_clken_t div;
int64_t fref = cmu_get_ref(base);
+
if (fref < 0) {
return -1;
}
/* 4. wait LOCK */
#ifndef BAIKAL_QEMU
int try;
+
try = 100;
do {
ret = reg_read(base, &raw);
{
/* CLKEN = 0 */
uint32_t raw;
- cmu_clkdiv_t *reg = (void*)&raw;
+ cmu_clkdiv_t *reg = (void *)&raw;
int ret;
+
ret = reg_read(base, &raw);
if (ret < 0) {
return ret;
{
/* CLKEN = 1 */
uint32_t raw;
- cmu_clkdiv_t *reg = (void*)&raw;
+ cmu_clkdiv_t *reg = (void *)&raw;
int ret;
+
ret = reg_read(base, &raw);
if (ret < 0) {
return ret;
/* return CLKEN */
uint32_t raw;
int ret;
+
ret = reg_read(base, &raw);
if (ret < 0) {
return ret;
{
cmu_clken_t div;
int64_t fref = cmu_get_ref(base);
+
if (fref < 0) {
return -1;
}
if (cmu_clken_div_calc(freq, fref, &div) < 0) {
return -1;
}
+
int64_t calc = cmu_clken_calc(fref, &div);
+
return calc;
}
-int64_t baikal_smc_clk_handler(const uint32_t ops,
+int64_t baikal_smc_clk_handler(const uint32_t smc_fid,
const uint64_t base,
const uint64_t freq,
const uint64_t x3,
const uint64_t x4)
{
struct clk_desc *clk = cmu_desc_get_by_base(base);
+ /* Convert SMC FID to SMC64 to support SMC32/SMC64 */
+ const uint32_t local_smc_fid = BIT(30) | smc_fid;
if (!clk) {
return -1;
}
- switch (ops) {
+ switch (local_smc_fid) {
case BAIKAL_SMC_CLK_GET:
return clk->ops->get(base);
case BAIKAL_SMC_CLK_SET:
}
}
-int64_t baikal_smc_gmac_handler(const uint32_t ops,
+int64_t baikal_smc_gmac_handler(const uint32_t smc_fid,
const uint64_t addr,
const uint64_t x2,
const uint64_t x3,
{
uint32_t mask;
uint32_t reg;
+ /* Convert SMC FID to SMC64 to support SMC32/SMC64 */
+ const uint32_t local_smc_fid = BIT(30) | smc_fid;
switch (addr) {
case GMAC0_BASE:
return -1;
}
- switch (ops) {
+ switch (local_smc_fid) {
case BAIKAL_SMC_GMAC_DIV2_ENABLE:
reg_read(SCP_GPR_GMAC_DIV_CTL, ®);
reg |= mask;
SMMUV3_STE_BYPASS(ste, SMMU_STE_MEMATTR_IWB_OWB, SMMU_STE_MTCFG_REPLACE_MEMATTR,
SMMU_STE_ALLOCCFG_RW, SMMU_STE_SHCFG_OUTER, SMMU_STE_NSCFG_NSEC,
SMMU_STE_PRIVCFG_USE_INCOMING, SMMU_STE_INSTCFG_USE_INCOMING);
- memcpy((void *)BAIKAL_SCMM_SMMU_STRTAB_BASE + 10*SMMU_STE_SIZE, (void *)ste, SMMU_STE_SIZE);
+ memcpy((void *)BAIKAL_SCMM_SMMU_STRTAB_BASE + 10 * SMMU_STE_SIZE, (void *)ste, SMMU_STE_SIZE);
ste = BAIKAL_SCMM_SMMU_STRTAB_BASE + SMMU_STE_SIZE;
SMMUV3_STE_BYPASS(ste, 0, SMMU_STE_MTCFG_USE_INCOMING, SMMU_STE_ALLOCCFG_USE_INCOMING,
SMMU_STE_SHCFG_USE_INCOMING, SMMU_STE_NSCFG_USE_INCOMING,
SMMU_STE_PRIVCFG_USE_INCOMING, SMMU_STE_INSTCFG_USE_INCOMING);
- memcpy((void *)BAIKAL_SCMM_SMMU_STRTAB_BASE + 2*SMMU_STE_SIZE, (void *)ste, SMMU_STE_SIZE);
- memcpy((void *)BAIKAL_SCMM_SMMU_STRTAB_BASE + 3*SMMU_STE_SIZE, (void *)ste, SMMU_STE_SIZE);
- memcpy((void *)BAIKAL_SCMM_SMMU_STRTAB_BASE + 4*SMMU_STE_SIZE, (void *)ste, SMMU_STE_SIZE);
- memcpy((void *)BAIKAL_SCMM_SMMU_STRTAB_BASE + 8*SMMU_STE_SIZE, (void *)ste, SMMU_STE_SIZE);
- memcpy((void *)BAIKAL_SCMM_SMMU_STRTAB_BASE + 12*SMMU_STE_SIZE, (void *)ste, SMMU_STE_SIZE);
+ memcpy((void *)BAIKAL_SCMM_SMMU_STRTAB_BASE + 2 * SMMU_STE_SIZE, (void *)ste, SMMU_STE_SIZE);
+ memcpy((void *)BAIKAL_SCMM_SMMU_STRTAB_BASE + 3 * SMMU_STE_SIZE, (void *)ste, SMMU_STE_SIZE);
+ memcpy((void *)BAIKAL_SCMM_SMMU_STRTAB_BASE + 4 * SMMU_STE_SIZE, (void *)ste, SMMU_STE_SIZE);
+ memcpy((void *)BAIKAL_SCMM_SMMU_STRTAB_BASE + 8 * SMMU_STE_SIZE, (void *)ste, SMMU_STE_SIZE);
+ memcpy((void *)BAIKAL_SCMM_SMMU_STRTAB_BASE + 12 * SMMU_STE_SIZE, (void *)ste, SMMU_STE_SIZE);
dsb();
/* Enable SMMU */
- if (smmuv3_enable(SMMU_BASE, true) != 0)
+ if (smmuv3_enable(SMMU_BASE, true) != 0) {
ERROR("SCMM SMMU enable failed.\n");
+ }
}
void bs1000_gmac_init(void)
#define DDR_DEBUG_TEST_MAPPING 0 /* 0 - default; 1 - special debug mapping for 2-rank/2-DIMMs testing */
#define DDR_CTRL_DFI_INIT_TIMEOUT 50
#define DDR_CTRL_DONE_TIMEOUT 10 /* small umctl2 timeout for different tasks */
-#define DDR_PHY_TWRDATA_DELAY 16 /* see PHY PUB DataBook, Table5-3 (p.91); (t_ctrl_delay+(6+4)+TxDqsDly)/2 */
+#define DDR_PHY_TWRDATA_DELAY 16 /* see PHY PUB DataBook, Table5-3 (p.91); (t_ctrl_delay + (6 + 4) + TxDqsDly) / 2 */
#define MSTR (0x0)
#define STAT (0x4)
BS_DDRC_WRITE(port, PWRCTL, reg_val);
}
-
void umctl2_exit_SR(int port)
{
uint32_t reg_val;
/* delay 1 us */
udelay(1);
}
+
static void ctrl_set_sar(int port)
{
- /* program SAR registers (UMCTL2_SARMINSIZE=256MB) */
+ /* program SAR registers (UMCTL2_SARMINSIZE = 256 MiB) */
/* configure a SARBASE0 reg. */
- BS_DDRC_WRITE(port, SARBASE0, 8); /* region 0: 2GB base address */
+ BS_DDRC_WRITE(port, SARBASE0, 8); /* region 0: 2 GiB base address */
/* configure a SARSIZE0 reg. */
- BS_DDRC_WRITE(port, SARSIZE0, 8 - 1); /* region 0: 2GB size */
+ BS_DDRC_WRITE(port, SARSIZE0, 8 - 1); /* region 0: 2 GiB size */
/* configure a SARBASE1 reg. */
- BS_DDRC_WRITE(port, SARBASE1, 34 * 4); /* region 1: 34GB base address */
+ BS_DDRC_WRITE(port, SARBASE1, 34 * 4); /* region 1: 34 GiB base address */
/* configure a SARSIZE1 reg. */
- BS_DDRC_WRITE(port, SARSIZE1, 30 * 4 - 1); /* region 1: 30GB size */
+ BS_DDRC_WRITE(port, SARSIZE1, 30 * 4 - 1); /* region 1: 30 GiB size */
/* configure a SARBASE2 reg. */
- BS_DDRC_WRITE(port, SARBASE2, 544 * 4); /* region 2: 544GB base address */
+ BS_DDRC_WRITE(port, SARBASE2, 544 * 4); /* region 2: 544 GiB base address */
/* configure a SARSIZE2 reg. */
- BS_DDRC_WRITE(port, SARSIZE2, 64 * 4 - 1); /* region 2: 64GB size (note: it's a max value for SARSIZE) */
+ BS_DDRC_WRITE(port, SARSIZE2, 64 * 4 - 1); /* region 2: 64 GiB size (note: it's a max value for SARSIZE) */
/* configure a SARBASE3 reg. */
- /* note: we can't set 8TB region, SARSIZE have a max value 64GB */
- BS_DDRC_WRITE(port, SARBASE3, 608 * 4); /* region 3: 544+64GB base address */
+ /* note: we can't set 8 TiB region, SARSIZE have a max value 64 GiB */
+ BS_DDRC_WRITE(port, SARBASE3, 608 * 4); /* region 3: 544 + 64 GiB base address */
/* configure a SARSIZE3 reg. */
- BS_DDRC_WRITE(port, SARSIZE3, 64 * 4 - 1); /* region 3: 64GB size (note: it's a max value for SARSIZE) */
+ BS_DDRC_WRITE(port, SARSIZE3, 64 * 4 - 1); /* region 3: 64 GiB size (note: it's a max value for SARSIZE) */
}
/** @brief increments HIF address and strips address by mask in DRAMconfig
/* note: shift input address by -3 for APP_ADDR => HIF_ADDR conversion */
uint64_t strip_addr_mask = data->addr_strip_bit >> 3;
- /* note: be careful for max HIF_ADDR value 33 bit
- * (HIF_ADDR width is 34 bits - 128GB address space is maximum!)
+ /*
+ * note: be careful for max HIF_ADDR value 33 bit
+ * (HIF_ADDR width is 34 bits - 128 GiB address space is maximum)
*/
if (hif_addr > 33) {
/* max value = 33, but gets incremented once more later */
/* COL2 ->HIF A2 */
/* BG0 ->HIF A3 */
uint32_t hif_addr = 4; /* next empty HIF address */
+
map2_val &= ~GENMASK(12, 8);
map2_val |= GENMASK(12, 8) & ((hif_addr - 3) << 8); /* map COL3->HIF */
hif_addr = hif_addr_increment(hif_addr, data);
/* configure a DFITMG1 reg. */
regval = 2; /* see PHY PUB DataBook, Table5-12 (p.97) */
regval |= (2 << 8); /* see PHY PUB DataBook, Table5-12 (p.97) */
- /* see PHY PUB DataBook, Table5-3 (p.91) << 16); (t_ctrl_delay+(6+4)+TxDqsDly)/2 */
+ /* see PHY PUB DataBook, Table5-3 (p.91) << 16); (t_ctrl_delay + (6 + 4) + TxDqsDly) / 2 */
regval |= GENMASK(20, 16) & ((((DDR_PHY_TWRDATA_DELAY + 1) / 2 + 1)) << 16);
/* add one additional clk for RDIMM (see F0RC0F settings: 1 clk delay for parity by default) */
regval |= ((data->registered_dimm ? 1 : 0) << 24);
regval &= ~GENMASK(31, 28); /* note: have to set non-zero value for CAL mode (we don't use CAL mode) */
const uint32_t dfitmg1_val = regval;
+
BS_DDRC_WRITE(port, DFITMG1, regval);
/* configure a DFITMG2 reg. */
BS_DDRC_WRITE(port, DFITMG2, regval);
/* configure a DRAMTMG0 reg. */
- unsigned t_ras_min = data->timing_2t ? (data->tRAS + 1) / 2 : data->tRAS / 2;
+ unsigned int t_ras_min = data->timing_2t ? (data->tRAS + 1) / 2 : data->tRAS / 2;
+
regval = GENMASK(5, 0) & t_ras_min;
regval |= GENMASK(14, 8) & (((data->tRASmax / 1024 - 1) / 2) << 8);
regval |= GENMASK(21, 16) & (((data->tFAW + 1) / 2) << 16);
- unsigned wr2pre = (data->WL + 4 + data->tWR);
+ unsigned int wr2pre = (data->WL + 4 + data->tWR);
+
regval |= GENMASK(30, 24) & ((data->timing_2t ? (wr2pre + 1) / 2 : wr2pre / 2) << 24);
BS_DDRC_WRITE(port, DRAMTMG0, regval);
/* configure a DRAMTMG1 reg. */
regval = GENMASK(6, 0) & ((data->tRC + 1) / 2);
- unsigned rd2pre = ((data->AL + data->tRTP) > (data->RL + 4 - data->tRP)) ?
+ unsigned int rd2pre = ((data->AL + data->tRTP) > (data->RL + 4 - data->tRP)) ?
(data->AL + data->tRTP) : (data->RL + 4 - data->tRP);
regval |= GENMASK(13, 8) & ((data->timing_2t ? (rd2pre + 1) / 2 : rd2pre / 2) << 8);
regval |= GENMASK(20, 16) & (((data->tXP + data->PL + 1) / 2) << 16);
BS_DDRC_WRITE(port, DRAMTMG1, regval);
/* configure a DRAMTMG2 reg. */
- unsigned wr2rd = data->CWL + data->PL + 4 + data->tWTR_L; /* CRC off */
+ unsigned int wr2rd = data->CWL + data->PL + 4 + data->tWTR_L; /* CRC off */
+
regval = GENMASK(5, 0) & ((wr2rd + 1) / 2);
/* see umctl2 Databook for "rd2wr" description */
regval |= GENMASK(13, 8) & (((data->RL + 4 + 1 + (data->wr_preamble_2CK ? 2 : 1) - data->WL + 1) / 2) << 8);
BS_DDRC_WRITE(port, DRAMTMG2, regval);
/* configure a DRAMTMG3 reg. */
- regval = GENMASK(9, 0) & ((data->tMOD + data->PL + 1 + data->registered_dimm) / 2);
- regval |= GENMASK(17, 12) & (((data->tMOD + data->PL + 1) / 2) << 12);
+ regval = GENMASK(9, 0) & (DIV_ROUND_UP_2EVAL(data->tMOD + data->PL, 2) + !!data->registered_dimm);
+ regval |= GENMASK(17, 12) & (DIV_ROUND_UP_2EVAL(data->tMOD + data->PL, 2) << 12); /* tMRD_PAR */
BS_DDRC_WRITE(port, DRAMTMG3, regval);
/* configure a DRAMTMG4 reg. */
/* program ODT timings */
/* configure a ODTCFG reg. */
- unsigned dfi_t_cmd_lat = GENMASK(4, 0) & (dfitmg1_val >> 28);
- int rd_odt_delay = data->CL - data->CWL - (data->rd_preamble_2CK ? 2 : 1) + \
+ unsigned int dfi_t_cmd_lat = GENMASK(4, 0) & (dfitmg1_val >> 28);
+ int rd_odt_delay = data->CL - data->CWL - (data->rd_preamble_2CK ? 2 : 1) +
(data->wr_preamble_2CK ? 2 : 1) + dfi_t_cmd_lat;
if (rd_odt_delay < 0) {
rd_odt_delay = 0;
BS_DDRC_WRITE(port, ODTCFG, regval); /* cons. using wr_preamble */
/* configure a ODTMAP reg. */
- if (data->dimms == 1 ) {
+ if (data->dimms == 1) {
/* ODT signal mapping: single DIMM */
if (data->ranks == 1) {
regval = 0x00000201; /* single DIMM, 1-rank ODT mask */
/* issue dfi_init_start signal (for DRAM init by PHY) (uMCTL2 DataBook p.1567 Table6-8, step 16)
* WARNING: this is last step of time critical section for RDIMM
- * (avoid any delay from PHY training complete to dfi_init_start) */
+ * (avoid any delay from PHY training complete to dfi_init_start)
+ */
BS_DDRC_WRITE(port, DFIMISC, (1 << 6) | (1 << 5));
/* disable Quazi-Dynamic registers programming (uMCTL2 DataBook p.1567 Table6-8, step 17) */
BS_DDRC_WRITE(port, DFIMISC, (1 << 6));
/* (uMCTL2 DataBook p.1567 Table6-8, step 21) */
- unsigned RWSL; /* Read to Write System Latency (as PHY training result) */
+ unsigned int RWSL; /* Read to Write System Latency (as PHY training result) */
+
if (data->dimms == 1 && data->ranks == 1) {
RWSL = data->trn_res.rd2wr_CDD_sr; /* single rank constrain */
} else {
RWSL = data->trn_res.rd2wr_CDD_mr; /* multi-ranks constrain */
}
- unsigned rd2wr = data->RL + 4 + 1 + (data->wr_preamble_2CK ? 2 : 1) - data->WL + RWSL; /* see umctl2 Databook for "rd2wr" description */
+ unsigned int rd2wr = data->RL + 4 + 1 + (data->wr_preamble_2CK ? 2 : 1) - data->WL + RWSL; /* see umctl2 Databook for "rd2wr" description */
+
+ unsigned int WWSL; /* Write to Write System Latency (as PHY training result) */
- unsigned WWSL; /* Write to Write System Latency (as PHY training result) */
if (data->dimms == 1 && data->ranks == 1) {
WWSL = 0; /* single rank constrain (see PHY PUB databook "Rank-to-Rank Spacing") */
} else {
}
/* increase wr2rd delay by PHY training CDD_WW: see PUB databook 10.2.1.2.2 */
- unsigned wr2rd;
+ unsigned int wr2rd;
+
if (data->crc_on && MR5_DM) {
wr2rd = data->CWL + data->PL + 4 + data->tWTR_L_CRC_DM + WWSL; /* CRC_&_DM on */
} else {
}
uint32_t val = BS_DDRC_READ(port, DRAMTMG2);
+
val &= ~GENMASK(13, 8);
val |= GENMASK(13, 8) & (((rd2wr + 1) / 2) << 8);
val &= ~GENMASK(5, 0);
BS_DDRC_WRITE(port, DRAMTMG2, val);
/* tphy_wrcsgap=4 (see phy pub databook) */
- unsigned wrcsgap = 4 + (data->wr_preamble_2CK ? 1 : 0) + data->crc_on + WWSL;
+ unsigned int wrcsgap = 4 + (data->wr_preamble_2CK ? 1 : 0) + data->crc_on + WWSL;
+
+ unsigned int RRSL; /* Read to Read System Latency (as PHY training result) */
- unsigned RRSL; /* Read to Read System Latency (as PHY training result) */
if (data->dimms == 1 && data->ranks == 1) {
RRSL = 0; /* single rank constrain (see PHY PUB databook "Rank-to-Rank Spacing") */
} else {
RRSL = data->trn_res.rd2rd_CDD_mr; /* multi-ranks constrain */
}
- unsigned rdcsgap = 2 + (data->rd_preamble_2CK ? 1 : 0) + RRSL; /* tphy_rdcsgap=2 (see phy pub databook) */
- unsigned rdcsgap_odt = 5 + (data->rd_preamble_2CK ? 2 : 1) - 2 + RRSL; /* (rd_odt_hold=(5+RD_PREAMBLE)) - BL/2 */
+ unsigned int rdcsgap = 2 + (data->rd_preamble_2CK ? 1 : 0) + RRSL; /* tphy_rdcsgap = 2 (see phy pub databook) */
+ unsigned int rdcsgap_odt = 5 + (data->rd_preamble_2CK ? 2 : 1) - 2 + RRSL; /* (rd_odt_hold = (5 + RD_PREAMBLE)) - BL / 2 */
+
if (rdcsgap_odt > rdcsgap) {
rdcsgap = rdcsgap_odt;
}
BS_DDRC_WRITE(port, RANKCTL, val);
/* update DFITMG1 (DFI timing) */
- unsigned txdqs_dly = data->trn_res.TxDqsDlyMax;
+ unsigned int txdqs_dly = data->trn_res.TxDqsDlyMax;
+
val = BS_DDRC_READ(port, DFITMG1);
- /* see PHY PUB DataBook, Table5-3 (p.91) << 16); (t_ctrl_delay+(6+4)+TxDqsDly)/2 */
+ /* see PHY PUB DataBook, Table5-3 (p.91) << 16); (t_ctrl_delay + (6 + 4) + TxDqsDly) / 2 */
val &= ~GENMASK(20, 16);
- val |= GENMASK(20, 16) & (((DDR_PHY_TWRDATA_DELAY + txdqs_dly + 1) / 2 + 1));
+ val |= GENMASK(20, 16) & (((DDR_PHY_TWRDATA_DELAY + txdqs_dly + 1) / 2 + 1) << 16);
BS_DDRC_WRITE(port, DFITMG1, val);
/* set dfi_init_complete_en to 1 (uMCTL2 DataBook p.1567 Table6-8, step 22) */
void ddr_io_lcru_write(int port, uint32_t offs, int value)
{
if (port < 3) {
- mmio_write_32(DDR0_CMU0_BASE + \
+ mmio_write_32(DDR0_CMU0_BASE +
DDR_CTRL_BASE_OFF * port + offs, value);
} else {
- mmio_write_32(DDR3_CMU0_BASE + \
+ mmio_write_32(DDR3_CMU0_BASE +
DDR_CTRL_BASE_OFF * (port % 3) + offs, value);
}
}
void ddr_io_gpr_write(int port, uint32_t offs, int value)
{
if (port < 3) {
- mmio_write_32(DDR0_GPR_BASE + \
+ mmio_write_32(DDR0_GPR_BASE +
DDR_CTRL_BASE_OFF * port + offs, value);
} else {
- mmio_write_32(DDR3_GPR_BASE + \
+ mmio_write_32(DDR3_GPR_BASE +
DDR_CTRL_BASE_OFF * (port % 3) + offs, value);
}
}
void ddr_io_phy_write(int port, uint32_t offs, int value)
{
if (port < 3) {
- mmio_write_32(DDR0_PHY_BASE + \
+ mmio_write_32(DDR0_PHY_BASE +
DDR_CTRL_BASE_OFF * port + offs, value);
} else {
- mmio_write_32(DDR3_PHY_BASE + \
+ mmio_write_32(DDR3_PHY_BASE +
DDR_CTRL_BASE_OFF * (port % 3) + offs, value);
}
}
-
void ddr_io_ctrl_write(int port, uint32_t offs, int value)
{
if (port < 3) {
- mmio_write_32(DDR0_CTRL_BASE + \
+ mmio_write_32(DDR0_CTRL_BASE +
DDR_CTRL_BASE_OFF * port + offs, value);
} else {
- mmio_write_32(DDR3_CTRL_BASE + \
+ mmio_write_32(DDR3_CTRL_BASE +
DDR_CTRL_BASE_OFF * (port % 3) + offs, value);
}
}
uint32_t ddr_io_lcru_read(int port, uint32_t offs)
{
if (port < 3) {
- return mmio_read_32(DDR0_CMU0_BASE + \
+ return mmio_read_32(DDR0_CMU0_BASE +
DDR_CTRL_BASE_OFF * port + offs);
} else {
- return mmio_read_32(DDR3_CMU0_BASE + \
+ return mmio_read_32(DDR3_CMU0_BASE +
DDR_CTRL_BASE_OFF * (port % 3) + offs);
}
}
uint32_t ddr_io_gpr_read(int port, uint32_t offs)
{
if (port < 3) {
- return mmio_read_32(DDR0_GPR_BASE + \
+ return mmio_read_32(DDR0_GPR_BASE +
DDR_CTRL_BASE_OFF * port + offs);
} else {
- return mmio_read_32(DDR3_GPR_BASE + \
+ return mmio_read_32(DDR3_GPR_BASE +
DDR_CTRL_BASE_OFF * (port % 3) + offs);
}
}
uint32_t ddr_io_phy_read(int port, uint32_t offs)
{
if (port < 3) {
- return mmio_read_32(DDR0_PHY_BASE + \
+ return mmio_read_32(DDR0_PHY_BASE +
DDR_CTRL_BASE_OFF * port + offs);
} else {
- return mmio_read_32(DDR3_PHY_BASE + \
+ return mmio_read_32(DDR3_PHY_BASE +
DDR_CTRL_BASE_OFF * (port % 3) + offs);
}
}
-
uint32_t ddr_io_ctrl_read(int port, uint32_t offs)
{
if (port < 3) {
- return mmio_read_32(DDR0_CTRL_BASE + \
+ return mmio_read_32(DDR0_CTRL_BASE +
DDR_CTRL_BASE_OFF * port + offs);
} else {
- return mmio_read_32(DDR3_CTRL_BASE + \
+ return mmio_read_32(DDR3_CTRL_BASE +
DDR_CTRL_BASE_OFF * (port % 3) + offs);
}
}
#define BAIKAL_TFW_RDIMM_OFFS BAIKAL_TFW_UDIMM_SIZE
int ddr_init_ecc_memory(int port);
-int ddr_odt_configuration(const unsigned port,
+int ddr_odt_configuration(const unsigned int port,
struct ddr_configuration *const data);
uint8_t firmware_container[55036];
bytes[2] = 0;
} else if (channels == 6) {
int capacity_gb = spd_get_baseconf_dimm_capacity(spd) / 1024 / 1024 / 1024;
+
switch (capacity_gb) {
case 1:
- /* 1GB DRAM size per SN-F addressing */
+ /* 1 GiB DRAM size per SN-F addressing */
bytes[0] = 28;
bytes[1] = 31;
bytes[2] = 35;
break;
case 2:
- /* 2GB DRAM size per SN-F addressing */
+ /* 2 GiB DRAM size per SN-F addressing */
bytes[0] = 28;
bytes[1] = 32;
bytes[2] = 33;
break;
case 4:
- /* 4GB DRAM size per SN-F addressing */
+ /* 4 GiB DRAM size per SN-F addressing */
bytes[0] = 28;
bytes[1] = 33;
bytes[2] = 34;
break;
case 8:
- /* 8GB DRAM size per SN-F addressing */
+ /* 8 GiB DRAM size per SN-F addressing */
bytes[0] = 33;
bytes[1] = 34;
bytes[2] = 39;
break;
case 16:
- /* 16GB DRAM size per SN-F addressing */
+ /* 16 GiB DRAM size per SN-F addressing */
bytes[0] = 28;
bytes[1] = 36;
bytes[2] = 39;
break;
case 32:
- /* 32GB DRAM size per SN-F addressing */
+ /* 32 GiB DRAM size per SN-F addressing */
bytes[0] = 28;
bytes[1] = 36;
bytes[2] = 37;
break;
case 64:
- /* 64GB DRAM size per SN-F addressing */
+ /* 64 GiB DRAM size per SN-F addressing */
bytes[0] = 28;
bytes[1] = 37;
bytes[2] = 38;
break;
case 128:
- /* 128GB DRAM size per SN-F addressing */
+ /* 128 GiB DRAM size per SN-F addressing */
bytes[0] = 37;
bytes[1] = 38;
bytes[2] = 43;
break;
default:
- ERROR("Can't configure CMN"
- " - incorrect DRAM size=%dGB\n", capacity_gb);
+ ERROR("Can't configure CMN - incorrect DRAM size = %d GiB\n", capacity_gb);
return -1;
}
} else {
for (int dimm_idx = 0; dimm_idx < 6; ++dimm_idx) {
if (conf & (1 << (dimm_idx * 2))) {
int dual_channel_mode = (conf & (1 << (dimm_idx * 2 + 1))) ? 1 : 0;
+
spd_content = (struct ddr4_spd_eeprom *)baikal_dimm_spd_get(dimm_idx * 2);
ret = ddr_port_init(dimm_idx, spd_content, channels, dual_channel_mode);
if (ret) {
uint32_t dbus_half; /* this is user defined flag to turn on/off half DDR data bus mode */
uint32_t par_on; /* this is user defined flag to turn on/off CA PARITY support */
uint32_t crc_on; /* this is user defined flag to turn on/off CRC support */
- uint32_t phy_eql; /* this is user defined flag to turn on/off PHY equalization
- (0-off; 1-DFE(rx); 2-FFE(tx); 3-(DFE+FFE)) */
+ uint32_t phy_eql; /* this is user defined flag to turn on/off PHY equalization:
+ * (0-off; 1-DFE(rx); 2-FFE(tx); 3-(DFE+FFE))
+ */
uint32_t clock_mhz; /* DRAM clock (MHz) (for example 1200 MHz for DDR4-2400) */
uint32_t dimms;
uint32_t tRAS; /* ACT to PRE command period */
uint32_t tRC; /* ACT to ACT or REF command period */
uint32_t tRCD; /* ACT to internal read or write delay time */
- uint32_t tWTR_S; /* Write to Read time for different bank
- group */
+ uint32_t tWTR_S; /* Write to Read time for different bank group */
uint32_t tWTR_L; /* Write to Read time for same bank group */
- uint32_t tRRD_S; /* ACTIVATE to ACTIVATE Command delay to
- different bank group */
- uint32_t tRRD_L; /* ACTIVATE to ACTIVATE Command delay to
- same bank group */
+ uint32_t tRRD_S; /* ACTIVATE to ACTIVATE Command delay to different bank group */
+ uint32_t tRRD_L; /* ACTIVATE to ACTIVATE Command delay to same bank group */
uint32_t tFAW; /* Four Activate Window delay time */
uint32_t tRFC1; /* Refresh Cycle time in 1x mode */
uint32_t tRFC4; /* Refresh Cycle time in 4x mode */
uint32_t tREFI; /* Periodic Refresh Interval */
uint32_t tRTP; /* Read to Precharge for autoprecharge */
- uint32_t tWR_CRC_DM; /* Write Recovery time when CRC and DM
- are enabled */
- uint32_t tWTR_S_CRC_DM; /* Write to Read time for different bank group
- with both CRC and DM enabled */
- uint32_t tWTR_L_CRC_DM; /* Write to Read time for same bank group
- with both CRC and DM enabled */
+ uint32_t tWR_CRC_DM; /* Write Recovery time when CRC and DM are enabled */
+ uint32_t tWTR_S_CRC_DM; /* Write to Read time for different bank group with both CRC and DM enabled */
+ uint32_t tWTR_L_CRC_DM; /* Write to Read time for same bank group with both CRC and DM enabled */
uint32_t tDLLK; /* DLL Locking time */
uint32_t tXP; /* Exit Power Down with DLL on */
uint32_t tMOD; /* Mode Register Set time */
- uint32_t tCCD_S; /* CAS_n to CAS_n command Delay for different
- bank group */
- uint32_t tCCD_L; /* CAS_n to CAS_n command Delay for same bank
- group */
- uint32_t tCKSRX; /* Valid Clock Requirement before Self Refresh
- Exit or Power-Down Exit or Reset Exit */
+ uint32_t tCCD_S; /* CAS_n to CAS_n command Delay for different bank group */
+ uint32_t tCCD_L; /* CAS_n to CAS_n command Delay for same bank group */
+ uint32_t tCKSRX; /* Valid Clock Requirement before Self Refresh Exit or Power-Down Exit or Reset Exit */
uint32_t tCKE; /* CKE minimum pulse width */
uint32_t tMRD; /* MRS command cycle time */
- uint32_t tMRD_PDA; /* Mode Register Set command cycle time
- in PDA mode */
+ uint32_t tMRD_PDA; /* Mode Register Set command cycle time in PDA mode */
uint32_t tRASmax; /* Maximum ACT to PRE command period */
uint32_t tMPX_S; /* CS setup time to CKE */
uint32_t tMPX_LH; /* CS_n Low hold time to CKE rising edge */
uint32_t tCPDED; /* Command pass disable delay */
- uint32_t tXS; /* Exit Self Refresh to commands not requiring
- a locked DLL */
+ uint32_t tXS; /* Exit Self Refresh to commands not requiring a locked DLL */
uint32_t tXS_FAST; /* Exit Self Refresh to ZQCL,ZQCS and MRS */
- uint32_t tXS_ABORT; /* SRX to commands not requiring a locked DLL
- in Self Refresh ABORT */
- uint32_t tXSDLL; /* Exit Self Refresh to tXSDLL commands
- requiring a locked DLL */
- uint32_t tXMP; /* Exit MPSM to commands not requiring
- a locked DLL */
- uint32_t tXMPDLL; /* Exit MPSM to commands requiring
- a locked DLL */
+ uint32_t tXS_ABORT; /* SRX to commands not requiring a locked DLL in Self Refresh ABORT */
+ uint32_t tXSDLL; /* Exit Self Refresh to tXSDLL commands requiring a locked DLL */
+ uint32_t tXMP; /* Exit MPSM to commands not requiring a locked DLL */
+ uint32_t tXMPDLL; /* Exit MPSM to commands requiring a locked DLL */
uint32_t tCKMPE; /* Valid clock requirement after MPSM entry */
uint32_t CL; /* CAS Latency */
uint32_t CWL; /* CAS Write Latency */
uint32_t CWL_ALT; /* CWL alternative (when write preamble is 2CK - special PHY training setting) */
- uint32_t WCL; /* Write Command Latency when CRC and DM
- are both enabled */
+ uint32_t WCL; /* Write Command Latency when CRC and DM are both enabled */
uint32_t PL; /* C/A Parity Latency */
uint32_t AL; /* Additive Latency */
uint32_t RL; /* Read Latency */
uint16_t set_mr1(uint32_t odi, uint32_t rtt_nom)
{
uint16_t mr1_reg = 0;
+
mr1_reg |= (MR1_Q_OFF & 0x1) << 12;
mr1_reg |= (MR1_TDQS & 0x1) << 11;
mr1_reg |= (rtt_nom & 0x7) << 8;
uint16_t set_mr3(uint32_t wcl, uint32_t fg_rfsh)
{
uint16_t mr3_reg = 0;
+
mr3_reg |= (MR3_MPR_RD_FORMAT & 0x3) << 11;
/* A10:A9 WCL_CRC_DM: Write CMD Latency when CRC and DM are enabled */
mr3_reg |= ((wcl - 4) & 0x3) << 9;
uint16_t set_mr4(uint32_t wr_pre_2ck, uint32_t rd_pre_2ck)
{
uint16_t mr4_reg = 0;
+
mr4_reg |= (MR4_HPPR & 0x1) << 13;
mr4_reg |= (!!wr_pre_2ck) << 12;
mr4_reg |= (!!rd_pre_2ck) << 11;
uint32_t tmp;
data->dimms = 1;
-#ifdef BAIKAL_DUAL_CHANNEL_MODE
- if (spd_content.dual_channel[port] == 'y') {
- data->dimms = 2;
- }
-#endif
/*
* The SPD spec has not the burst length byte, but DDR4 spec has
* nature BL8 and BC4, BL8 -bit3, BC4 -bit2.
data->tCK = 1000000 / data->clock_mhz;
}
#endif
-
-#ifdef BAIKAL_DUAL_CHANNEL_MODE
-#ifdef BAIKAL_DBM20
- if (spd_content.dual_channel[port] == 'y') {
- data->clock_mhz = 800; /* 1600 MHz in double rate */
- data->tCK = 1000000 / data->clock_mhz;
- }
-#endif
-#endif /* BAIKAL_DUAL_CHANNEL_MODE */
-
/* Compute CAS Latency (CL) */
uint64_t lat_mask = ((uint64_t)spd->caslat_b1 << 7) |
((uint64_t)spd->caslat_b2 << 15) |
(uint32_t)((((uint64_t)(x) * 1000) / data->tCK + 974) / 1000)
#define CLOCK_NS(x) CLOCK_PS((uint64_t)(x) * 1000)
-
uint16_t set_mr0(const uint32_t cl, uint32_t wr);
uint16_t set_mr1(uint32_t odi, uint32_t rtt_nom);
uint16_t set_mr2(uint32_t cwl, uint32_t rtt_wr, uint32_t ddr_crc);
{
/* Enable ADB400 */
uint32_t val = 0x17 << 11;
+
ddr_io_lcru_write(port, DDRLCRU_GPR_OFFS + ADBFNCCR, val);
/* deassert all resets (Deasserting DDR SS Core and AXI Resets) */
/* send command to LCP */
uint32_t mode;
enum cmd_type_t type = CMD_DDRSPEEDBIN_SET;
+
switch (clock_mhz) {
case DDRSB_1600:
mode = CMU_DDR4_1600;
{ 0, 2, 7, 4, 102, 30, 80, 34 }
};
-int ddr_odt_configuration(const unsigned port,
- struct ddr_configuration *const data)
+int ddr_odt_configuration(const unsigned int port,
+ struct ddr_configuration *const data)
{
- unsigned odt_set;
+ unsigned int odt_set;
if (data->dimms == 1) {
if (data->ranks == 1) {
uint8_t mod_thickness;
/* 130 (Unbuffered) Reference Raw Card Used */
uint8_t ref_raw_card;
- /* 131 (Unbuffered) Address Mapping from
- Edge Connector to DRAM */
+ /* 131 (Unbuffered) Address Mapping from Edge Connector to DRAM */
uint8_t addr_mapping;
/* 132~253 (Unbuffered) Reserved */
uint8_t res_132[254 - 132];
void phyinit_calcMb(void *mb, struct ddr_configuration *data, int training_2d)
{
struct pmu_smb_ddr4_t *pmu_smb_p = (struct pmu_smb_ddr4_t *)mb;
+
memset(pmu_smb_p, 0, sizeof(struct pmu_smb_ddr4_t));
pmu_smb_p->Pstate = 0x0;
/* If Share2DVrefResult[x] = 1, pstate x will use the per-lane VrefDAC0/1 CSRs which can be trained by 2d training. */
/* If 2D has not run yet, VrefDAC0/1 will default to pstate 0's 1D phyVref messageBlock setting. */
- /* If Share2DVrefResult[x] = 0, pstate x will use the per-phy VrefInGlobal CSR,
- * which are set to pstate x's 1D phyVref messageBlock setting. */
+ /*
+ * If Share2DVrefResult[x] = 0, pstate x will use the per-phy VrefInGlobal CSR,
+ * which are set to pstate x's 1D phyVref messageBlock setting.
+ */
pmu_smb_p->Share2DVrefResult = 0x1; /* Bitmap that controls which vref generator the phy will use per pstate */;
if (training_2d) {
if (data->registered_dimm) {
/* Only content of the Control Word is required to be programmed. */
- uint16_t tmp = 0;
+ uint16_t tmp = 0;
/* F0RC0D */
if (data->mirrored_dimm) {
pmu_smb_p->F0RC0D_D0 = 0x4 | (pmu_smb_p->CsPresentD0) ? 0x8 : 0x0;
#include "ddr_phy_tmp_regs.h"
#define NUMBER_ANIB 12
-/* Enable Write DQS Extension feature of PHY.
- * See "DesignWare Cores LPDDR4 MultiPHY, WDQS Extension Application Note" */
+/*
+ * Enable Write DQS Extension feature of PHY.
+ * See "DesignWare Cores LPDDR4 MultiPHY, WDQS Extension Application Note"
+ */
#define WDQSEXT 0
#define SNPS_UMCTLOPT 0
#define EXTCALRES_VAL 0
void phyinit_C_PhyConfig(int port, struct ddr_configuration *data)
{
- /* Program TxSlewRate:
+ /*
+ * Program TxSlewRate:
* - TxSlewRate::TxPreDrvMode is dependent on DramType.
* - TxSlewRate::TxPreP and TxSlewRate::TxPreN are technology-specific
* User should consult the "Output Slew Rate" section of HSpice Model App Note
- * in specific technology for recommended settings */
+ * in specific technology for recommended settings
+ */
const int TxPreP = 0xf; /* Default to 0xf (max). Optimal setting is technology specific. */
const int TxPreN = 0xf; /* Default to 0xf (max). Optimal setting is technology specific. */
const int TxPreDrvMode = 0x2;
- const int TxSlewRate = (TxPreDrvMode << csr_TxPreDrvMode_LSB) | \
+ const int TxSlewRate = (TxPreDrvMode << csr_TxPreDrvMode_LSB) |
(TxPreN << csr_TxPreN_LSB) | (TxPreP << csr_TxPreP_LSB);
- unsigned byte;
+ unsigned int byte;
+
for (byte = 0; byte < 9; byte++) {
- for (unsigned lane = 0; lane <= 1; lane++) {
- unsigned b_addr = lane << 8;
- unsigned c_addr = byte << 12;
- DDRPHY_WRITE_REG16(port, (tDBYTE | c_addr | b_addr | csr_TxSlewRate_ADDR), TxSlewRate);
+ for (unsigned int lane = 0; lane <= 1; lane++) {
+ unsigned int b_addr = lane << 8;
+ unsigned int c_addr = byte << 12;
+
+ DDRPHY_WRITE_REG16(port, (tDBYTE | c_addr | b_addr | csr_TxSlewRate_ADDR), TxSlewRate);
}
}
- /* Program ATxSlewRate:
+ /*
+ * Program ATxSlewRate:
* - ATxSlewRate::ATxPreDrvMode is dependent on DramType and whether the ACX4 instance is used for AC or CK
* - ATxSlewRate::ATxPreP and ATxSlewRate::TxPreN are technology-specific
* User should consult the "Output Slew Rate" section of HSpice Model App Note
- * in specific technology for recommended settings */
- unsigned anib;
+ * in specific technology for recommended settings
+ */
+ unsigned int anib;
+
for (anib = 0; anib < NUMBER_ANIB; anib++) {
/* # of ANIBs CK ANIB Instance */
/* ACX8 ANIB 1 */
/* ACX13 ANIB 4,5 */
int ATxPreDrvMode;
- if (anib == 0x4 || anib == 0x5 ) {
+
+ if (anib == 0x4 || anib == 0x5) {
/* CK ANIB instance */
ATxPreDrvMode = 0x0;
} else {
const int ATxPreP = 0xf; /* Default to 0xf (max). Optimal setting is technology specific. */
const int ATxPreN = 0xf; /* Default to 0xf (max). Optimal setting is technology specific. */
- const int ATxSlewRate = (ATxPreDrvMode << csr_ATxPreDrvMode_LSB) | \
+ const int ATxSlewRate = (ATxPreDrvMode << csr_ATxPreDrvMode_LSB) |
(ATxPreN << csr_ATxPreN_LSB) | (ATxPreP << csr_ATxPreP_LSB);
- unsigned c_addr = anib << 12;
- DDRPHY_WRITE_REG16(port,(tANIB | c_addr | csr_ATxSlewRate_ADDR), ATxSlewRate);
+ unsigned int c_addr = anib << 12;
+
+ DDRPHY_WRITE_REG16(port, (tANIB | c_addr | csr_ATxSlewRate_ADDR), ATxSlewRate);
}
if (data->registered_dimm) {
/* Program PllCtrl2: Calculate PLL controls per p-state from Frequency */
int PllCtrl2;
+
if (data->clock_mhz / 2 < 235) {
PllCtrl2 = 0x7;
} else if (data->clock_mhz / 2 < 313) {
DDRPHY_WRITE_REG16(port, (tMASTER | csr_PllCtrl2_ADDR), PllCtrl2);
- /* Program ARdPtrInitVal:
+ /*
+ * Program ARdPtrInitVal:
* - The values programmed here assume ideal properties of DfiClk and Pclk including:
* - DfiClk skew
* - DfiClk jitter
* - For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-6
* - PLL Enabled mode:
* - For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-6
- * - For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 0-6 */
+ * - For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 0-6
+ */
int ARdPtrInitVal;
+
if (data->clock_mhz >= 933) {
ARdPtrInitVal = 0x2;
} else {
DDRPHY_WRITE_REG16(port, (tMASTER | csr_ARdPtrInitVal_ADDR), ARdPtrInitVal);
- /* Program DbyteDllModeCntrl:
+ /*
+ * Program DbyteDllModeCntrl:
* - DllRxPreambleMode
* Program DqsPreambleControl:
* - Fields:
* - PositionDfeInit
* - LP4TglTwoTckTxDqsPre
* - LP4PostambleExt
- * - LP4SttcPreBridgeRxEn */
- int TwoTckRxDqsPre = (!!data->rd_preamble_2CK);
+ * - LP4SttcPreBridgeRxEn
+ */
+ int TwoTckRxDqsPre = !!data->rd_preamble_2CK;
const int LP4SttcPreBridgeRxEn = 0x0;
const int DllRxPreambleMode = 0x1;
- int TwoTckTxDqsPre = (!!data->wr_preamble_2CK);
+ int TwoTckTxDqsPre = !!data->wr_preamble_2CK;
const int LP4TglTwoTckTxDqsPre = 0x0;
const int PositionDfeInit = 0x2;
const int LP4PostambleExt = 0x0;
const int WDQSEXTENSION = 0;
- int DqsPreambleControl = (WDQSEXTENSION << csr_WDQSEXTENSION_LSB) | \
- (LP4SttcPreBridgeRxEn << csr_LP4SttcPreBridgeRxEn_LSB) | \
- (LP4PostambleExt << csr_LP4PostambleExt_LSB) | \
- (LP4TglTwoTckTxDqsPre << csr_LP4TglTwoTckTxDqsPre_LSB) | \
- (PositionDfeInit << csr_PositionDfeInit_LSB) | \
- (TwoTckTxDqsPre << csr_TwoTckTxDqsPre_LSB) | \
+ int DqsPreambleControl = (WDQSEXTENSION << csr_WDQSEXTENSION_LSB) |
+ (LP4SttcPreBridgeRxEn << csr_LP4SttcPreBridgeRxEn_LSB) |
+ (LP4PostambleExt << csr_LP4PostambleExt_LSB) |
+ (LP4TglTwoTckTxDqsPre << csr_LP4TglTwoTckTxDqsPre_LSB) |
+ (PositionDfeInit << csr_PositionDfeInit_LSB) |
+ (TwoTckTxDqsPre << csr_TwoTckTxDqsPre_LSB) |
(TwoTckRxDqsPre << csr_TwoTckRxDqsPre_LSB);
DDRPHY_WRITE_REG16(port, (tMASTER | csr_DqsPreambleControl_ADDR), DqsPreambleControl);
int DbyteDllModeCntrl = DllRxPreambleMode << csr_DllRxPreambleMode_LSB;
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_DbyteDllModeCntrl_ADDR), DbyteDllModeCntrl);
const int DllGainIV = 0x1;
DDRPHY_WRITE_REG16(port, (tMASTER | csr_DllLockParam_ADDR), DllLockParam);
DDRPHY_WRITE_REG16(port, (tMASTER | csr_DllGainCtl_ADDR), DllGainCtl);
- /* Program ProcOdtTimeCtl:
+ /*
+ * Program ProcOdtTimeCtl:
* - POdtStartDelay[3:2]
- * - POdtTailWidth[1:0] */
+ * - POdtTailWidth[1:0]
+ */
int ProcOdtTimeCtl;
if (WDQSEXT) {
/* Memclk Freq > 1200MHz */
} else {
if (TwoTckRxDqsPre == 1) {
- ProcOdtTimeCtl = 0x3;/* POdtStartDelay = 0x0, POdtTailWidth = 0x3 */
+ ProcOdtTimeCtl = 0x3; /* POdtStartDelay = 0x0, POdtTailWidth = 0x3 */
} else {
- ProcOdtTimeCtl = 0x7;/* POdtStartDelay = 0x1, POdtTailWidth = 0x3 */
+ ProcOdtTimeCtl = 0x7; /* POdtStartDelay = 0x1, POdtTailWidth = 0x3 */
}
}
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_ProcOdtTimeCtl_ADDR), ProcOdtTimeCtl);
- /* Program TxOdtDrvStren:
+ /*
+ * Program TxOdtDrvStren:
* - ODTStrenP_px[5:0]
- * - ODTStrenN_px[11:6] */
+ * - ODTStrenN_px[11:6]
+ */
int ODTStrenP = phyinit_mapDrvStren(data->PHY_ODT, ODTStrenP_T);
int ODTStrenN = phyinit_mapDrvStren(data->PHY_ODT, ODTStrenN_T);
int TxOdtDrvStren = (ODTStrenN << csr_ODTStrenN_LSB) | ODTStrenP;
+
for (byte = 0; byte < 9; byte++) {
- for (unsigned lane = 0; lane <= 1; lane++) {
- unsigned b_addr = lane << 8;
- unsigned c_addr = byte << 12;
+ for (unsigned int lane = 0; lane <= 1; lane++) {
+ unsigned int b_addr = lane << 8;
+ unsigned int c_addr = byte << 12;
+
DDRPHY_WRITE_REG16(port, (tDBYTE | c_addr | b_addr | csr_TxOdtDrvStren_ADDR), TxOdtDrvStren);
}
}
- /* Program TxImpedanceCtrl1:
+ /*
+ * Program TxImpedanceCtrl1:
* - DrvStrenFSDqP[5:0]
- * - DrvStrenFSDqN[11:6] */
+ * - DrvStrenFSDqN[11:6]
+ */
int DrvStrenFSDqP = phyinit_mapDrvStren(data->PHY_ODI, DrvStrenFSDqP_T);
int DrvStrenFSDqN = phyinit_mapDrvStren(data->PHY_ODI, DrvStrenFSDqN_T);
int TxImpedanceCtrl1 = (DrvStrenFSDqN << csr_DrvStrenFSDqN_LSB) | (DrvStrenFSDqP << csr_DrvStrenFSDqP_LSB);
+
for (byte = 0; byte < 9; byte++) {
- for (unsigned lane = 0; lane <= 1; lane++) {
- unsigned b_addr = lane << 8;
- unsigned c_addr = byte << 12;
- DDRPHY_WRITE_REG16(port, \
- (tDBYTE | c_addr | b_addr | csr_TxImpedanceCtrl1_ADDR), \
+ for (unsigned int lane = 0; lane <= 1; lane++) {
+ unsigned int b_addr = lane << 8;
+ unsigned int c_addr = byte << 12;
+
+ DDRPHY_WRITE_REG16(port,
+ (tDBYTE | c_addr | b_addr | csr_TxImpedanceCtrl1_ADDR),
TxImpedanceCtrl1);
}
}
- /* Program ATxImpedance:
- * - ADrvStrenP[4:0]
- * - ADrvStrenN[9:5] */
+ /*
+ * Program ATxImpedance:
+ * - ADrvStrenP[4:0]
+ * - ADrvStrenN[9:5]
+ */
int ATxImpedance_config = 20;
for (anib = 0; anib < NUMBER_ANIB; anib++) {
const int ADrvStrenP = phyinit_mapDrvStren(ATxImpedance_config, ADrvStrenP_T);
const int ADrvStrenN = phyinit_mapDrvStren(ATxImpedance_config, ADrvStrenN_T);
const int ATxImpedance = (ADrvStrenN << csr_ADrvStrenN_LSB) | (ADrvStrenP << csr_ADrvStrenP_LSB);
- unsigned c_addr = anib << 12;
+ unsigned int c_addr = anib << 12;
+
DDRPHY_WRITE_REG16(port, (tANIB | c_addr | csr_ATxImpedance_ADDR), ATxImpedance);
}
/* Program DfiMode */
int DfiMode = 0x1; /* DFI1 does not physically exists */
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_DfiMode_ADDR), DfiMode);
- /* Program DfiCAMode:
+ /*
+ * Program DfiCAMode:
* - DfiLp3CAMode
* - DfiD4CAMode
* - DfiLp4CAMode
- * - DfiD4AltCAMode */
+ * - DfiD4AltCAMode
+ */
int DfiCAMode = 2; /* DDR4 */
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_DfiCAMode_ADDR), DfiCAMode);
- /* Program CalDrvStr0:
+ /*
+ * Program CalDrvStr0:
* - CalDrvStrPd50[3:0]
- * - CalDrvStrPu50[7:4] */
+ * - CalDrvStrPu50[7:4]
+ */
uint16_t CalDrvStrPu50 = EXTCALRES_VAL;
uint16_t CalDrvStrPd50 = CalDrvStrPu50;
uint16_t CalDrvStr0 = (CalDrvStrPu50 << csr_CalDrvStrPu50_LSB) | CalDrvStrPd50;
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_CalDrvStr0_ADDR), CalDrvStr0);
/* Program CalUclkInfo: Impedance calibration CLK Counter. */
/* number of DfiClk cycles per 1us - round up */
uint16_t CalUClkTicksPer1uS = (data->clock_mhz + 1) / 2;
+
if (CalUClkTicksPer1uS < 24) {
CalUClkTicksPer1uS = 24; /* Minimum value of CalUClkTicksPer1uS = 24 */
}
int CalInterval = 0x9;
int CalOnce = 0x0;
int CalRate = (CalOnce << csr_CalOnce_LSB) | (CalInterval << csr_CalInterval_LSB);
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_CalRate_ADDR), CalRate);
/* Program VrefInGlobal:
* - MajorModeDbyte
* - ExtVrefRange
* - DfeCtrl
- * - GainCurrAdj */
+ * - GainCurrAdj
+ */
int MajorModeDbyte = 3; /* DDR4 */
const int SelAnalogVref = 1; /* Use Global VREF from Master */
uint8_t GlobalVrefInSel = 0x4;
/* check range1 first. Only use range0 if customer input maxes out range1 */
uint8_t GlobalVrefInDAC = (uint8_t)((vref_percentVddq / 500) + 1); /* Min value is 1 */
+
if (GlobalVrefInDAC > 127) {
GlobalVrefInDAC = (uint8_t)((vref_percentVddq - 34500) / 500);
if (GlobalVrefInDAC < 1) {
}
int VrefInGlobal = (GlobalVrefInDAC << csr_GlobalVrefInDAC_LSB) | GlobalVrefInSel;
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_VrefInGlobal_ADDR), VrefInGlobal);
- int DqDqsRcvCntrl = (GainCurrAdj_defval << csr_GainCurrAdj_LSB) | \
- (MajorModeDbyte << csr_MajorModeDbyte_LSB) | \
- (DfeCtrl_defval << csr_DfeCtrl_LSB) | \
- (ExtVrefRange_defval << csr_ExtVrefRange_LSB) | \
+ int DqDqsRcvCntrl = (GainCurrAdj_defval << csr_GainCurrAdj_LSB) |
+ (MajorModeDbyte << csr_MajorModeDbyte_LSB) |
+ (DfeCtrl_defval << csr_DfeCtrl_LSB) |
+ (ExtVrefRange_defval << csr_ExtVrefRange_LSB) |
(SelAnalogVref << csr_SelAnalogVref_LSB);
for (byte = 0; byte < 9; byte++) {
- for (unsigned lane = 0; lane <= 1; lane++) {
- unsigned b_addr = lane << 8;
- unsigned c_addr = byte << 12;
- DDRPHY_WRITE_REG16(port, \
- (tDBYTE | c_addr | b_addr | csr_DqDqsRcvCntrl_ADDR), \
+ for (unsigned int lane = 0; lane <= 1; lane++) {
+ unsigned int b_addr = lane << 8;
+ unsigned int c_addr = byte << 12;
+
+ DDRPHY_WRITE_REG16(port,
+ (tDBYTE | c_addr | b_addr | csr_DqDqsRcvCntrl_ADDR),
DqDqsRcvCntrl);
}
}
- /* Program MemAlertControl and MemAlertControl2:
+ /*
+ * Program MemAlertControl and MemAlertControl2:
* - Fields:
* - MALERTVrefLevel
* - MALERTPuStren
* - MALERTPuEn
* - MALERTRxEn
* - MALERTSyncBypass
- * - MALERTDisableVal */
+ * - MALERTDisableVal
+ */
+
/* MemAlert applies to DDR4(all DIMM) or DDR3(RDIMM) only */
const int MALERTPuEn = 1;
const int MALERTRxEn = 1;
const int MALERTDisableVal_defval = 1;
int MALERTVrefLevel = 0x29;
- int MemAlertControl = (MALERTDisableVal_defval << 14) | \
- (MALERTRxEn << 13) | (MALERTPuEn << 12) | \
+ int MemAlertControl = (MALERTDisableVal_defval << 14) |
+ (MALERTRxEn << 13) | (MALERTPuEn << 12) |
(MALERTPuStren << 8) | MALERTVrefLevel;
DDRPHY_WRITE_REG16(port, (tMASTER | csr_MemAlertControl_ADDR), MemAlertControl);
int MALERTSyncBypass = 0x0;
int MemAlertControl2 = (MALERTSyncBypass << csr_MALERTSyncBypass_LSB);
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_MemAlertControl2_ADDR), MemAlertControl2);
/* Program DfiFreqRatio */
int DfiFreqRatio = 1; /* set 1 for 1:2 DFI clock */
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_DfiFreqRatio_ADDR), DfiFreqRatio);
- /* Program TristateModeCA based on DramType and 2T Timing
+ /*
+ * Program TristateModeCA based on DramType and 2T Timing
* - Fields:
* - CkDisVal
* - DisDynAdrTri
- * - DDR2TMode */
+ * - DDR2TMode
+ */
+
/* CkDisVal depends on DramType */
int CkDisVal_def = 1;
int DisDynAdrTri = 0x0;
int DDR2TMode = data->timing_2t;
- int TristateModeCA = (CkDisVal_def << csr_CkDisVal_LSB) | \
- (DDR2TMode << csr_DDR2TMode_LSB) | \
+ int TristateModeCA = (CkDisVal_def << csr_CkDisVal_LSB) |
+ (DDR2TMode << csr_DDR2TMode_LSB) |
(DisDynAdrTri << csr_DisDynAdrTri_LSB);
DDRPHY_WRITE_REG16(port, (tMASTER | csr_TristateModeCA_ADDR), TristateModeCA);
/* Program DfiXlat based on Pll Bypass Input */
uint16_t pllbypass_dat = 0;
+
pllbypass_dat |= 0x0 << (0);
for (uint16_t loopVector = 0; loopVector < 8; loopVector++) {
- if (loopVector == 0 ) {
+ if (loopVector == 0) {
/* Relock DfiFreq = 00,01,02,03) Use StartVec 5 (pll_enabled) or StartVec 6 (pll_bypassed) */
uint16_t dfifreqxlat_dat = pllbypass_dat + 0x5555;
+
DDRPHY_WRITE_REG16(port, (tMASTER | (csr_DfiFreqXlat0_ADDR + loopVector)), dfifreqxlat_dat);
} else if (loopVector == 7) {
/* LP3-entry DfiFreq = 1F */
DDRPHY_WRITE_REG16(port, (tMASTER | (csr_DfiFreqXlat0_ADDR + loopVector)), 0xf000);
} else {
- /* everything else = skip retrain (could also map to 0000 since retrain code is excluded,
- * but this is cleaner) */
+ /*
+ * Everything else = skip retrain (could also map to 0000 since retrain code is excluded,
+ * but this is cleaner)
+ */
DDRPHY_WRITE_REG16(port, (tMASTER | (csr_DfiFreqXlat0_ADDR + loopVector)), 0x5555);
}
}
- /* Program DqDqsRcvCntrl1 (Receiver Powerdown) and DbyteMiscMode
+ /*
+ * Program DqDqsRcvCntrl1 (Receiver Powerdown) and DbyteMiscMode
* - see function dwc_ddrphy_phyinit_IsDbyteDisabled() to determine
* which DBytes are turned off completely based on PHY configuration.
* - Fields:
* - DByteDisable
* - PowerDownRcvr
* - PowerDownRcvrDqs
- * - RxPadStandbyEn */
+ * - RxPadStandbyEn
+ */
/* Implements Section 1.3 of Pub Databook */
for (int d = 0; d < 9; d++) /* for each dbyte */ {
if (d == 8 && (!data->ecc_on)) {
int c_addr = d * c1;
uint16_t regData = 0x1 << csr_DByteDisable_LSB;
+
DDRPHY_WRITE_REG16(port, (c_addr | tDBYTE | csr_DbyteMiscMode_ADDR), regData);
- unsigned regData1 = (0x1ff << csr_PowerDownRcvr_LSB | \
- 0x1 << csr_PowerDownRcvrDqs_LSB | \
+ unsigned int regData1 = (0x1ff << csr_PowerDownRcvr_LSB |
+ 0x1 << csr_PowerDownRcvrDqs_LSB |
0x1 << csr_RxPadStandbyEn_LSB);
+
DDRPHY_WRITE_REG16(port, (c_addr | tDBYTE | csr_DqDqsRcvCntrl1_ADDR), regData1);
} else {
/* disable RDBI lane if not used. */
int mr5_rdbi_off = 1;
+
if (((data->pocket.MR5 >> 12) & 0x1)) {
mr5_rdbi_off = 0;
}
- if ((data->device_width != 4 ) && mr5_rdbi_off) {
+
+ if ((data->device_width != 4) && mr5_rdbi_off) {
/* turn off Rx of DBI lane */
- unsigned regData2 = (0x100 << csr_PowerDownRcvr_LSB | csr_RxPadStandbyEn_MASK);
+ unsigned int regData2 = (0x100 << csr_PowerDownRcvr_LSB | csr_RxPadStandbyEn_MASK);
int c_addr = d * c1;
+
DDRPHY_WRITE_REG16(port, (c_addr | tDBYTE | csr_DqDqsRcvCntrl1_ADDR), regData2);
}
}
}
- /* Program DqDqsRcvCntrl1 (Receiver Powerdown) and DbyteMiscMode
+ /*
+ * Program DqDqsRcvCntrl1 (Receiver Powerdown) and DbyteMiscMode
* - Fields:
* - X4TG
* - MasterX4Config
- * note: PHY does not support mixed dram device data width */
+ * note: PHY does not support mixed dram device data width
+ */
int X4TG = 0;
+
if (data->device_width == 4) {
X4TG = 0xf;
}
+
int MasterX4Config = X4TG << csr_X4TG_LSB;
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_MasterX4Config_ADDR), MasterX4Config);
/* Program DMIPinPresent based on DramType and Read-DBI enable
* - Fields:
- * - RdDbiEnabled */
+ * - RdDbiEnabled
+ */
/* For DDR4, Read DBI is enabled in MR5-A12 */
int DMIPinPresent = (data->pocket.MR5 >> 12) & 0x1;
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_DMIPinPresent_ADDR), DMIPinPresent);
/* note: This feature is BETA and untested. Future PhyInit version will fully enable this feature. */
- uint16_t Acx4AnibDis= 0x0;
+ uint16_t Acx4AnibDis = 0x0;
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_Acx4AnibDis_ADDR), Acx4AnibDis);
}
/* Enable PHY interrupts */
uint16_t int_enable = (1 << csr_PhyTrngCmpltEn_LSB) | (1 << csr_PhyInitCmpltEn_LSB) | (1 << csr_PhyTrngFailEn_LSB);
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_PhyInterruptEnable_ADDR), int_enable);
reg = DDRPHY_READ_REG16(port, (tMASTER | csr_PhyInterruptEnable_ADDR));
* -# Wait for the training firmware to complete by following the procedure in
* "uCtrl Initialization and Mailbox Messaging" implemented in
* dwc_ddrphy_phyinit_userCustom_G_waitFwDone() function.
- * -# Halt the microcontroller. */
+ * -# Halt the microcontroller.
+ */
int phyinit_G_ExecFW(int port)
{
/* 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and */
/* 2. Begin execution of the training firmware by setting the MicroReset CSR to 4\'b0000. */
DDRPHY_WRITE_REG16(port, (tAPBONLY | csr_MicroReset_ADDR), 0x0);
- /* 3. Wait for the training firmware to complete by following the procedure in
- uCtrl Initialization and Mailbox Messaging" */
+ /*
+ * 3. Wait for the training firmware to complete by following the procedure in
+ * uCtrl Initialization and Mailbox Messaging"
+ */
int ret = phyinit_G_WaitFWDone(port);
/* 4. Halt the microcontroller." */
}
/* select PMU iccm image */
- unsigned image_offs = 0;
- unsigned image_size = 0;
+ unsigned int image_offs = 0;
+ unsigned int image_size = 0;
+
if (data->registered_dimm) {
if (training_2d) {
image_offs = RDIMM_PMUTRAIN_2D_IMEM_OFFS;
}
}
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
- * This allows the memory controller unrestricted access to the configuration CSRs. */
+ /*
+ * 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+ * This allows the memory controller unrestricted access to the configuration CSRs.
+ */
DDRPHY_WRITE_REG16(port, (tAPBONLY | csr_MicroContMuxSel_ADDR), 0x0);
- const uint16_t *msg = (uint16_t*)(firmware_container + image_offs);
- unsigned index;
+ const uint16_t *msg = (uint16_t *)(firmware_container + image_offs);
+ unsigned int index;
+
for (index = 0; index < image_size / sizeof(uint16_t); index++) {
DDRPHY_WRITE_REG16(port, (DDRPHY_PMU_ICCM_ADDR + index), msg[index]);
}
DDRPHY_WRITE_REG16(port, (DDRPHY_PMU_ICCM_ADDR + index), 0x0);
}
- /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
- * This allows the firmware unrestricted access to the configuration CSRs. */
+ /*
+ * 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+ * This allows the firmware unrestricted access to the configuration CSRs.
+ */
DDRPHY_WRITE_REG16(port, (tAPBONLY | csr_MicroContMuxSel_ADDR), 0x1);
}
* This function performs the following tasks:
* -# Load the firmware DMEM segment to initialize the data structures from the
* DMEM incv file provided in the training firmware package.
- * -# Write the Firmware Message Block with the required contents detailing the training parameters. */
-void phyinit_F_LoadDMEM(int port, struct ddr_configuration *data, const void* mb, int training_2d)
+ * -# Write the Firmware Message Block with the required contents detailing the training parameters.
+ */
+void phyinit_F_LoadDMEM(int port, struct ddr_configuration *data, const void *mb, int training_2d)
{
/* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. */
/* This allows the memory controller unrestricted access to the configuration CSRs. */
int dccm_index = 0;
/* upload PMU message block */
- unsigned msg_block_size = sizeof(struct pmu_smb_ddr4_t);
-
+ unsigned int msg_block_size = sizeof(struct pmu_smb_ddr4_t);
uint16_t *msg = (uint16_t *)mb;
+
for (; dccm_index < msg_block_size / sizeof(uint16_t); dccm_index++) {
DDRPHY_WRITE_REG16(port, (DDRPHY_PMU_DCCM_ADDR + dccm_index), msg[dccm_index]);
}
/* upload PMU dccm image (tail without message block) */
- unsigned dccm_image_offs = 0;
- unsigned dccm_image_size = 0;
+ unsigned int dccm_image_offs = 0;
+ unsigned int dccm_image_size = 0;
+
if (data->registered_dimm) {
if (training_2d) {
dccm_image_offs = RDIMM_PMUTRAIN_2D_DMEM_OFFS;
dccm_index++;
}
- /* 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
- * This allows the firmware unrestricted access to the configuration CSRs. */
+ /*
+ * 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+ * This allows the firmware unrestricted access to the configuration CSRs.
+ */
DDRPHY_WRITE_REG16(port, (tAPBONLY | csr_MicroContMuxSel_ADDR), 0x1);
}
phyinit_LoadPieProdCode_udimm(port);
}
- /* Registers: Seq0BDLY0, Seq0BDLY1, Seq0BDLY2, Seq0BDLY3
- * - Program PIE instruction delays */
+ /*
+ * Registers: Seq0BDLY0, Seq0BDLY1, Seq0BDLY2, Seq0BDLY3
+ * - Program PIE instruction delays
+ */
+
/* Need delays for 0.5us, 1us, 10us, and 25us. */
uint16_t psCount[4];
const int delayScale = 1;
int DfiFrq = data->clock_mhz / 2;
+
psCount[0] = DfiFrq * delayScale / 2 / 4;
int LowFreqOpt = 0;
+
if (data->registered_dimm) {
- if (data->clock_mhz < 400 ) {
+ if (data->clock_mhz < 400) {
LowFreqOpt = 7;
- } else if (data->clock_mhz < 533 ) {
+ } else if (data->clock_mhz < 533) {
LowFreqOpt = 14;
}
} else {
- if (data->clock_mhz < 400 ) {
+ if (data->clock_mhz < 400) {
LowFreqOpt = 3;
- } else if (data->clock_mhz < 533 ) {
+ } else if (data->clock_mhz < 533) {
LowFreqOpt = 11;
}
}
psCount[2] = DfiFrq * delayScale * 10 / 4;
int dllLock;
+
if (DfiFrq > 267) {
dllLock = 176;
} else if (DfiFrq <= 267 && DfiFrq > 200) {
DDRPHY_WRITE_REG16(port, (tMASTER | csr_Seq0BDLY2_ADDR), psCount[2]);
DDRPHY_WRITE_REG16(port, (tMASTER | csr_Seq0BDLY3_ADDR), psCount[3]);
- /* Registers: Seq0BDisableFlag0 Seq0BDisableFlag1 Seq0BDisableFlag2
- * Seq0BDisableFlag3 Seq0BDisableFlag4 Seq0BDisableFlag5
- * - Program PIE Instruction Disable Flags */
+ /*
+ * Registers: Seq0BDisableFlag0 Seq0BDisableFlag1 Seq0BDisableFlag2
+ * Seq0BDisableFlag3 Seq0BDisableFlag4 Seq0BDisableFlag5
+ * - Program PIE Instruction Disable Flags
+ */
DDRPHY_WRITE_REG16(port, (tINITENG | csr_Seq0BDisableFlag0_ADDR), 0x0000);
DDRPHY_WRITE_REG16(port, (tINITENG | csr_Seq0BDisableFlag1_ADDR), 0x0173);
DDRPHY_WRITE_REG16(port, (tINITENG | csr_Seq0BDisableFlag2_ADDR), 0x0060);
DDRPHY_WRITE_REG16(port, (tINITENG | csr_Seq0BDisableFlag7_ADDR), 0x6152);
if (data->registered_dimm) {
- /* Registers AcsmPlayback*x*
- * Program Address/Command Sequence Engine (ACSM) registers with required instructions for retraining algorithm. */
- int acsmplayback[2][4] = {{0,0,0,0}, {0,0,0,0}};
+ /* Registers AcsmPlayback*x* */
+
+ /* Program Address/Command Sequence Engine (ACSM) registers with required instructions for retraining algorithm. */
+ int acsmplayback[2][4] = {{0, 0, 0, 0}, {0, 0, 0, 0}};
int NumVec = 0;
/* DIMM Operating Speed */
uint32_t F0RC0A = 0x0a0 | (0xf & data->pocket.F0RC0A_D0); /* use the RCD register value for 1D training. */
+
acsmplayback[0][NumVec] = 0x3ff & F0RC0A;
acsmplayback[1][NumVec] = (0x1c00 & F0RC0A) >> 10;
NumVec += 1;
/* Fine Granularity RDIMM Operating Speed */
uint32_t F0RC3x = 0x300 | (0xff & data->pocket.F0RC3x_D0);
+
acsmplayback[0][NumVec] = 0x3ff & F0RC3x;
acsmplayback[1][NumVec] = (0x1c00 & F0RC3x) >> 10;
NumVec += 1;
/* F0RC5x: CW Destination Selection & Write/Read Additional QxODT[1:0] Signal High */
uint32_t F0RC5x = 0x500 | (0xff & SNPS_UMCTL_F0RC5x);
+
acsmplayback[0][NumVec] = 0x3ff & F0RC5x;
acsmplayback[1][NumVec] = (0x1c00 & F0RC5x) >> 10;
NumVec += 1;
/* Program Training Hardware Registers for mission mode retraining and DRAM drift compensation algorithm. */
/* Register: AcsmCtrl13 Fields: AcsmCkeEnb */
uint16_t regData = (0xf << csr_AcsmCkeEnb_LSB);
+
DDRPHY_WRITE_REG16(port, (tACSM | csr_AcsmCtrl13_ADDR), regData);
/* Register: AcsmCtrl0 Fields: AcsmParMode, Acsm2TMode */
- DDRPHY_WRITE_REG16(port, (tACSM | csr_AcsmCtrl0_ADDR), csr_AcsmParMode_MASK | csr_Acsm2TMode_MASK );
+ DDRPHY_WRITE_REG16(port, (tACSM | csr_AcsmCtrl0_ADDR), csr_AcsmParMode_MASK | csr_Acsm2TMode_MASK);
}
/* - Register: CalZap
* - Prepare the calibration controller for mission mode.
- * Turn on calibration and hold idle until dfi_init_start is asserted sequence is triggered. */
+ * Turn on calibration and hold idle until dfi_init_start is asserted sequence is triggered.
+ */
DDRPHY_WRITE_REG16(port, (tMASTER | csr_CalZap_ADDR), 0x1);
/* - Register: CalRate
* - Fields:
* - CalRun
* - CalOnce
- * - CalInterval */
+ * - CalInterval
+ */
int CalInterval = 0x9;
int CalOnce = 0x0;
int CalRate = (0x1 << csr_CalRun_LSB) | (CalOnce << csr_CalOnce_LSB) | (CalInterval << csr_CalInterval_LSB);
+
DDRPHY_WRITE_REG16(port, (tMASTER | csr_CalRate_ADDR), CalRate);
- /* At the end of this function, PHY Clk gating register UcclkHclkEnables is
- * set for mission mode. Additionally APB access is Isolated by setting MicroContMuxSel. */
+ /*
+ * At the end of this function, PHY Clk gating register UcclkHclkEnables is
+ * set for mission mode. Additionally APB access is Isolated by setting MicroContMuxSel.
+ */
+
/* Disabling Ucclk (PMU) and Hclk (training hardware) */
DDRPHY_WRITE_REG16(port, (tDRTUB | csr_UcclkHclkEnables_ADDR), 0x0);
/* Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. */
/* (C) Initialize PHY Configuration */
phyinit_C_PhyConfig(port, data);
- /* Switches between supported phyinit training sequences refer to
- * "Alternative PHY Training sequence" document for further details. */
+ /*
+ * Switches between supported phyinit training sequences refer to
+ * "Alternative PHY Training sequence" document for further details.
+ */
+
/* 0x0 | Minimizes number of Imem/Dmem loads (default) */
/* 0x1 | High frequency P1/P2/P3 support (DDR4/LP4 only) */
#if (PHYINIT_SEQUENCENUM == 0)
/* Note: this routine implies other items such as DfiFreqRatio, DfiCtlClk are also set properly. */
/* (F) Write the Message Block parameters for the training firmware */
- /* uint8_t __attribute__((aligned (sizeof(u32)))) msg_block[MSG_BLOCK_1D_SIZE]; */
struct pmu_smb_ddr4_t msg_block = {0};
+
phyinit_calcMb((void *)&msg_block, data, false);
phyinit_F_LoadDMEM(port, data, &msg_block, false);
phyinit_D_LoadIMEM(port, data, true); /* 2D image */
/* 2D-F, cont. Write the Message Block parameters for the training firmware */
- /* u8 __attribute__((aligned (sizeof(u32)))) msg_block[MSG_BLOCK_2D_SIZE]; */
phyinit_calcMb((void *)&msg_block, data, true); /* pstate=0 */
phyinit_F_LoadDMEM(port, data, &msg_block, true);
/* (F) Write the Message Block parameters for the training firmware */
struct pmu_smb_ddr4_t msg_block = {0};
- phyinit_calcMb((void*) &msg_block, data, false);
+
+ phyinit_calcMb((void *)&msg_block, data, false);
phyinit_F_LoadDMEM(port, data, &msg_block, false);
/* 2D-F, cont. Write the Message Block parameters for the training firmware */
msg_block = {0};
- phyinit_calcMb((void*) &msg_block, data, true); /* pstate=0 */
+ phyinit_calcMb((void *)&msg_block, data, true); /* pstate=0 */
phyinit_F_LoadDMEM(port, data, &msg_block, true);
void phyinit_E_setDfiClk(int port);
void phyinit_calcMb(void *mb, struct ddr_configuration *data, int training_2d);
void phyinit_D_LoadIMEM(int port, struct ddr_configuration *data, int training_2d);
-void phyinit_F_LoadDMEM(int port, struct ddr_configuration *data, const void* mb, int training_2d);
+void phyinit_F_LoadDMEM(int port, struct ddr_configuration *data, const void *mb, int training_2d);
void phyinit_I_LoadPIE(int port, struct ddr_configuration *data);
-
int phyinit_H_readMsgBlock(int port, struct ddr_configuration *data);
#endif /* DDR_PHY_MAIN_H */
static int get_mail_u16(int port, uint16_t *mail, int timeout_us)
{
uint64_t timeout;
+
for (timeout = timeout_init_us(timeout_us);;) {
if (!(DDRPHY_READ_REG16(port, (tAPBONLY | csr_UctShadowRegs_ADDR)) & csr_UctWriteProtShadow_MASK)) {
break;
static int get_mail_u32(int port, uint32_t *mail, int timeout_us)
{
uint64_t timeout;
+
for (timeout = timeout_init_us(timeout_us);;) {
if (!(DDRPHY_READ_REG16(port, (tAPBONLY | csr_UctShadowRegs_ADDR)) & csr_UctWriteProtShadow_MASK)) {
break;
return 1;
}
}
+
uint16_t low = DDRPHY_READ_REG16(port, (tAPBONLY | csr_UctWriteOnlyShadow_ADDR));
uint16_t high = DDRPHY_READ_REG16(port, (tAPBONLY | csr_UctDatWriteOnlyShadow_ADDR));
+
*mail = (high << 16) | low;
DDRPHY_WRITE_REG16(port, (tAPBONLY | csr_DctWriteProt_ADDR), 0);
/* read stream arguments */
int argc = 0;
int argc_input = *str_index & 0xffff;
+
for (int i = 0; i < argc_input; i++) {
uint32_t arg;
+
if (get_mail_u32(port, &arg, DDRPHY_MAIL_TIMEOUT) != 0) {
break;
}
{
/* seek for message in info table */
int idx = -1;
- for (int i = 0; i < sizeof(pmu_msg_list) / sizeof(pmu_msg_list[0]); i++) {
+
+ for (int i = 0; i < ARRAY_SIZE(pmu_msg_list); i++) {
if (pmu_msg_list[i].id == major) {
idx = i;
break;
}
}
if (idx >= 0) {
- /* WARNING: avoid any messaging with EOFRW_PASS! (RDIMM time critcal section) */
+ /* WARNING: avoid any messaging with EOFRW_PASS (RDIMM time critcal section) */
if (idx != PMU_MSG_EOFRW_PASS) {
INFO("pmu: ");
printf("%s\n", pmu_msg_list[idx].info);
int phyinit_G_WaitFWDone(int port)
{
uint16_t major = -1;
+
do {
/* process pmu mailbox */
if (get_mail_u16(port, &major, DDRPHY_TRAINING_TIMEOUT)) {
uint32_t str_index;
uint32_t str_arg[DDRPHY_MAIL_STRARG_MAX];
int argc = get_pmu_streaming_message(port, &str_index, str_arg);
+
if (argc >= 0) {
print_pmu_streaming_message(str_index, str_arg, argc);
} else {
int phyinit_mapDrvStren(int DrvStren_ohm, enum drv_stren_t TargetCSR)
{
int Stren_setting;
+
if ((TargetCSR == DrvStrenFSDqP_T) || (TargetCSR == DrvStrenFSDqN_T)) {
if (DrvStren_ohm == 0) {
Stren_setting = 0x00; /* High-impedance */
}
} else if (TargetCSR == ODTStrenP_T) {
/* DDR4 & LPDDR3 - P is non-zero */
- if (DrvStren_ohm == 0) { Stren_setting = 0x00; /* High-impedance */
+ if (DrvStren_ohm == 0) {
+ Stren_setting = 0x00; /* High-impedance */
} else if (DrvStren_ohm < 29) {
Stren_setting = 0x3f;
} else if (DrvStren_ohm < 31) {
/* DDR4 & LPDDR3 - N is high-Z */
Stren_setting = 0x00; /* High-impedance */
} else if ((TargetCSR == ADrvStrenP_T) || (TargetCSR == ADrvStrenN_T)) {
- if (DrvStren_ohm == 120) { Stren_setting = 0x00;
+ if (DrvStren_ohm == 120) {
+ Stren_setting = 0x00;
} else if (DrvStren_ohm == 60) {
Stren_setting = 0x01;
} else if (DrvStren_ohm == 40) {
struct pmu_msg_info {
int id;
- const char* info;
+ const char *info;
};
int phyinit_G_WaitFWDone(int port);
static uint8_t getMBdata_u8(int port, size_t offset)
{
uint16_t mem = DDRPHY_READ_REG16(port, (DDRPHY_PMU_DCCM_ADDR + (offset / 2)));
+
return (offset % 2) ? (uint8_t)(mem >> 8) : (uint8_t)mem;
}
}
/* return: PHY training result - TxDqsDly maximum, in PHY clocks */
-static unsigned phy_getTxDqsDlyMax(int port)
+static unsigned int phy_getTxDqsDlyMax(int port)
{
- unsigned dly_max = 0;
+ unsigned int dly_max = 0;
const int pstate = 0;
const uint32_t TxDqsDlyTgX_addr[4] = {
csr_TxDqsDlyTg0_ADDR, csr_TxDqsDlyTg1_ADDR,
csr_TxDqsDlyTg2_ADDR, csr_TxDqsDlyTg3_ADDR
};
- for (unsigned byte = 0; byte < 9; byte++) {
- for (unsigned lane = 0; lane <= 1; lane++) {
- unsigned b_addr = lane << 8;
- unsigned c_addr = byte << 12;
- unsigned p_addr = pstate << 20;
- for (int i = 0; i < 4; i++) {
- uint16_t val = DDRPHY_READ_REG16(port,
- (p_addr | tDBYTE | c_addr | b_addr | TxDqsDlyTgX_addr[i]));
- unsigned dly_frac = val & 0x1f; /* [4..0] bits for fractional value */
- unsigned dly_int = (val >> 6) & 0xf; /* [9..6] bits for integer value */
- if (dly_frac != 0) {
- dly_int += 1;
- }
- if (dly_int > dly_max) {
- dly_max = dly_int;
- }
- }
- }
+
+ for (unsigned int byte = 0; byte < 9; byte++) {
+ for (unsigned int lane = 0; lane <= 1; lane++) {
+ unsigned int b_addr = lane << 8;
+ unsigned int c_addr = byte << 12;
+ unsigned int p_addr = pstate << 20;
+
+ for (int i = 0; i < 4; i++) {
+ uint16_t val = DDRPHY_READ_REG16(port,
+ (p_addr | tDBYTE | c_addr | b_addr | TxDqsDlyTgX_addr[i]));
+ unsigned int dly_frac = val & 0x1f; /* [4..0] bits for fractional value */
+ unsigned int dly_int = (val >> 6) & 0xf; /* [9..6] bits for integer value */
+
+ if (dly_frac != 0) {
+ dly_int += 1;
+ }
+
+ if (dly_int > dly_max) {
+ dly_max = dly_int;
+ }
+ }
+ }
}
/* convert result from UI to PHY clk value */
/* get rd2wr training result for single-rank DDR (just get R0-R0 result) */
/* see phy pub databook "Rank-to-Rank Spacing" */
-static unsigned phy_getRd2WrCDDsr(int port, unsigned cdd_00_offset)
+static unsigned int phy_getRd2WrCDDsr(int port, unsigned int cdd_00_offset)
{
int8_t rd2wr = getMBdata_u8(port, cdd_00_offset);
+
return (rd2wr >= 0) ? rd2wr : -rd2wr;
}
/* get rd2wr training result for multi-ranks DDR (seek maximum for all ranks) */
/* see phy pub databook "Rank-to-Rank Spacing" */
-static unsigned phy_getRd2WrCDDmr(int port, unsigned cdd_33_offset, unsigned cdd_00_offset, unsigned cs_mask)
+static unsigned int phy_getRd2WrCDDmr(int port,
+ unsigned int cdd_33_offset,
+ unsigned int cdd_00_offset,
+ unsigned int cs_mask)
{
- unsigned rd2wr_max = 0;
+ unsigned int rd2wr_max = 0;
/* read uint8_t CDD data by uint16_t bus read transaction */
- unsigned start_offset_u16 = cdd_33_offset & ~0x1;
- unsigned end_offset_u16 = cdd_00_offset & ~0x1;
+ unsigned int start_offset_u16 = cdd_33_offset & ~0x1;
+ unsigned int end_offset_u16 = cdd_00_offset & ~0x1;
int cs_high = 3;
int cs_low = 3;
- for (unsigned offset = start_offset_u16; offset <= end_offset_u16; offset += 2) {
+
+ for (unsigned int offset = start_offset_u16; offset <= end_offset_u16; offset += 2) {
uint16_t data = getMBdata_u16(port, offset);
+
if ((offset + 0) >= cdd_33_offset) {
if ((cs_mask & (1 << cs_high)) && (cs_mask & (1 << cs_low))) {
/* low byte data process */
int8_t rd2wr = data & 0xff;
- unsigned rd2wr_abs = (rd2wr >= 0) ? rd2wr : -rd2wr;
+ unsigned int rd2wr_abs = (rd2wr >= 0) ? rd2wr : -rd2wr;
+
if (rd2wr_abs > rd2wr_max) {
rd2wr_max = rd2wr_abs;
}
if ((cs_mask & (1 << cs_high)) && (cs_mask & (1 << cs_low))) {
/* high byte data process */
int8_t rd2wr = data >> 8;
- unsigned rd2wr_abs = (rd2wr >= 0) ? rd2wr : -rd2wr;
+ unsigned int rd2wr_abs = (rd2wr >= 0) ? rd2wr : -rd2wr;
+
if (rd2wr_abs > rd2wr_max) {
rd2wr_max = rd2wr_abs;
}
}
cs_low -= 1;
- if (cs_low < 0) { cs_low = 3; cs_high -= 1; }
+ if (cs_low < 0) {
+ cs_low = 3;
+ cs_high -= 1;
+ }
}
}
/* get wr2wr training result for multi-ranks DDR (seek maximum for all ranks) */
/* see phy pub databook "Rank-to-Rank Spacing" */
-static unsigned phy_getWr2WrCDDmr(int port, unsigned cdd_32_offset, unsigned cdd_01_offset, unsigned cs_mask)
+static unsigned int phy_getWr2WrCDDmr(int port,
+ unsigned int cdd_32_offset,
+ unsigned int cdd_01_offset,
+ unsigned int cs_mask)
{
int wr2wr_max = 0;
/* read uint8_t CDD data by uint16_t bus read transaction */
- unsigned start_offset_u16 = cdd_32_offset & ~0x1;
- unsigned end_offset_u16 = cdd_01_offset & ~0x1;
+ unsigned int start_offset_u16 = cdd_32_offset & ~0x1;
+ unsigned int end_offset_u16 = cdd_01_offset & ~0x1;
int cs_high = 3;
int cs_low = 2;
- for (unsigned offset = start_offset_u16; offset <= end_offset_u16; offset += 2) {
+
+ for (unsigned int offset = start_offset_u16; offset <= end_offset_u16; offset += 2) {
uint16_t data = getMBdata_u16(port, offset);
+
if ((offset + 0) >= cdd_32_offset) {
if ((cs_mask & (1 << cs_high)) && (cs_mask & (1 << cs_low))) {
/* low byte data process */
int8_t wr2wr = data & 0xff;
- if (wr2wr > wr2wr_max)
+
+ if (wr2wr > wr2wr_max) {
wr2wr_max = wr2wr;
+ }
}
cs_low -= 1;
if (cs_low < 0) {
if ((cs_mask & (1 << cs_high)) && (cs_mask & (1 << cs_low))) {
/* high byte data process */
int8_t wr2wr = data >> 8;
+
if (wr2wr > wr2wr_max) {
wr2wr_max = wr2wr;
}
/* get rd2rd training result for multi-ranks DDR (seek maximum for all ranks) */
/* see phy pub databook "Rank-to-Rank Spacing" */
-static unsigned phy_getRd2RdCDDmr(int port, unsigned cdd_32_offset, unsigned cdd_01_offset, unsigned cs_mask)
+static unsigned int phy_getRd2RdCDDmr(int port,
+ unsigned int cdd_32_offset,
+ unsigned int cdd_01_offset,
+ unsigned int cs_mask)
{
int rd2rd_max = 0;
/* read uint8_t CDD data by uint16_t bus read transaction */
- unsigned start_offset_u16 = cdd_32_offset & ~0x1;
- unsigned end_offset_u16 = cdd_01_offset & ~0x1;
+ unsigned int start_offset_u16 = cdd_32_offset & ~0x1;
+ unsigned int end_offset_u16 = cdd_01_offset & ~0x1;
int cs_high = 3;
int cs_low = 2;
- for (unsigned offset = start_offset_u16; offset <= end_offset_u16; offset += 2) {
+
+ for (unsigned int offset = start_offset_u16; offset <= end_offset_u16; offset += 2) {
uint16_t data = getMBdata_u16(port, offset);
+
if ((offset + 0) >= cdd_32_offset) {
if ((cs_mask & (1 << cs_high)) && (cs_mask & (1 << cs_low))) {
/* low byte data process */
int8_t rd2rd = data & 0xff;
+
if (rd2rd > rd2rd_max) {
rd2rd_max = rd2rd;
}
if ((cs_mask & (1 << cs_high)) && (cs_mask & (1 << cs_low))) {
/* high byte data process */
int8_t rd2rd = data >> 8;
- if (rd2rd > rd2rd_max)
+
+ if (rd2rd > rd2rd_max) {
rd2rd_max = rd2rd;
+ }
}
cs_low -= 1;
if (cs_low < 0) {
int phyinit_H_readMsgBlock(int port, struct ddr_configuration *data)
{
- /* 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
- * This allows the memory controller unrestricted access to the configuration CSRs. */
+ /*
+ * 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+ * This allows the memory controller unrestricted access to the configuration CSRs.
+ */
DDRPHY_WRITE_REG16(port, (tAPBONLY | csr_MicroContMuxSel_ADDR), 0x0);
uint8_t cs_fail = getMBdata_u8(port, 0x14); /* offsetof(pmu_smb_ddr4_t, CsTestFail) */
data->trn_res.TxDqsDlyMax = phy_getTxDqsDlyMax(port);
uint8_t CsPresent = data->ranks == 1 ? 0x1 : 0x3;
+
if (data->dimms == 2) {
CsPresent = CsPresent | (CsPresent << 2);
}
uint8_t PllBypassEn;
uint16_t DRAMFreq;
uint8_t DfiFreqRatio;
- uint8_t BPZNResVal ;
+ uint8_t BPZNResVal;
uint8_t PhyOdtImpedance;
uint8_t PhyDrvImpedance;
uint8_t PhyVref;
/*
- * Copyright (c) 2021-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2021-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define BAIKAL_BOOT_SPI_SUBSECTOR (4 * 1024)
#define BAIKAL_BOOT_SPI_SIZE (32 * 1024 * 1024)
+#define BAIKAL_I2C_ICLK_FREQ 200000000
#define SYS_COUNTER_FREQ_IN_TICKS ULL(25000000)
#if defined(BAIKAL_QEMU)
#define GIC_BASE U(0x1000000)
#define GIC_SIZE U(0x1000000)
#define GICD_BASE (GIC_BASE)
+#define GITS0_BASE (GIC_BASE + 0x40000)
+#define GITS0_TRANSLATER (GIC_BASE + 0x50040)
+#define GITS1_BASE (GIC_BASE + 0x60000)
+#define GITS1_TRANSLATER (GIC_BASE + 0x70040)
+#define GITS2_BASE (GIC_BASE + 0x80000)
+#define GITS2_TRANSLATER (GIC_BASE + 0x90040)
+#define GITS3_BASE (GIC_BASE + 0xa0000)
+#define GITS3_TRANSLATER (GIC_BASE + 0xb0040)
+#define GITS4_BASE (GIC_BASE + 0xc0000)
+#define GITS4_TRANSLATER (GIC_BASE + 0xd0040)
+#define GITS5_BASE (GIC_BASE + 0xe0000)
+#define GITS5_TRANSLATER (GIC_BASE + 0xf0040)
+#define GITS6_BASE (GIC_BASE + 0x100000)
+#define GITS6_TRANSLATER (GIC_BASE + 0x110040)
+#define GITS7_BASE (GIC_BASE + 0x120000)
+#define GITS7_TRANSLATER (GIC_BASE + 0x130040)
+#define GITS8_BASE (GIC_BASE + 0x140000)
+#define GITS8_TRANSLATER (GIC_BASE + 0x150040)
+#define GITS9_BASE (GIC_BASE + 0x160000)
+#define GITS9_TRANSLATER (GIC_BASE + 0x170040)
+#define GITS10_BASE (GIC_BASE + 0x180000)
+#define GITS10_TRANSLATER (GIC_BASE + 0x190040)
+#define GITS11_BASE (GIC_BASE + 0x1a0000)
+#define GITS11_TRANSLATER (GIC_BASE + 0x1b0040)
+#define GITS12_BASE (GIC_BASE + 0x1c0000)
+#define GITS12_TRANSLATER (GIC_BASE + 0x1d0040)
+#define GITS13_BASE (GIC_BASE + 0x1e0000)
+#define GITS13_TRANSLATER (GIC_BASE + 0x1f0040)
+#define GITS14_BASE (GIC_BASE + 0x200000)
+#define GITS14_TRANSLATER (GIC_BASE + 0x210040)
+#define GITS15_BASE (GIC_BASE + 0x220000)
+#define GITS15_TRANSLATER (GIC_BASE + 0x230040)
#define GICR_BASE (GIC_BASE + 0x240000)
#define CORESIGHT_CFG_BASE U(0x2000000)
#define PCIE0_GPR_BASE (PCIE0_BASE + 0x20000)
#define PCIE0_GPR_SS_MODE_CTL (PCIE0_GPR_BASE + 0x10)
#define PCIE0_GPR_PWRUP_RST_CTL (PCIE0_GPR_BASE + 0x18)
+#define PCIE0_GPR_ITS0_TRGTADDR_CTL (PCIE0_GPR_BASE + 0x88)
+#define PCIE0_GPR_ITS1_TRGTADDR_CTL (PCIE0_GPR_BASE + 0x90)
#define PCIE0_PVT_BASE (PCIE0_BASE + 0x30000)
#define PCIE0_NIC_CFG_GPV (PCIE0_BASE + 0x200000)
#define PCIE0_NIC_CFG_P0 (PCIE0_NIC_CFG_GPV + 0x08)
#define PCIE1_GPR_BASE (PCIE1_BASE + 0x20000)
#define PCIE1_GPR_SS_MODE_CTL (PCIE1_GPR_BASE + 0x10)
#define PCIE1_GPR_PWRUP_RST_CTL (PCIE1_GPR_BASE + 0x18)
+#define PCIE1_GPR_ITS0_TRGTADDR_CTL (PCIE1_GPR_BASE + 0x88)
+#define PCIE1_GPR_ITS1_TRGTADDR_CTL (PCIE1_GPR_BASE + 0x90)
#define PCIE1_PVT_BASE (PCIE1_BASE + 0x30000)
#define PCIE1_NIC_CFG_GPV (PCIE1_BASE + 0x200000)
#define PCIE1_NIC_CFG_P0 (PCIE1_NIC_CFG_GPV + 0x08)
#define PCIE2_GPR_BASE (PCIE2_BASE + 0x20000)
#define PCIE2_GPR_SS_MODE_CTL (PCIE2_GPR_BASE + 0x10)
#define PCIE2_GPR_PWRUP_RST_CTL (PCIE2_GPR_BASE + 0x18)
+#define PCIE2_GPR_ITS0_TRGTADDR_CTL (PCIE2_GPR_BASE + 0x88)
+#define PCIE2_GPR_ITS1_TRGTADDR_CTL (PCIE2_GPR_BASE + 0x90)
#define PCIE2_PVT_BASE (PCIE2_BASE + 0x30000)
#define PCIE2_NIC_CFG_GPV (PCIE2_BASE + 0x200000)
#define PCIE2_NIC_CFG_P0 (PCIE2_NIC_CFG_GPV + 0x08)
#define PCIE3_GPR_BASE (PCIE3_BASE + 0x20000)
#define PCIE3_GPR_SS_MODE_CTL (PCIE3_GPR_BASE + 0x10)
#define PCIE3_GPR_PWRUP_RST_CTL (PCIE3_GPR_BASE + 0x18)
+#define PCIE3_GPR_ITS0_TRGTADDR_CTL (PCIE3_GPR_BASE + 0x120)
+#define PCIE3_GPR_ITS1_TRGTADDR_CTL (PCIE3_GPR_BASE + 0x128)
+#define PCIE3_GPR_ITS2_TRGTADDR_CTL (PCIE3_GPR_BASE + 0x130)
+#define PCIE3_GPR_ITS3_TRGTADDR_CTL (PCIE3_GPR_BASE + 0x138)
+#define PCIE3_GPR_ITS4_TRGTADDR_CTL (PCIE3_GPR_BASE + 0x140)
#define PCIE3_PVT_BASE (PCIE3_BASE + 0x30000)
#define PCIE3_NIC_CFG_GPV (PCIE3_BASE + 0x200000)
#define PCIE3_NIC_CFG_P0 (PCIE3_NIC_CFG_GPV + 0x08)
#define PCIE4_GPR_BASE (PCIE4_BASE + 0x20000)
#define PCIE4_GPR_SS_MODE_CTL (PCIE4_GPR_BASE + 0x10)
#define PCIE4_GPR_PWRUP_RST_CTL (PCIE4_GPR_BASE + 0x18)
+#define PCIE4_GPR_ITS0_TRGTADDR_CTL (PCIE4_GPR_BASE + 0x120)
+#define PCIE4_GPR_ITS1_TRGTADDR_CTL (PCIE4_GPR_BASE + 0x128)
+#define PCIE4_GPR_ITS2_TRGTADDR_CTL (PCIE4_GPR_BASE + 0x130)
+#define PCIE4_GPR_ITS3_TRGTADDR_CTL (PCIE4_GPR_BASE + 0x138)
+#define PCIE4_GPR_ITS4_TRGTADDR_CTL (PCIE4_GPR_BASE + 0x140)
#define PCIE4_PVT_BASE (PCIE4_BASE + 0x30000)
#define PCIE4_NIC_CFG_GPV (PCIE4_BASE + 0x200000)
#define PCIE4_NIC_CFG_P0 (PCIE4_NIC_CFG_GPV + 0x08)
#ifndef BS1000_DIMM_SPD_H
#define BS1000_DIMM_SPD_H
-const void* baikal_dimm_spd_get(const unsigned dimm_idx);
+const void *baikal_dimm_spd_get(const unsigned int dimm_idx);
void baikal_dimm_spd_read(void);
#endif /* BS1000_DIMM_SPD_H */
/*
- * Copyright (c) 2020-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2020-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define BAIKAL_SEC_DTB_BASE (BAIKAL_SCMM_SMMU_BASE + BAIKAL_SCMM_SMMU_SIZE)
#define BAIKAL_NS_DTB_BASE NS_DRAM0_BASE
#define BAIKAL_NS_IMAGE_OFFSET NS_DRAM1_BASE
+#define BAIKAL_NS_IMAGE_MAX_SIZE NS_DRAM1_SIZE
/* Parts of the boot image */
#define BAIKAL_SCP_MAX_SIZE (512 * 1024)
include lib/libfdt/libfdt.mk
include lib/xlat_tables_v2/xlat_tables.mk
+$(eval $(call add_define_val,SDK_VERSION,$(SDK_VERSION)))
+
HW_ASSISTED_COHERENCY := 1
USE_COHERENT_MEM := 0
plat/baikal/common/memtest.c \
plat/baikal/common/spd.c
-override BL1_LINKERFILE := plat/baikal/common/bl1.ld.S
+override BL1_DEFAULT_LINKER_SCRIPT_SOURCE := plat/baikal/common/bl1.ld.S
BL2_SOURCES += common/desc_image_load.c \
drivers/io/io_fip.c \
${GICV3_SOURCES} \
$(LIBFDT_SRCS)
+ifeq (${ENABLE_PMF}, 1)
+BL31_SOURCES += lib/pmf/pmf_smc.c
+endif
+
ifeq ($(notdir $(CC)),armclang)
TF_CFLAGS_aarch64 += -mcpu=cortex-a75
else ifneq ($(findstring clang,$(notdir $(CC))),)
else
TF_CFLAGS_aarch64 += -mtune=cortex-a75
endif
+
+BL1_CPPFLAGS += -march=armv8-a+crc
+BL2_CPPFLAGS += -march=armv8-a+crc
+BL2U_CPPFLAGS += -march=armv8-a+crc
+BL31_CPPFLAGS += -march=armv8-a+crc
+BL32_CPPFLAGS += -march=armv8-a+crc
}
if (stack_area_ptr != (volatile uint64_t *)STACKS_START) {
- const unsigned used = STACKS_END - (uintptr_t)stack_area_ptr;
- const unsigned total = STACKS_END - STACKS_START;
+ const unsigned int used = STACKS_END - (uintptr_t)stack_area_ptr;
+ const unsigned int total = STACKS_END - STACKS_START;
+
INFO("BL1: %u bytes (%u%%) of stack are used\n", used, used * 100 / total);
} else {
ERROR("BL1: stack has been overflowed\n");
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
0),
.image_info.image_base = BAIKAL_NS_IMAGE_OFFSET,
- .image_info.image_max_size = NS_DRAM0_BASE + NS_DRAM0_SIZE -
- BAIKAL_NS_IMAGE_OFFSET,
+ .image_info.image_max_size = BAIKAL_NS_IMAGE_MAX_SIZE,
# endif /* !PRELOADED_BL33_BASE */
.next_handoff_image_id = INVALID_IMAGE_ID,
# include <dw_spi_flash.h>
#endif
-void bootflash_init(void)
+int bootflash_init(void)
{
#if defined(BAIKAL_MBM10) || defined(BAIKAL_MBM20)
- scp_flash_init();
+ return scp_flash_init();
#else
- spi_flash_init(BAIKAL_BOOT_SPI_SS_LINE);
+ return spi_flash_init(BAIKAL_BOOT_SPI_SS_LINE);
#endif
}
void fdt_memory_node_set(void *fdt,
const uint64_t region_descs[][2],
- const unsigned region_num)
+ const unsigned int region_num)
{
int err;
uint64_t memregs[4][2];
int node;
- unsigned region;
+ unsigned int region;
assert(fdt != NULL);
assert(region_num >= 1 && region_num <= ARRAY_SIZE(memregs));
/*
- * Copyright (c) 2020-2021, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2020-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/common/platform.h>
#include <baikal_def.h>
+#include <baikal_gicv3.h>
#include <platform_def.h>
/* The GICv3 driver only needs to be initialized in EL3 */
#include <crc.h>
#include <platform_def.h>
+#include <drivers/mmc.h>
+#include <baikal_mshc.h>
+#include <baikal_def.h>
+
/* IO devices */
static const io_dev_connector_t *fip_dev_con;
static uintptr_t fip_dev_handle;
return local_image_handle;
}
+#ifdef IMAGE_BL1
/* Return 0 for equal uuids. */
static inline int compare_uuids(const uuid_t *uuid1, const uuid_t *uuid2)
{
return memcmp(uuid1, uuid2, sizeof(uuid_t));
}
-static int read_fdt_from_flash(uint32_t flashaddr)
+size_t bootflash_read_blocks(int lba, uintptr_t buf, size_t size)
+{
+ if (bootflash_read(lba * MMC_BLOCK_SIZE, (void *)buf, size)) {
+ return 0;
+ } else {
+ return size;
+ }
+}
+
+/* TODO: use io_open, io_read */
+static int read_fdt(uintptr_t src, uintptr_t dst, void *func)
{
- uint8_t *dst = (void *)BAIKAL_SEC_DTB_BASE;
+ size_t (*read_blocks)(int lba, uintptr_t dst, size_t size) = func;
int err;
const struct fdt_header *const fdt_header = (void *)dst;
uint32_t fdt_totalsize;
- err = bootflash_read(flashaddr, dst, sizeof(struct fdt_header));
- flush_dcache_range((uintptr_t)dst, sizeof(struct fdt_header));
- if (err) {
- return -ENOENT;
+ err = read_blocks((src / MMC_BLOCK_SIZE),
+ ROUND_DOWN(dst),
+ ROUND_UP(sizeof(struct fdt_header)));
+ if (!err) {
+ VERBOSE("%s: -- read_blocks\n", __func__);
+ return -1;
}
if (be32toh(fdt_header->magic) != FDT_MAGIC) {
ERROR("%s: FDT header magic is wrong\n", __func__);
- return -ENOENT;
+ return -1;
}
fdt_totalsize = be32toh(fdt_header->totalsize);
if (fdt_totalsize < sizeof(struct fdt_header) ||
fdt_totalsize > BAIKAL_DTB_MAX_SIZE) {
ERROR("%s: FDT total size is wrong: %u\n", __func__, fdt_totalsize);
- return -ENOENT;
+ return -1;
}
- dst += sizeof(struct fdt_header);
- flashaddr += sizeof(struct fdt_header);
- err = bootflash_read(flashaddr, dst, fdt_totalsize - sizeof(struct fdt_header));
- flush_dcache_range((uintptr_t)dst, fdt_totalsize - sizeof(struct fdt_header));
- if (err) {
- return -ENOENT;
+ err = read_blocks((src / MMC_BLOCK_SIZE),
+ ROUND_DOWN(dst),
+ ROUND_UP(fdt_totalsize));
+ if (!err) {
+ VERBOSE("%s: -- read_blocks\n", __func__);
+ return -1;
}
- INFO("DTB: crc32:0x%08x size:%u\n",
+ INFO("BL1: DTB crc32:0x%08x size:%u\n",
crc32((void *)BAIKAL_SEC_DTB_BASE, fdt_totalsize, 0),
fdt_totalsize);
return 0;
}
-
-static int read_fip_from_flash(uintptr_t local_image_handle, uint32_t offset)
+static int read_fip(uintptr_t src, uintptr_t dst, uintptr_t local_image_handle, void *func)
{
+ size_t (*read_blocks)(int lba, uintptr_t dst, size_t size) = func;
fip_toc_entry_t entry = {0};
int result, size = 0;
size_t bytes_read;
- uint8_t *addr = (uint8_t *)BAIKAL_FIP_BASE;
- int src = offset;
static const uuid_t uuid_null = {0};
/* Read FIP Header part */
result = io_seek(local_image_handle, IO_SEEK_SET, sizeof(fip_toc_header_t));
if (result != 0) {
- WARN("fip_file_open: failed to seek\n");
- result = -ENOENT;
+ VERBOSE("%s: -- io_seek\n", __func__);
+ return -1;
}
- result = bootflash_read(src, addr, sizeof(fip_toc_header_t));
- flush_dcache_range((uintptr_t)addr, sizeof(fip_toc_header_t));
- if (result != 0) {
- result = -ENOENT;
+ result = read_blocks((src / MMC_BLOCK_SIZE),
+ ROUND_DOWN(dst),
+ ROUND_UP(sizeof(fip_toc_header_t)));
+ if (!result) {
+ VERBOSE("%s: -- read_blocks\n", __func__);
+ return -1;
}
- src += sizeof(fip_toc_header_t);
- addr += sizeof(fip_toc_header_t);
+ src += sizeof(fip_toc_header_t);
+ dst += sizeof(fip_toc_header_t);
do {
- result = bootflash_read(src, addr, sizeof(fip_toc_entry_t));
- flush_dcache_range((uintptr_t)addr, sizeof(fip_toc_entry_t));
- if (result != 0) {
- result = -ENOENT;
+ result = read_blocks((src / MMC_BLOCK_SIZE),
+ ROUND_DOWN(dst),
+ ROUND_UP(sizeof(fip_toc_entry_t)));
+ if (!result) {
+ VERBOSE("%s: -- read_blocks\n", __func__);
+ return -1;
}
result = io_read(local_image_handle,
sizeof(entry),
&bytes_read);
if (result != 0) {
- WARN("Failed to read FIP (%i)\n", result);
+ VERBOSE("%s: -- io_read\n", __func__);
+ return -1;
}
- src += sizeof(fip_toc_entry_t);
- addr += sizeof(fip_toc_entry_t);
+ src += sizeof(fip_toc_entry_t);
+ dst += sizeof(fip_toc_entry_t);
size += entry.size;
+
} while (compare_uuids(&entry.uuid, &uuid_null) != 0);
- result = bootflash_read(src, addr, size);
- flush_dcache_range((uintptr_t)addr, size);
- if (result != 0) {
- result = -ENOENT;
+ result = read_blocks((src / MMC_BLOCK_SIZE),
+ ROUND_DOWN(dst),
+ ROUND_UP(size));
+ if (!result) {
+ VERBOSE("%s: -- read_blocks\n", __func__);
+ return -1;
}
- INFO("FIP: crc32:0x%08x size:%lu\n",
- crc32((void *)BAIKAL_FIP_BASE, (uintptr_t)addr + size - BAIKAL_FIP_BASE, 0),
- (uintptr_t)addr + size - BAIKAL_FIP_BASE);
+ INFO("BL1: FIP crc32:0x%08x size:%lu\n",
+ crc32((void *)BAIKAL_FIP_BASE, dst + size - BAIKAL_FIP_BASE, 0),
+ dst + size - BAIKAL_FIP_BASE);
- return result;
+ return 0;
}
-static int read_flash(uintptr_t local_image_handle)
+#ifdef BAIKAL_SD_FIRMWARE_DEBUG
+int mmc_test(uint32_t dst)
{
- int result;
+ int i = 0;
+ uint32_t cnt[] = {1, 100, 1000, 0};
- result = read_fdt_from_flash(BAIKAL_DTB_OFFSET);
- result |= read_fip_from_flash(local_image_handle, BAIKAL_FIP_OFFSET);
- return result;
+ while (cnt[i]) {
+ uint32_t size = MMC_BLOCK_SIZE * cnt[i];
+ uintptr_t buf = BAIKAL_FIP_BASE + 0 * size;
+ uintptr_t bufa = BAIKAL_FIP_BASE + 1 * size;
+ uintptr_t bufb = BAIKAL_FIP_BASE + 2 * size;
+
+ memset((void *)bufa, 0xaa, size);
+ memset((void *)bufb, 0xbb, size);
+
+ mmc_read_blocks(dst / MMC_BLOCK_SIZE, buf, size); /* save */
+ mmc_write_blocks(dst / MMC_BLOCK_SIZE, bufa, size);
+ mmc_read_blocks(dst / MMC_BLOCK_SIZE, bufb, size);
+ mmc_write_blocks(dst / MMC_BLOCK_SIZE, buf, size); /* restore */
+
+ int ret = memcmp((void *)bufa, (void *)bufb, size);
+
+ if (ret) {
+ VERBOSE("%s: -- mmc fail\n", __func__);
+ return ret;
+ }
+
+ i++;
+ }
+
+ return 0;
}
+int mmc_copy(uint32_t dst, uint32_t src, uint32_t size)
+{
+ uintptr_t buf = BAIKAL_FIP_BASE;
+ uint64_t part;
+
+ bootflash_init();
+ while (size) {
+ part = MIN(size, 1024 * MMC_BLOCK_SIZE);
+ bootflash_read(src, (void *)buf, part);
+ mmc_write_blocks(dst / MMC_BLOCK_SIZE, buf, part);
+ src += part;
+ dst += part;
+ size -= part;
+ }
+
+ return 0;
+}
+#endif /* BAIKAL_SD_FIRMWARE_DEBUG */
+
+static int read_image(uintptr_t local_image_handle)
+{
+ int ret;
+
+ /* sd */
+#ifdef BAIKAL_SD_FIRMWARE
+ ret = dw_mshc_init();
+ if (ret) {
+ goto skip;
+ }
+
+#ifdef BAIKAL_SD_FIRMWARE_TEST
+ VERBOSE("BL1: test sd/mmc...\n");
+ ret = mmc_test(BAIKAL_SD_FIRMWARE_OFFSET);
+ if (ret) {
+ goto skip;
+ }
+#endif
+
+#ifdef BAIKAL_SD_FIRMWARE_DEBUG
+ VERBOSE("BL1: copy firmware to sd/mmc...\n");
+ ret = mmc_copy(BAIKAL_SD_FIRMWARE_OFFSET, BAIKAL_BOOT_OFFSET, BAIKAL_BOOT_MAX_SIZE);
+ if (ret) {
+ goto skip;
+ }
+#endif /* BAIKAL_SD_FIRMWARE_DEBUG */
+
+ VERBOSE("BL1: read firmware from sd/mmc...\n");
+ ret = read_fdt(BAIKAL_SD_FIRMWARE_OFFSET + BAIKAL_DTB_OFFSET, BAIKAL_SEC_DTB_BASE, (void *)mmc_read_blocks);
+ if (ret) {
+ goto skip;
+ }
+ ret = read_fip(BAIKAL_SD_FIRMWARE_OFFSET + BAIKAL_FIP_OFFSET, BAIKAL_FIP_BASE, local_image_handle, (void *)mmc_read_blocks);
+
+skip:
+ dw_mshc_off();
+ if (ret == 0) {
+ return ret;
+ }
+#endif /* BAIKAL_SD_FIRMWARE */
+
+ /* flash */
+ ret = bootflash_init();
+ if (ret) {
+ return ret;
+ }
+ VERBOSE("BL1: read firmware from spi flash...\n");
+ ret = read_fdt(BAIKAL_DTB_OFFSET, BAIKAL_SEC_DTB_BASE, (void *)bootflash_read_blocks);
+ if (ret) {
+ return ret;
+ }
+ ret = read_fip(BAIKAL_FIP_OFFSET, BAIKAL_FIP_BASE, local_image_handle, (void *)bootflash_read_blocks);
+ return ret;
+}
+#endif /* IMAGE_BL1 */
static inline int is_valid_header(fip_toc_header_t *header)
{
if (result == 0) {
result = io_open(memmap_dev_handle, spec, &local_image_handle);
if (result == 0) {
-#ifndef IMAGE_BL1
+#ifdef IMAGE_BL1
+ result = read_image(local_image_handle);
+#endif
if (!(is_valid_header((fip_toc_header_t *)BAIKAL_FIP_BASE))) {
- result = read_flash(local_image_handle);
+ VERBOSE("%s: -- broken fip\n", __func__);
+ result = -1;
}
-#else
- result = read_flash(local_image_handle);
-#endif
+
io_close(local_image_handle);
}
}
--- /dev/null
+/*
+ * Copyright (c) 2023, Baikal Electronics, JSC. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <string.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include <baikal_mshc.h>
+#include <baikal_def.h>
+
+/* TODO: rework */
+#if defined(BAIKAL_DBM10) || defined(BAIKAL_DBM20) || \
+ defined(BAIKAL_MBM10) || defined(BAIKAL_MBM20)
+#include <bm1000_cmu.h>
+#endif
+
+static int reg_size(int Reg)
+{
+ int size = 0;
+
+ switch (Reg) {
+ case SDHCI_DMA_ADDRESS:
+ case SDHCI_ARGUMENT:
+ case SDHCI_BUFFER:
+ case SDHCI_PRESENT_STATE:
+ case SDHCI_MSHC_VER:
+ case SDHCI_CAPABILITIES:
+ case SDHCI_CAPABILITIES_1:
+ case SDHCI_MAX_CURRENT:
+ case SDHCI_ADMA_ADDRESS:
+ case SDHCI_ADMA_ADDRESS_HI:
+ case SDHCI_RESPONSE_0:
+ case SDHCI_RESPONSE_1:
+ case SDHCI_RESPONSE_2:
+ case SDHCI_RESPONSE_3:
+ size = 4;
+ break;
+
+ case SDHCI_TRANSFER_MODE:
+ case SDHCI_BLOCK_SIZE:
+ case SDHCI_16BIT_BLK_CNT:
+ case SDHCI_COMMAND:
+ case SDHCI_CLOCK_CONTROL:
+ case SDHCI_INT_STATUS:
+ case SDHCI_ERR_STATUS:
+ case SDHCI_INT_ENABLE:
+ case SDHCI_ERR_ENABLE:
+ case SDHCI_SIGNAL_ENABLE:
+ case SDHCI_ERR_SIGNAL_ENABLE:
+ case SDHCI_AUTO_CMD_STATUS:
+ case SDHCI_HOST_CONTROL2:
+ case SDHCI_SET_INT_ERROR:
+ case SDHCI_SET_ACMD12_ERROR:
+ case SDHCI_PRESET_INIT:
+ case SDHCI_PRESET_DS:
+ case SDHCI_PRESET_HS:
+ case SDHCI_PRESET_FOR_SDR12:
+ case SDHCI_PRESET_FOR_SDR25:
+ case SDHCI_PRESET_FOR_SDR50:
+ case SDHCI_PRESET_FOR_SDR104:
+ case SDHCI_PRESET_FOR_DDR50:
+ case SDHCI_PRESET_FOR_HS400:
+ case SDHCI_SLOT_INT_STATUS:
+ case SDHCI_HOST_VERSION:
+ case SDHCI_EMMC_CONTROL:
+ size = 2;
+ break;
+
+ case SDHCI_TIMEOUT_CONTROL:
+ case SDHCI_SOFTWARE_RESET:
+ case SDHCI_ADMA_ERROR:
+ case SDHCI_MSHC_CTRL:
+ case SDHCI_HOST_CONTROL:
+ case SDHCI_POWER_CONTROL:
+ case SDHCI_BLOCK_GAP_CONTROL:
+ case SDHCI_WAKE_UP_CONTROL:
+ size = 1;
+ break;
+ }
+
+ return size;
+}
+
+static int reg_write(uintptr_t base, int Val, int Reg)
+{
+ switch (reg_size(Reg)) {
+ case 4:
+ *(uint32_t *) (base + Reg) = Val;
+ break;
+ case 2:
+ *(uint16_t *) (base + Reg) = Val;
+ break;
+ case 1:
+ *(uint8_t *) (base + Reg) = Val;
+ break;
+ }
+
+ return -1;
+}
+
+static int reg_read(uintptr_t base, int Reg)
+{
+ switch (reg_size(Reg)) {
+ case 4:
+ return *(uint32_t *) (base + Reg);
+ case 2:
+ return *(uint16_t *) (base + Reg);
+ case 1:
+ return *(uint8_t *) (base + Reg);
+ }
+
+ return -1;
+}
+
+static void led_on(uintptr_t base, uint32_t on)
+{
+ int reg = reg_read(base, SDHCI_HOST_CONTROL);
+
+ if (on) {
+ reg &= ~SDHCI_CTRL_LED;
+ } else {
+ reg |= SDHCI_CTRL_LED;
+ }
+
+ reg_write(base, reg, SDHCI_HOST_CONTROL);
+}
+
+static int speed_mode(uintptr_t base, uint32_t mode)
+{
+ int ctrl1 = reg_read(base, SDHCI_HOST_CONTROL);
+ int ctrl2 = reg_read(base, SDHCI_HOST_CONTROL2);
+
+ switch (mode) {
+ case SD_DEFAULT:
+ ctrl1 &= ~SDHCI_CTRL_HISPD;
+ ctrl2 &= ~SDHCI_CTRL_VDD_180;
+ break;
+ case SD_HIGH:
+ ctrl1 |= SDHCI_CTRL_HISPD;
+ ctrl2 &= ~SDHCI_CTRL_VDD_180;
+ break;
+ case SD_12:
+ ctrl2 |= SDHCI_CTRL_UHS_SDR12;
+ ctrl2 |= SDHCI_CTRL_VDD_180;
+ break;
+ case SD_25:
+ ctrl2 |= SDHCI_CTRL_UHS_SDR25;
+ ctrl2 |= SDHCI_CTRL_VDD_180;
+ break;
+ case SD_50:
+ ctrl2 |= SDHCI_CTRL_UHS_SDR50;
+ ctrl2 |= SDHCI_CTRL_VDD_180;
+ break;
+ case SD_104:
+ ctrl2 |= SDHCI_CTRL_UHS_SDR104;
+ ctrl2 |= SDHCI_CTRL_VDD_180;
+ break;
+ case DD_50:
+ ctrl2 |= SDHCI_CTRL_UHS_DDR50;
+ ctrl2 |= SDHCI_CTRL_VDD_180;
+ break;
+ default:
+ return -1;
+ }
+
+ reg_write(base, ctrl1, SDHCI_HOST_CONTROL);
+ reg_write(base, ctrl2, SDHCI_HOST_CONTROL2);
+ return 0;
+}
+
+static int clock_supply(uintptr_t base, uint32_t Freq)
+{
+ int ret;
+ int Reg;
+
+ /* Disable */
+ Reg = reg_read(base, SDHCI_CLOCK_CONTROL);
+ Reg &= ~SDHCI_CLOCK_PLL_EN;
+ Reg &= ~SDHCI_CLOCK_CARD_EN;
+ reg_write(base, Reg, SDHCI_CLOCK_CONTROL);
+
+ /* TODO: rework */
+ /* Config */
+#if defined(BM1000_CMU_H)
+ int Div = MMAVLSP_PLL_FREQ / (2 * Freq);
+
+ cmu_clkch_enable_by_base(MMAVLSP_CMU0_CLKCHCTL_MSHC_TX_X2, Div);
+#elif defined(BS1000_CMU_H)
+ /* cmu_clkch_set_rate(MMAVLSP_CMU0_CLKCHCTL_MSHC_TX_X2, MMAVLSP_PLL_FREQ); ?? */
+ /* cmu_clkch_enable(MMAVLSP_CMU0_CLKCHCTL_MSHC_TX_X2); ?? */
+ return -1;
+#elif defined(BL1000_CMU_H)
+ return -1;
+#else
+ return -1;
+#endif /* CMU_H */
+
+ /* Wait */
+ ret = WAIT(!(reg_read(base, SDHCI_CLOCK_CONTROL) & SDHCI_CLOCK_STABLE));
+ if (ret) {
+ return -1;
+ }
+
+ /* Enable */
+ Reg = reg_read(base, SDHCI_CLOCK_CONTROL);
+ Reg |= SDHCI_CLOCK_PLL_EN;
+ Reg |= SDHCI_CLOCK_CARD_EN;
+ reg_write(base, Reg, SDHCI_CLOCK_CONTROL);
+
+ /* Reset */
+ reg_write(base, SDHCI_RESET_CMD, SDHCI_SOFTWARE_RESET);
+ reg_write(base, SDHCI_RESET_DATA, SDHCI_SOFTWARE_RESET);
+ udelay(1000);
+ ret = WAIT(reg_read(base, SDHCI_SOFTWARE_RESET));
+ if (ret) {
+ return ret;
+ }
+
+ udelay(1000);
+ return ret;
+}
+
+static int config_width(uintptr_t base, uint32_t width)
+{
+ int ctrl = reg_read(base, SDHCI_HOST_CONTROL);
+ reg_ctl1_t *reg = (void *)&ctrl;
+
+ switch (width) {
+ case MMC_BUS_WIDTH_1:
+ reg->width = 0;
+ reg->ext_width = 0;
+ break;
+ case MMC_BUS_WIDTH_4:
+ reg->width = 1;
+ reg->ext_width = 0;
+ break;
+ case MMC_BUS_WIDTH_8:
+ reg->width = 0;
+ reg->ext_width = 1;
+ break;
+ default:
+ return -1;
+ }
+
+ reg_write(base, ctrl, SDHCI_HOST_CONTROL);
+ return 0;
+}
+
+static void reset(uintptr_t base)
+{
+ reg_write(base, SDHCI_POWER_OFF, SDHCI_POWER_CONTROL);
+ udelay(1000);
+
+ /* irq */
+ reg_write(base, 0xffff, SDHCI_INT_STATUS);
+ reg_write(base, 0xffff, SDHCI_ERR_STATUS);
+ reg_write(base, 0xffff, SDHCI_INT_ENABLE);
+ reg_write(base, 0xffff, SDHCI_ERR_ENABLE);
+ reg_write(base, 0x0000, SDHCI_SIGNAL_ENABLE);
+ reg_write(base, 0x0000, SDHCI_ERR_SIGNAL_ENABLE);
+
+ /* config */
+ reg_write(base, 0, SDHCI_HOST_CONTROL);
+ reg_write(base,
+ SDHCI_CTRL_V4_MODE |
+ SDHCI_CTRL_64BIT_ADDR |
+ SDHCI_CTRL_ASYNC,
+ SDHCI_HOST_CONTROL2);
+ reg_write(base, 0, SDHCI_TRANSFER_MODE);
+ reg_write(base, 0, SDHCI_16BIT_BLK_CNT);
+ reg_write(base, 0, SDHCI_32BIT_BLK_CNT);
+ reg_write(base, 0, SDHCI_ARGUMENT);
+ reg_write(base, 0, SDHCI_COMMAND);
+ reg_write(base, SDHCI_DEFAULT_BLOCK_SIZE, SDHCI_BLOCK_SIZE);
+ reg_write(base, SDHCI_TIMEOUT_DEFAULT, SDHCI_TIMEOUT_CONTROL);
+
+ /* clock */
+ int reg;
+
+ reg = reg_read(base, SDHCI_CLOCK_CONTROL);
+ reg &= SDHCI_CLOCK_EN;
+ reg &= SDHCI_CLOCK_CARD_EN;
+ reg &= SDHCI_CLOCK_PLL_EN;
+ reg_write(base, reg, SDHCI_CLOCK_CONTROL);
+ udelay(1000);
+
+ led_on(base, false);
+}
+
+static int init_host(uintptr_t base)
+{
+ reset(base);
+ reg_write(base, SDHCI_POWER_330 | SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
+ reg_write(base, SDHCI_CLOCK_EN, SDHCI_CLOCK_CONTROL);
+ udelay(1000);
+ return 0;
+}
+
+/*
+ * ops
+ */
+static int dw_send_cmd(struct mmc_cmd *cmd)
+{
+ int ret;
+ uintptr_t base = MMAVLSP_EMMC_BASE;
+ uint32_t CmdRaw = 0;
+ reg_cmd_t *Cmd = (void *)&CmdRaw;
+
+ /* busy */
+ ret = WAIT(reg_read(base, SDHCI_PRESENT_STATE) & (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT));
+ if (ret) {
+ goto exit;
+ }
+
+ /* clean */
+ reg_write(base, 0xffff, SDHCI_INT_STATUS);
+ reg_write(base, 0xffff, SDHCI_ERR_STATUS);
+ reg_write(base, 0x0, SDHCI_RESPONSE_0);
+ reg_write(base, 0x0, SDHCI_RESPONSE_1);
+ reg_write(base, 0x0, SDHCI_RESPONSE_2);
+ reg_write(base, 0x0, SDHCI_RESPONSE_3);
+
+ /* cmd */
+ Cmd->index = cmd->cmd_idx;
+ if (Cmd->index == MMC_CMD(14) ||
+ Cmd->index == MMC_CMD(19) ||
+ Cmd->index == MMC_CMD(17) ||
+ Cmd->index == MMC_CMD(18) ||
+ Cmd->index == MMC_CMD(21) ||
+ Cmd->index == MMC_CMD(24) ||
+ Cmd->index == MMC_CMD(25) ||
+ Cmd->index == MMC_CMD(26) ||
+ Cmd->index == MMC_CMD(27) ||
+ Cmd->index == MMC_CMD(51) ||
+ Cmd->index == MMC_CMD(49)) {
+ Cmd->data_present = 1; /* 0-nodata, 1-data */
+ }
+
+ /* mode */
+ uint32_t Mode = reg_read(base, SDHCI_TRANSFER_MODE);
+ reg_mode_t *mode = (void *)&Mode;
+
+ if (Cmd->index == MMC_CMD(24) || Cmd->index == MMC_CMD(25)) {
+ mode->xfer_dir = 0;
+ } else {
+ mode->xfer_dir = 1;
+ }
+
+ reg_write(base, Mode, SDHCI_TRANSFER_MODE);
+
+ if (cmd->resp_type & MMC_RSP_136) {
+ Cmd->resp_type = SDHCI_CMD_RESP_LONG;
+ } else if (cmd->resp_type & (MMC_RSP_48 | MMC_RSP_BUSY)) {
+ Cmd->resp_type = SDHCI_CMD_RESP_SHORT_BUSY;
+ } else if (cmd->resp_type & MMC_RSP_48) {
+ Cmd->resp_type = SDHCI_CMD_RESP_SHORT;
+ } else {
+ Cmd->resp_type = SDHCI_CMD_RESP_NONE;
+ }
+ if (cmd->resp_type & MMC_RSP_CRC) {
+ Cmd->crc_chk = 1;
+ }
+ if (cmd->resp_type & MMC_RSP_CMD_IDX) {
+ Cmd->index_chk = 1;
+ }
+
+ /* exec */
+ led_on(base, true);
+ reg_write(base, cmd->cmd_arg, SDHCI_ARGUMENT);
+ reg_write(base, CmdRaw, SDHCI_COMMAND);
+
+ /* resp */
+ ret = WAIT(!(reg_read(base, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE));
+ reg_write(base, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
+ if (ret) {
+ goto exit;
+ }
+
+ cmd->resp_data[0] = reg_read(base, SDHCI_RESPONSE_0);
+ cmd->resp_data[1] = reg_read(base, SDHCI_RESPONSE_1);
+ cmd->resp_data[2] = reg_read(base, SDHCI_RESPONSE_2);
+ cmd->resp_data[3] = reg_read(base, SDHCI_RESPONSE_3);
+
+ /* error */
+ if (reg_read(base, SDHCI_ERR_STATUS)) {
+ reg_write(base, 0xffff, SDHCI_ERR_STATUS);
+ ret = -1;
+ goto exit;
+ }
+
+exit:
+ led_on(base, false);
+ return ret;
+}
+
+static int dw_prepare(int lba, uintptr_t buf, size_t size)
+{
+ int ret;
+ uintptr_t base = MMAVLSP_EMMC_BASE;
+ uint32_t Blocksize = size < SDHCI_DEFAULT_BLOCK_SIZE ? size : SDHCI_DEFAULT_BLOCK_SIZE;
+ uint32_t Blocks = size / Blocksize;
+ uint32_t Mode = 0;
+ reg_mode_t *mode = (void *)&Mode;
+
+ /* busy */
+ ret = WAIT(reg_read(base, SDHCI_PRESENT_STATE) & (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT));
+ if (ret) {
+ return -3;
+ }
+
+ if (Blocks > 1) {
+ mode->block_cnt_en = 1;
+ mode->multi_block = 1;
+ }
+
+ reg_write(base, Blocksize, SDHCI_BLOCK_SIZE);
+ reg_write(base, Blocks, SDHCI_32BIT_BLK_CNT);
+ reg_write(base, Mode, SDHCI_TRANSFER_MODE);
+
+ return 0;
+}
+
+static int dw_read(int lba, uintptr_t buf, size_t size)
+{
+ int ret;
+ uintptr_t base = MMAVLSP_EMMC_BASE;
+ uint32_t j;
+ uint32_t Iter;
+ uint32_t *P = (void *)buf;
+ uint32_t Blocksize = reg_read(base, SDHCI_BLOCK_SIZE);
+ uint32_t Blocks = reg_read(base, SDHCI_32BIT_BLK_CNT);
+
+ led_on(base, true);
+ for (j = 0; j < Blocks; j++) {
+ ret = WAIT(!(reg_read(base, SDHCI_INT_STATUS) & SDHCI_INT_DATA_AVAIL));
+ reg_write(base, SDHCI_INT_DATA_AVAIL, SDHCI_INT_STATUS);
+ if (ret) {
+ goto exit;
+ }
+ for (Iter = 0; Iter < Blocksize / sizeof(uint32_t); Iter++) {
+ *P++ = *(uint32_t *)(base + SDHCI_BUFFER);
+ }
+ }
+
+ /* end */
+ ret = WAIT(!(reg_read(base, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END));
+ reg_write(base, SDHCI_INT_DATA_END, SDHCI_INT_STATUS);
+ if (ret) {
+ goto exit;
+ }
+
+ /* multi */
+ int mode = reg_read(base, SDHCI_TRANSFER_MODE);
+
+ if (mode & SDHCI_TRNS_MULTI) {
+ if (reg_read(base, SDHCI_32BIT_BLK_CNT)) {
+ ret = -1;
+ goto exit;
+ }
+ }
+
+ /* error */
+ if (reg_read(base, SDHCI_ERR_STATUS)) {
+ ret = -1;
+ reg_write(base, 0xffff, SDHCI_ERR_STATUS);
+ goto exit;
+ }
+
+exit:
+ led_on(base, false);
+ return ret;
+}
+
+static int dw_write(int lba, uintptr_t buf, size_t size)
+{
+ int ret;
+ uintptr_t base = MMAVLSP_EMMC_BASE;
+ uint32_t j;
+ uint32_t Iter;
+ uint32_t *P = (void *)buf;
+ uint32_t Blocksize = reg_read(base, SDHCI_BLOCK_SIZE);
+ uint32_t Blocks = reg_read(base, SDHCI_32BIT_BLK_CNT);
+
+ led_on(base, true);
+ for (j = 0; j < Blocks; j++) {
+ ret = WAIT(!(reg_read(base, SDHCI_INT_STATUS) & SDHCI_INT_SPACE_AVAIL));
+ reg_write(base, SDHCI_INT_SPACE_AVAIL, SDHCI_INT_STATUS);
+ if (ret) {
+ goto exit;
+ }
+ for (Iter = 0; Iter < Blocksize / sizeof(uint32_t); Iter++) {
+ *(uint32_t *)(base + SDHCI_BUFFER) = *P++;
+ }
+ }
+
+ /* end */
+ ret = WAIT(!(reg_read(base, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END));
+ reg_write(base, SDHCI_INT_DATA_END, SDHCI_INT_STATUS);
+ if (ret) {
+ goto exit;
+ }
+
+ /* multi */
+ if (reg_read(base, SDHCI_TRANSFER_MODE) & SDHCI_TRNS_MULTI) {
+ ret = WAIT(reg_read(base, SDHCI_32BIT_BLK_CNT));
+ if (ret) {
+ goto exit;
+ }
+ }
+
+ /* error */
+ if (reg_read(base, SDHCI_ERR_STATUS)) {
+ ret = -1;
+ reg_write(base, 0xffff, SDHCI_ERR_STATUS);
+ goto exit;
+ }
+
+exit:
+ led_on(base, false);
+ return ret;
+}
+
+static int dw_set_ios(unsigned int clk, unsigned int width)
+{
+ uintptr_t base = MMAVLSP_EMMC_BASE;
+
+ clock_supply(base, clk);
+ config_width(base, width);
+ return 0;
+}
+
+static void dw_init(void)
+{
+ uintptr_t base = MMAVLSP_EMMC_BASE;
+
+ init_host(base);
+ clock_supply(base, SDHCI_INIT_CLOCK);
+ speed_mode(base, SD_DEFAULT);
+}
+
+void dw_mshc_off(void)
+{
+ uintptr_t base = MMAVLSP_EMMC_BASE;
+
+ reset(base);
+}
+
+static const struct mmc_ops dw_mmc_ops = {
+ .init = dw_init,
+ .send_cmd = dw_send_cmd,
+ .set_ios = dw_set_ios,
+ .prepare = dw_prepare,
+ .read = dw_read,
+ .write = dw_write,
+};
+
+int dw_mshc_init(void)
+{
+ int err;
+ static struct mmc_device_info info;
+
+ memset(&info, 0, sizeof(info));
+#if 0
+ /* eMMC */
+ info.mmc_dev_type = MMC_IS_EMMC;
+ info.ocr_voltage = OCR_3_2_3_3;
+ err = mmc_init(&dw_mmc_ops, SDHCI_DEFAULT_CLOCK, MMC_BUS_WIDTH_8, MMC_FLAG_CMD23, &info);
+#else
+ /* SD */
+ info.mmc_dev_type = MMC_IS_SD;
+ info.ocr_voltage = OCR_3_2_3_3;
+ err = mmc_init(&dw_mmc_ops, SDHCI_DEFAULT_CLOCK, MMC_BUS_WIDTH_4, 0, &info);
+#endif
+ return err;
+}
#include <baikal_def.h>
#include <baikal_pvt.h>
-static uintptr_t pvt_get_reg_addr(const uintptr_t base, const unsigned offset)
+static uintptr_t pvt_get_reg_addr(const uintptr_t base, const unsigned int offset)
{
- unsigned i;
+ unsigned int i;
static const uintptr_t pvt_bases[] = {
#if defined(MMCA57_0_PVT_BASE)
MMCA57_0_PVT_BASE,
return 0;
}
-uint32_t pvt_read_reg(const uintptr_t base, const unsigned offset)
+uint32_t pvt_read_reg(const uintptr_t base, const unsigned int offset)
{
const uintptr_t reg_addr = pvt_get_reg_addr(base, offset);
- if (!reg_addr) {
+ if (reg_addr == 0) {
return 1;
}
#ifdef BAIKAL_QEMU
return mmio_read_32(reg_addr);
}
-uint32_t pvt_write_reg(const uintptr_t base, const unsigned offset, const uint32_t val)
+uint32_t pvt_write_reg(const uintptr_t base, const unsigned int offset, const uint32_t val)
{
const uintptr_t reg_addr = pvt_get_reg_addr(base, offset);
- if (!reg_addr) {
+ if (reg_addr == 0) {
return 1;
}
#ifndef BAIKAL_QEMU
/*
- * Copyright (c) 2020-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2020-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <baikal_sip_svc.h>
static int baikal_smc_flash_init(uint64_t *const data);
-static int baikal_smc_flash_position(const unsigned pos);
+static int baikal_smc_flash_position(const unsigned int pos);
static int baikal_smc_flash_pull(uint64_t *const data);
static int baikal_smc_flash_push(const uint64_t data0,
const uint64_t data1,
const uint64_t data2,
const uint64_t data3);
-static uint8_t flash_buf[1024] __aligned(8);
-static unsigned flash_buf_idx;
+static uint8_t flash_buf[1024] __aligned(8);
+static unsigned int flash_buf_idx;
int64_t baikal_smc_flash_handler(const uint32_t smc_fid,
const uint64_t x1,
const uint64_t x4,
uint64_t *data)
{
+ if ((smc_fid & BIT(30)) == 0) {
+ ERROR("%s: SMC32 (smc_fid 0x%x) is not supported\n", __func__, smc_fid);
+ return -1;
+ }
+
switch (smc_fid) {
case BAIKAL_SMC_FLASH_WRITE:
return bootflash_write(x1, flash_buf, x2);
return 0;
}
-static int baikal_smc_flash_position(const unsigned pos)
+static int baikal_smc_flash_position(const unsigned int pos)
{
if (pos > sizeof(flash_buf) - 4 * sizeof(uint64_t)) {
return -1;
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * The .data section gets copied from ROM to RAM at runtime.
- * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes
- * aligned regions in it.
+ * The .data section gets copied from ROM to RAM at runtime. Its LMA should be
+ * 16-byte aligned to allow efficient copying of 16-bytes aligned regions in it.
* Its VMA must be page-aligned as it marks the first read/write page.
*/
#define DATA_ALIGN 16
DRAM (rwx): ORIGIN = SEC_DRAM_BASE, LENGTH = SEC_DRAM_SIZE
}
-SECTIONS
-{
+SECTIONS {
. = BL1_RO_BASE;
+
ASSERT(. == ALIGN(PAGE_SIZE),
- "BL1_RO_BASE address is not aligned on a page boundary.")
+ "BL1_RO_BASE address is not aligned on a page boundary.")
#if SEPARATE_CODE_AND_RODATA
.text . : {
__TEXT_START__ = .;
+
*bl1_entrypoint.o(.text*)
*(SORT_BY_ALIGNMENT(.text*))
*(.vectors)
+
. = ALIGN(PAGE_SIZE);
+
__TEXT_END__ = .;
- } >ROM
+ } >ROM
- /* .ARM.extab and .ARM.exidx are only added because Clang need them */
- .ARM.extab . : {
+ /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
+ .ARM.extab . : {
*(.ARM.extab* .gnu.linkonce.armextab.*)
- } >ROM
+ } >ROM
- .ARM.exidx . : {
+ .ARM.exidx . : {
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } >ROM
+ } >ROM
.rodata . : {
__RODATA_START__ = .;
+
*(SORT_BY_ALIGNMENT(.rodata*))
- RODATA_COMMON
+ RODATA_COMMON
/*
* No need to pad out the .rodata section to a page boundary. Next is
* the .data section, which can mapped in ROM with the same memory
* attributes as the .rodata section.
*
- * Pad out to 16 bytes though as .data section needs to be 16 byte
- * aligned and lld does not align the LMA to the aligment specified
+ * Pad out to 16 bytes though as .data section needs to be 16-byte
+ * aligned and lld does not align the LMA to the alignment specified
* on the .data section.
*/
__RODATA_END__ = .;
- . = ALIGN(16);
+
+ . = ALIGN(16);
} >ROM
-#else
- ro . : {
+#else /* SEPARATE_CODE_AND_RODATA */
+ .ro . : {
__RO_START__ = .;
+
*bl1_entrypoint.o(.text*)
*(SORT_BY_ALIGNMENT(.text*))
*(SORT_BY_ALIGNMENT(.rodata*))
- RODATA_COMMON
+ RODATA_COMMON
*(.vectors)
+
__RO_END__ = .;
/*
- * Pad out to 16 bytes as .data section needs to be 16 byte aligned and
- * lld does not align the LMA to the aligment specified on the .data
- * section.
+ * Pad out to 16 bytes as the .data section needs to be 16-byte aligned
+ * and lld does not align the LMA to the alignment specified on the
+ * .data section.
*/
- . = ALIGN(16);
+ . = ALIGN(16);
} >ROM
-#endif
+#endif /* SEPARATE_CODE_AND_RODATA */
ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
- "cpu_ops not defined for this platform.")
+ "cpu_ops not defined for this platform.")
. = BL1_RW_BASE;
+
ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
- "BL1_RW_BASE address is not aligned on a page boundary.")
+ "BL1_RW_BASE address is not aligned on a page boundary.")
.data . : ALIGN(DATA_ALIGN) {
__DATA_START__ = .;
*(SORT_BY_ALIGNMENT(.data*))
__DATA_END__ = .;
} >RAM AT>ROM
+
__DATA_RAM_START__ = __DATA_START__;
__DATA_RAM_END__ = __DATA_END__;
} >RAM
ASSERT(__BSS_END__ < SCP_SERVICE_BASE,
- "BSS section has exceeded its limit.")
+ "BSS section has exceeded its limit.")
#if USE_COHERENT_MEM
/*
- * The base address of the coherent memory section must be page-aligned (4K)
- * to guarantee that the coherent data are stored on their own pages and
- * are not mixed with normal data. This is required to set up the correct
- * memory attributes for the coherent data page tables.
+ * The base address of the coherent memory section must be page-aligned to
+ * guarantee that the coherent data are stored on their own pages and are
+ * not mixed with normal data. This is required to set up the correct memory
+ * attributes for the coherent data page tables.
*/
- coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
+ .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
__COHERENT_RAM_START__ = .;
- *(tzfw_coherent_mem)
+ *(.tzfw_coherent_mem)
__COHERENT_RAM_END_UNALIGNED__ = .;
+
/*
- * Memory page(s) mapped to this section will be marked
- * as device memory. No other unexpected data must creep in.
- * Ensure the rest of the current memory page is unused.
+ * Memory page(s) mapped to this section will be marked as device
+ * memory. No other unexpected data must creep in. Ensure the rest of
+ * the current memory page is unused.
*/
. = ALIGN(PAGE_SIZE);
+
__COHERENT_RAM_END__ = .;
} >RAM
-#endif
+#endif /* USE_COHERENT_MEM */
__BL1_RAM_START__ = ADDR(.data);
__BL1_RAM_END__ = .;
* of BL1's actual content in Trusted ROM.
*/
__BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__;
+
ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT,
- "BL1's ROM content has exceeded its limit.")
+ "BL1's ROM content has exceeded its limit.")
__BSS_SIZE__ = SIZEOF(.bss);
#if USE_COHERENT_MEM
__COHERENT_RAM_UNALIGNED_SIZE__ =
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
-#endif
+#endif /* USE_COHERENT_MEM */
ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
/*
- * Copyright (c) 2020-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2020-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <arm_acle.h>
#include <crc.h>
-static inline uint16_t crc16iter(uint16_t crc) __attribute__((always_inline));
-static inline uint32_t crc32iter(uint32_t crc) __attribute__((always_inline));
-
uint16_t crc16(const void *data, size_t size, uint16_t crc)
{
const uint8_t *ptr = data;
- for (; size >= 8; size -= 8) {
- crc = crc16iter(crc ^= *ptr++ << 8);
- crc = crc16iter(crc ^= *ptr++ << 8);
- crc = crc16iter(crc ^= *ptr++ << 8);
- crc = crc16iter(crc ^= *ptr++ << 8);
- crc = crc16iter(crc ^= *ptr++ << 8);
- crc = crc16iter(crc ^= *ptr++ << 8);
- crc = crc16iter(crc ^= *ptr++ << 8);
- crc = crc16iter(crc ^= *ptr++ << 8);
- }
-
- for (; size; --size) {
- crc = crc16iter(crc ^= *ptr++ << 8);
+ while (size--) {
+ unsigned int i = 0;
+
+ crc ^= *ptr++ << 8;
+ while (i++ < 8) {
+ if (crc & 0x8000) {
+ crc = crc << 1 ^ 0x1021;
+ } else {
+ crc <<= 1;
+ }
+ }
}
return crc;
}
-static inline uint16_t crc16iter(uint16_t crc)
-{
- crc = crc << 1 ^ (0x1021 & ~((crc >> 15) - 1));
- crc = crc << 1 ^ (0x1021 & ~((crc >> 15) - 1));
- crc = crc << 1 ^ (0x1021 & ~((crc >> 15) - 1));
- crc = crc << 1 ^ (0x1021 & ~((crc >> 15) - 1));
- crc = crc << 1 ^ (0x1021 & ~((crc >> 15) - 1));
- crc = crc << 1 ^ (0x1021 & ~((crc >> 15) - 1));
- crc = crc << 1 ^ (0x1021 & ~((crc >> 15) - 1));
- crc = crc << 1 ^ (0x1021 & ~((crc >> 15) - 1));
- return crc;
-}
-
+/*
+ * compute CRC-32 using Arm intrinsic function
+ *
+ * This function is similar to tf_crc32() from common/tf_crc32.c.
+ * The main difference is crc32() allows input buffer to start from
+ * address 0 (which is important for checksumming contents of mailbox).
+ *
+ * Make sure to add a compile switch '-march=armv8-a+crc"
+ * for successful compilation of this file.
+ */
uint32_t crc32(const void *data, size_t size, uint32_t crc)
{
- const uint8_t *ptr = data;
-
- crc = ~crc;
-
- for (; size >= 8; size -= 8) {
- crc = crc32iter(crc ^= *ptr++);
- crc = crc32iter(crc ^= *ptr++);
- crc = crc32iter(crc ^= *ptr++);
- crc = crc32iter(crc ^= *ptr++);
- crc = crc32iter(crc ^= *ptr++);
- crc = crc32iter(crc ^= *ptr++);
- crc = crc32iter(crc ^= *ptr++);
- crc = crc32iter(crc ^= *ptr++);
- }
-
- for (; size; --size) {
- crc = crc32iter(crc ^= *ptr++);
+ uint32_t calc_crc = ~crc;
+ const unsigned char *local_buf = data;
+ size_t local_size = size;
+
+ /* Calculate CRC over byte data */
+ while (local_size != 0UL) {
+ calc_crc = __crc32b(calc_crc, *local_buf);
+ local_buf++;
+ local_size--;
}
- return ~crc;
-}
-
-static inline uint32_t crc32iter(uint32_t crc)
-{
- crc = crc >> 1 ^ (0xedb88320 & ~((crc & 1) - 1));
- crc = crc >> 1 ^ (0xedb88320 & ~((crc & 1) - 1));
- crc = crc >> 1 ^ (0xedb88320 & ~((crc & 1) - 1));
- crc = crc >> 1 ^ (0xedb88320 & ~((crc & 1) - 1));
- crc = crc >> 1 ^ (0xedb88320 & ~((crc & 1) - 1));
- crc = crc >> 1 ^ (0xedb88320 & ~((crc & 1) - 1));
- crc = crc >> 1 ^ (0xedb88320 & ~((crc & 1) - 1));
- crc = crc >> 1 ^ (0xedb88320 & ~((crc & 1) - 1));
- return crc;
+ return ~calc_crc;
}
#define SWPORTA_DR 0x00
#define SWPORTA_DDR 0x04
-void gpio_dir_clr(const uintptr_t base, const unsigned pin)
+void gpio_dir_clr(const uintptr_t base, const unsigned int pin)
{
assert(pin < 32);
mmio_clrbits_32(base + SWPORTA_DDR, 1 << pin);
}
-void gpio_dir_set(const uintptr_t base, const unsigned pin)
+void gpio_dir_set(const uintptr_t base, const unsigned int pin)
{
assert(pin < 32);
mmio_setbits_32(base + SWPORTA_DDR, 1 << pin);
}
-void gpio_out_rst(const uintptr_t base, const unsigned pin)
+void gpio_out_rst(const uintptr_t base, const unsigned int pin)
{
assert(pin < 32);
mmio_clrbits_32(base + SWPORTA_DR, 1 << pin);
}
-void gpio_out_set(const uintptr_t base, const unsigned pin)
+void gpio_out_set(const uintptr_t base, const unsigned int pin)
{
assert(pin < 32);
/*
- * Copyright (c) 2020-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2020-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define IC_DATA_CMD_STOP BIT(9)
#define IC_RAW_INTR_STAT_TX_ABRT BIT(6)
-#define IC_RAW_INTR_STAT_STOP_DET BIT(9)
#define IC_ENABLE_ENABLE BIT(0)
#define IC_ENABLE_STATUS_IC_EN BIT(0)
-#define IC_CLK 166
-#define NANO_TO_MICRO 1000
#define MIN_FS_SCL_HIGHTIME 600
#define MIN_FS_SCL_LOWTIME 1300
int i2c_txrx(const uintptr_t base,
- const unsigned addr,
+ const unsigned int iclk,
+ const unsigned int targetaddr,
const void *const txbuf,
- const unsigned txbufsize,
+ const unsigned int txbufsize,
void *const rxbuf,
- const unsigned rxbufsize)
+ const unsigned int rxbufsize)
{
uint64_t activity_timeout;
int err;
volatile struct i2c_regs *const i2cregs = (volatile struct i2c_regs *const)base;
- unsigned rxedsize = 0;
+ unsigned int rxedsize = 0;
uint8_t *const rxptr = (uint8_t *)rxbuf;
- unsigned txedsize = 0;
+ unsigned int txedsize = 0;
const uint8_t *const txptr = (uint8_t *)txbuf;
assert(i2cregs != NULL);
- assert(addr <= 0x7f);
+ assert(targetaddr <= 0x7f);
assert(txbuf != NULL || !txbufsize);
assert(rxbuf != NULL || !rxbufsize);
i2cregs->ic_enable = 0;
i2cregs->ic_con = IC_CON_IC_SLAVE_DISABLE | IC_CON_SPEED | IC_CON_MASTER_MODE;
- i2cregs->ic_tar = addr;
+ i2cregs->ic_tar = targetaddr;
i2cregs->ic_rx_tl = 0;
i2cregs->ic_tx_tl = 0;
i2cregs->ic_intr_mask = 0;
- i2cregs->ic_fs_scl_hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
- i2cregs->ic_fs_scl_lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
+ i2cregs->ic_fs_scl_hcnt = ((uint64_t)iclk * MIN_FS_SCL_HIGHTIME + 1000000000 - 1) / 1000000000;
+ assert(i2cregs->ic_fs_scl_hcnt + 5 > i2cregs->ic_fs_spklen);
+ i2cregs->ic_fs_scl_lcnt = ((uint64_t)iclk * MIN_FS_SCL_LOWTIME + 1000000000 - 1) / 1000000000;
+ assert(i2cregs->ic_fs_scl_lcnt + 7 > i2cregs->ic_fs_spklen);
i2cregs->ic_enable = IC_ENABLE_ENABLE;
activity_timeout = timeout_init_us(100000);
for (;;) {
- const unsigned ic_status = i2cregs->ic_status;
+ const unsigned int ic_status = i2cregs->ic_status;
if (rxedsize < rxbufsize && (ic_status & IC_STATUS_RFNE)) {
rxptr[rxedsize++] = i2cregs->ic_data_cmd;
err = -1;
break;
}
- } else if ( (ic_status & IC_STATUS_TFE) &&
- !(ic_status & IC_STATUS_MST_ACTIVITY)) {
+ } else if ((ic_status & IC_STATUS_TFE) &&
+ !(ic_status & IC_STATUS_MST_ACTIVITY)) {
err = 0;
break;
}
i2cregs->ic_enable = 0;
- while (i2cregs->ic_enable_status & IC_ENABLE_STATUS_IC_EN);
+ while (i2cregs->ic_enable_status & IC_ENABLE_STATUS_IC_EN)
+ ;
if (err) {
return -1;
/*
- * Copyright (c) 2018-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2018-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define SPI_MAX_READ UL(0x10000)
#define SPI_MAX_WRITE UL(256) /* (3, 256) Page Program */
-static unsigned adr_mode;
+static unsigned int adr_mode;
-static int transfer(const unsigned line,
+static int transfer(const unsigned int line,
void *cmd_, uint32_t cmd_len,
void *tx_, uint32_t tx_len,
void *rx_, uint32_t rx_len)
case CMD_FLASH_READ:
out = buf;
lenout = lenbuf;
+ /* fallthrough */
case CMD_FLASH_SSE:
case CMD_FLASH_SE:
if (adr_mode == ADR_MODE_4BYTE) {
{
int err;
+#ifndef IMAGE_BL1
INFO("SPI: default parameters\n");
INFO("SPI: clock div: %u\n", BAIKAL_BOOT_SPI_BAUDR);
#ifdef BAIKAL_BOOT_SPI_CS_GPIO_PIN
INFO("SPI: flash CS#: %u\n", BAIKAL_BOOT_SPI_CS_GPIO_PIN);
#endif
INFO("SPI: flash size: %u MiB\n", BAIKAL_BOOT_SPI_SIZE / 1024 / 1024);
+#endif
SPI_SPIENR = SPI_SPIENR_SPI_DE;
SPI_CTRLR0 = 7 << SPI_DFS_OFFSET;
err = spi_flash_detect(line);
if (err) {
- ERROR("SPI: flash chip not found\n");
+ ERROR("SPI: not found\n");
return err;
}
#include <stddef.h>
#include <stdint.h>
-void bootflash_init(void);
-int bootflash_erase(uint32_t addr, size_t size);
-int bootflash_read( uint32_t addr, void *buf, size_t size);
-int bootflash_write(uint32_t addr, void *data, size_t size);
+int bootflash_init(void);
+int bootflash_erase(uint32_t addr, size_t size);
+int bootflash_read(uint32_t addr, void *buf, size_t size);
+int bootflash_write(uint32_t addr, void *data, size_t size);
#endif /* BAIKAL_BOOTFLASH_H */
bool fdt_node_is_enabled(const void *fdt, const int nodeoffset);
void fdt_memory_node_set(void *fdt,
const uint64_t region_descs[][2],
- const unsigned region_num);
+ const unsigned int region_num);
#endif /* BAIKAL_FDT_H */
--- /dev/null
+/*
+ * Copyright (c) 2023, Baikal Electronics, JSC. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BAIKAL_MSHC_H
+#define BAIKAL_MSHC_H
+
+#include <drivers/mmc.h>
+
+#define SDHCI_INIT_CLOCK (300 * 1000)
+#define SDHCI_DEFAULT_CLOCK (50 * 1000 * 1000)
+#define SDHCI_DEFAULT_BLOCK_SIZE 512
+
+/* Registers */
+#define SDHCI_DMA_ADDRESS 0x00
+#define SDHCI_ARGUMENT2 0x00
+#define SDHCI_32BIT_BLK_CNT 0x00
+
+#define SDHCI_BLOCK_SIZE 0x04
+#define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xfff))
+
+#define SDHCI_16BIT_BLK_CNT 0x06
+
+#define SDHCI_ARGUMENT 0x08
+
+#define SDHCI_TRANSFER_MODE 0x0c
+#define SDHCI_TRNS_DMA (1 << 0)
+#define SDHCI_TRNS_BLK_CNT_EN (1 << 1)
+#define SDHCI_TRNS_AUTO_CMD12 (1 << 2)
+#define SDHCI_TRNS_AUTO_CMD23 (1 << 3)
+#define SDHCI_TRNS_AUTO_SEL 0x0c
+#define SDHCI_TRNS_READ (1 << 4)
+#define SDHCI_TRNS_MULTI (1 << 5)
+
+#define SDHCI_COMMAND 0x0e
+#define SDHCI_CMD_RESP_NONE 0x00
+#define SDHCI_CMD_RESP_LONG 0x01
+#define SDHCI_CMD_RESP_SHORT 0x02
+#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
+
+#define SDHCI_RESPONSE 0x10
+#define SDHCI_RESPONSE_0 (SDHCI_RESPONSE + 0x4 * 0)
+#define SDHCI_RESPONSE_1 (SDHCI_RESPONSE + 0x4 * 1)
+#define SDHCI_RESPONSE_2 (SDHCI_RESPONSE + 0x4 * 2)
+#define SDHCI_RESPONSE_3 (SDHCI_RESPONSE + 0x4 * 3)
+
+#define SDHCI_BUFFER 0x20
+
+#define SDHCI_PRESENT_STATE 0x24
+#define SDHCI_CMD_INHIBIT (1 << 0)
+#define SDHCI_DATA_INHIBIT (1 << 1)
+#define SDHCI_DATA_74 0x000000f0
+#define SDHCI_DOING_WRITE (1 << 8)
+#define SDHCI_DOING_READ (1 << 9)
+#define SDHCI_SPACE_AVAILABLE (1 << 10)
+#define SDHCI_DATA_AVAILABLE (1 << 11)
+#define SDHCI_CARD_PRESENT (1 << 16)
+#define SDHCI_CARD_PRES_SHIFT 16
+#define SDHCI_CD_STABLE (1 << 17)
+#define SDHCI_CD_LVL (1 << 18)
+#define SDHCI_CD_LVL_SHIFT 18
+#define SDHCI_WRITE_PROTECT (1 << 19)
+#define SDHCI_DATA_30 0x00f00000
+#define SDHCI_DATA_LVL_SHIFT 20
+#define SDHCI_DATA_0_LVL_MASK 0x00100000
+#define SDHCI_CMD_LVL (1 << 24)
+#define SDHCI_VOLTAGE_STABLE (1 << 25)
+
+#define SDHCI_HOST_CONTROL 0x28
+#define SDHCI_CTRL_LED 0x01
+#define SDHCI_CTRL_4BITBUS 0x02
+#define SDHCI_CTRL_HISPD 0x04
+#define SDHCI_CTRL_DMA_MASK 0x18
+#define SDHCI_CTRL_SDMA 0x00
+#define SDHCI_CTRL_ADMA1 0x08
+#define SDHCI_CTRL_ADMA32 0x10
+#define SDHCI_CTRL_ADMA64 0x18
+#define SDHCI_CTRL_ADMA3 0x18
+#define SDHCI_CTRL_8BITBUS 0x20
+#define SDHCI_CTRL_CDTEST_INS 0x40
+#define SDHCI_CTRL_CDTEST_EN 0x80
+
+#define SDHCI_POWER_CONTROL 0x29
+#define SDHCI_POWER_OFF (0x0 << 0)
+#define SDHCI_POWER_ON (0x1 << 0)
+#define SDHCI_POWER_180 (0x5 << 1)
+#define SDHCI_POWER_300 (0x6 << 1)
+#define SDHCI_POWER_330 (0x7 << 1)
+#define SDHCI_EMMC_POWER_120 (0x5 << 1)
+#define SDHCI_EMMC_POWER_180 (0x6 << 1)
+#define SDHCI_EMMC_POWER_300 (0x7 << 1)
+#define SDHCI_POWER2_ON (0x1 << 4)
+#define SDHCI_POWER2_120 (0x4 << 5)
+#define SDHCI_POWER2_180 (0x5 << 5)
+
+#define SDHCI_BLOCK_GAP_CONTROL 0x2a
+
+#define SDHCI_WAKE_UP_CONTROL 0x2b
+#define SDHCI_WAKE_ON_INT 0x01
+#define SDHCI_WAKE_ON_INSERT 0x02
+#define SDHCI_WAKE_ON_REMOVE 0x04
+
+#define SDHCI_CLOCK_CONTROL 0x2c
+#define SDHCI_CLOCK_FREG_SELECT_LOW (0xff << 8)
+#define SDHCI_CLOCK_FREG_SELECT_HI (3 << 6)
+#define SDHCI_CLOCK_GEN_SELECT (1 << 5)
+#define SDHCI_CLOCK_RESERVED (1 << 4)
+#define SDHCI_CLOCK_PLL_EN (1 << 3)
+#define SDHCI_CLOCK_CARD_EN (1 << 2)
+#define SDHCI_CLOCK_STABLE (1 << 1)
+#define SDHCI_CLOCK_EN (1 << 0)
+
+#define SDHCI_TIMEOUT_CONTROL 0x2e
+#define SDHCI_TIMEOUT_DEFAULT 0xe
+
+#define SDHCI_SOFTWARE_RESET 0x2f
+#define SDHCI_RESET_ALL 0x01
+#define SDHCI_RESET_CMD 0x02
+#define SDHCI_RESET_DATA 0x04
+
+#define SDHCI_INT_STATUS 0x30
+#define SDHCI_INT_ENABLE 0x34
+#define SDHCI_SIGNAL_ENABLE 0x38
+#define SDHCI_INT_RESPONSE (1 << 0)
+#define SDHCI_INT_DATA_END (1 << 1)
+#define SDHCI_INT_BLK_GAP (1 << 2)
+#define SDHCI_INT_DMA_END (1 << 3)
+#define SDHCI_INT_SPACE_AVAIL (1 << 4)
+#define SDHCI_INT_DATA_AVAIL (1 << 5)
+#define SDHCI_INT_CARD_INSERT (1 << 6)
+#define SDHCI_INT_CARD_REMOVE (1 << 7)
+#define SDHCI_INT_CARD_INT (1 << 8)
+#define SDHCI_INT_RETUNE (1 << 12)
+#define SDHCI_INT_FX (1 << 13)
+#define SDHCI_INT_CQE (1 << 14)
+#define SDHCI_INT_ERROR (1 << 15)
+
+#define SDHCI_ERR_STATUS 0x32
+#define SDHCI_ERR_ENABLE 0x36
+#define SDHCI_ERR_SIGNAL_ENABLE 0x3a
+#define SDHCI_ERR_TIMEOUT (1 << 0)
+#define SDHCI_ERR_CRC (1 << 1)
+#define SDHCI_ERR_END_BIT (1 << 2)
+#define SDHCI_ERR_INDEX (1 << 3)
+#define SDHCI_ERR_DATA_TIMEOUT (1 << 4)
+#define SDHCI_ERR_DATA_CRC (1 << 5)
+#define SDHCI_ERR_DATA_END_BIT (1 << 6)
+#define SDHCI_ERR_BUS_POWER (1 << 7)
+#define SDHCI_ERR_AUTO_CMD_ERR (1 << 8)
+#define SDHCI_ERR_ADMA (1 << 9)
+#define SDHCI_ERR_TUNING (1 << 10)
+#define SDHCI_ERR_RESP (1 << 11)
+#define SDHCI_ERR_BOOT (1 << 12)
+
+#define SDHCI_AUTO_CMD_STATUS 0x3c
+#define SDHCI_AUTO_CMD_TIMEOUT 0x00000002
+#define SDHCI_AUTO_CMD_CRC 0x00000004
+#define SDHCI_AUTO_CMD_END_BIT 0x00000008
+#define SDHCI_AUTO_CMD_INDEX 0x00000010
+
+#define SDHCI_HOST_CONTROL2 0x3e
+#define SDHCI_CTRL_UHS_MASK 0x0007
+#define SDHCI_CTRL_UHS_SDR12 0x0000
+#define SDHCI_CTRL_UHS_SDR25 0x0001
+#define SDHCI_CTRL_UHS_SDR50 0x0002
+#define SDHCI_CTRL_UHS_SDR104 0x0003
+#define SDHCI_CTRL_UHS_DDR50 0x0004
+#define SDHCI_CTRL_HS400 0x0007
+#define SDHCI_CTRL_VDD_180 0x0008
+#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
+#define SDHCI_CTRL_DRV_TYPE_B 0x0000
+#define SDHCI_CTRL_DRV_TYPE_A 0x0010
+#define SDHCI_CTRL_DRV_TYPE_C 0x0020
+#define SDHCI_CTRL_DRV_TYPE_D 0x0030
+#define SDHCI_CTRL_EXEC_TUNING 0x0040
+#define SDHCI_CTRL_TUNED_CLK 0x0080
+#define SDHCI_CMD23_ENABLE 0x0800
+#define SDHCI_CTRL_V4_MODE 0x1000
+#define SDHCI_CTRL_64BIT_ADDR 0x2000
+#define SDHCI_CTRL_ASYNC 0x4000
+#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
+
+#define SDHCI_CAPABILITIES 0x40
+#define SDHCI_TIMEOUT_CLK_MASK 0x0000003f
+#define SDHCI_TIMEOUT_CLK_SHIFT 0
+#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
+#define SDHCI_CLOCK_BASE_MASK 0x00003f00
+#define SDHCI_CLOCK_V3_BASE_MASK 0x0000ff00
+#define SDHCI_CLOCK_BASE_SHIFT 8
+#define SDHCI_MAX_BLOCK_MASK 0x00030000
+#define SDHCI_MAX_BLOCK_SHIFT 16
+#define SDHCI_CAN_DO_8BIT 0x00040000
+#define SDHCI_CAN_DO_ADMA2 0x00080000
+#define SDHCI_CAN_DO_ADMA1 0x00100000
+#define SDHCI_CAN_DO_HISPD 0x00200000
+#define SDHCI_CAN_DO_SDMA 0x00400000
+#define SDHCI_CAN_DO_SUSPEND 0x00800000
+#define SDHCI_CAN_VDD_330 0x01000000
+#define SDHCI_CAN_VDD_300 0x02000000
+#define SDHCI_CAN_VDD_180 0x04000000
+#define SDHCI_CAN_64BIT_V4 0x08000000
+#define SDHCI_CAN_64BIT 0x10000000
+#define SDHCI_SUPPORT_SDR50 0x00000001
+#define SDHCI_SUPPORT_SDR104 0x00000002
+#define SDHCI_SUPPORT_DDR50 0x00000004
+#define SDHCI_SUPPORT_UHS2 0x00000008
+#define SDHCI_DRIVER_TYPE_A 0x00000010
+#define SDHCI_DRIVER_TYPE_C 0x00000020
+#define SDHCI_DRIVER_TYPE_D 0x00000040
+#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000f00
+#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8
+#define SDHCI_USE_SDR50_TUNING 0x00002000
+#define SDHCI_RETUNING_MODE_MASK 0x0000c000
+#define SDHCI_RETUNING_MODE_SHIFT 14
+#define SDHCI_CLOCK_MUL_MASK 0x00ff0000
+#define SDHCI_CLOCK_MUL_SHIFT 16
+#define SDHCI_CAN_DO_ADMA3 0x08000000
+#define SDHCI_SUPPORT_VDD2_18 0x10000000
+#define SDHCI_SUPPORT_HS400 0x80000000
+
+#define SDHCI_CAPABILITIES_1 0x44
+
+#define SDHCI_MAX_CURRENT 0x48
+#define SDHCI_MAX_CURRENT_LIMIT 0xff
+#define SDHCI_MAX_CURRENT_330_MASK 0x0000ff
+#define SDHCI_MAX_CURRENT_330_SHIFT 0
+#define SDHCI_MAX_CURRENT_300_MASK 0x00ff00
+#define SDHCI_MAX_CURRENT_300_SHIFT 8
+#define SDHCI_MAX_CURRENT_180_MASK 0xff0000
+#define SDHCI_MAX_CURRENT_180_SHIFT 16
+#define SDHCI_MAX_CURRENT_MULTIPLIER 4
+
+/* 4c-4f reserved for more max current */
+
+#define SDHCI_SET_ACMD12_ERROR 0x50
+#define SDHCI_SET_INT_ERROR 0x52
+
+#define SDHCI_ADMA_ERROR 0x54
+
+/* 55-57 reserved */
+
+#define SDHCI_ADMA_ADDRESS 0x58
+#define SDHCI_ADMA_ADDRESS_HI 0x5c
+
+/* 60-fb reserved */
+
+#define SDHCI_PRESET_INIT 0x60
+#define SDHCI_PRESET_DS 0x62
+#define SDHCI_PRESET_HS 0x64
+#define SDHCI_PRESET_FOR_SDR12 0x66
+#define SDHCI_PRESET_FOR_SDR25 0x68
+#define SDHCI_PRESET_FOR_SDR50 0x6a
+#define SDHCI_PRESET_FOR_SDR104 0x6c
+#define SDHCI_PRESET_FOR_DDR50 0x6e
+#define SDHCI_PRESET_FOR_HS400 0x74
+#define SDHCI_PRESET_DRV_MASK 0xc000
+#define SDHCI_PRESET_DRV_SHIFT 14
+#define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400
+#define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10
+#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3ff
+#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0
+
+#define SDHCI_SLOT_INT_STATUS 0xfc
+
+#define SDHCI_HOST_VERSION 0xfe
+#define SDHCI_VENDOR_VER_MASK 0xff00
+#define SDHCI_VENDOR_VER_SHIFT 8
+#define SDHCI_SPEC_VER_MASK 0x00ff
+#define SDHCI_SPEC_VER_SHIFT 0
+#define SDHCI_SPEC_100 0
+#define SDHCI_SPEC_200 1
+#define SDHCI_SPEC_300 2
+#define SDHCI_SPEC_400 3
+#define SDHCI_SPEC_410 4
+#define SDHCI_SPEC_420 5
+
+#define SDHCI_MSHC_VER 0x504
+#define SDHCI_MSHC_CTRL 0x508
+#define SDHCI_EMMC_CONTROL 0x52c
+#define SDHCI_EMMC_TYPE_MMC (1 << 0)
+#define SDHCI_EMMC_CRC_DISABLE (1 << 1)
+#define SDHCI_EMMC_DONT_RESET (1 << 2)
+
+typedef struct {
+ uint32_t size :11 - 0 + 1; /* 11 - 0 */
+ uint32_t boundary :14 - 12 + 1; /* 14 - 12 */
+ uint32_t _ :1; /* 15 */
+} reg_block_t;
+
+typedef struct {
+ uint32_t dma_en :1; /* 0 */
+ /* 0 - disable */
+ /* 1 - enable */
+ uint32_t block_cnt_en :1; /* 1 */
+ /* 0 - disable */
+ /* 1 - enable */
+ uint32_t auto_cmd :3 - 2 + 1; /* 3 - 2 */
+ /* 0 - disable */
+ /* 1 - cmd12_enable */
+ /* 2 - cmd23_enable */
+ /* 3 - auto_sel */
+ uint32_t xfer_dir :1; /* 4 */
+ /* 0 - write */
+ /* 1 - read */
+ uint32_t multi_block :1; /* 5 */
+ /* 0 - single */
+ /* 1 - multi */
+ uint32_t resp_type :1; /* 6 */
+ /* 0 - R1, memory */
+ /* 1 - R5, sdio */
+ uint32_t resp_err_chk_en :1; /* 7 */
+ /* 0 - disable */
+ /* 1 - enable */
+ uint32_t resp_irq_dis :1; /* 8 */
+ /* 0 - enable */
+ /* 1 - disable */
+ uint32_t _ :15 - 9 + 1; /* 15 - 9 */
+} reg_mode_t;
+
+typedef struct {
+ uint32_t resp_type :1 - 0 + 1; /* 1 - 0 */
+ /* 0 - noresp */
+ /* 1 - len136 */
+ /* 2 - len48 */
+ /* 3 - len48b */
+ uint32_t flag :1; /* 2 */
+ /* 0 - main */
+ /* 1 - sub */
+ uint32_t crc_chk :1; /* 3 */
+ /* 0 - no check */
+ /* 1 - check */
+ uint32_t index_chk :1; /* 4 */
+ /* 0 - no check */
+ /* 1 - check */
+ uint32_t data_present :1; /* 5 */
+ /* 0 - no data */
+ /* 1 - data */
+ uint32_t type :7 - 6 + 1; /* 7 - 6 */
+ /* 0 - normal */
+ /* 1 - suspend */
+ /* 2 - resume */
+ /* 3 - abort */
+ uint32_t index :13 - 8 + 1; /* 13 - 8 */
+ uint32_t _ :15 - 14 + 1; /* 15 - 14 */
+} reg_cmd_t;
+
+typedef struct {
+ uint32_t cmd_busy :1; /* 0 */
+ uint32_t data_busy :1; /* 1 */
+ uint32_t data_active :1; /* 2 */
+ uint32_t re_tune :1; /* 3 */
+ uint32_t dat_line_7_4 :7 - 4 + 1; /* 7 - 4 */
+ uint32_t wr_active :1; /* 8 */
+ uint32_t rd_active :1; /* 9 */
+ uint32_t buf_wr_en :1; /* 10 */
+ uint32_t buf_rd_en :1; /* 11 */
+ uint32_t _ :15 - 12 + 1; /* 15 - 12 */
+ uint32_t card_inserted :1; /* 16 */
+ uint32_t card_stable :1; /* 17 */
+ uint32_t card_detect :1; /* 18 */
+ uint32_t wr_protect :1; /* 19 */
+ uint32_t dat_line_3_0 :23 - 20 + 1; /* 23 - 20 */
+ uint32_t cmd_line :1; /* 24 */
+ uint32_t voltage_stable :1; /* 25 */
+ uint32_t __ :1; /* 26 */
+ uint32_t cmd_err :1; /* 27 */
+ uint32_t sub_cmd :1; /* 28 */
+ uint32_t dormant :1; /* 29 */
+ uint32_t sync :1; /* 30 */
+ uint32_t uhs2 :1; /* 31 */
+} reg_state_t;
+
+typedef struct {
+ uint32_t vdd1_on :1; /* 0 */
+ uint32_t vdd1 :3 - 1 + 1; /* 3 - 1 */
+ uint32_t vdd2_on :1; /* 4 */
+ uint32_t vdd2 :7 - 5 + 1; /* 7 - 5 */
+} reg_pwr_t;
+
+typedef struct {
+ uint32_t int_en :1; /* 0 */
+ uint32_t int_ready :1; /* 1 */
+ uint32_t ext_en :1; /* 2 */
+ uint32_t pll_en :1; /* 3 */
+ uint32_t _ :1; /* 4 */
+ uint32_t select :1; /* 5 */
+ uint32_t freq_hi :7 - 6 + 1; /* 7 - 6 */
+ uint32_t freq_low :15 - 8 + 1; /* 15 - 8 */
+} reg_clk_t;
+
+typedef struct {
+ uint32_t all :1; /* 0 */
+ uint32_t cmd :1; /* 1 */
+ uint32_t data :1; /* 2 */
+ uint32_t _ :7 - 3 + 1; /* 7 - 3 */
+} reg_reset_t;
+
+typedef struct {
+ uint32_t cmd :1; /* 0 */
+ uint32_t xfer :1; /* 1 */
+ uint32_t bgap :1; /* 2 */
+ uint32_t dma :1; /* 3 */
+ uint32_t buf_wr :1; /* 4 */
+ uint32_t buf_rd :1; /* 5 */
+ uint32_t card_insert :1; /* 6 */
+ uint32_t card_remove :1; /* 7 */
+ uint32_t card_irq :1; /* 8 */
+ uint32_t _ :11 - 9 + 1; /* 11 - 9 */
+ uint32_t tune :1; /* 12 */
+ uint32_t fx :1; /* 13 */
+ uint32_t cqe :1; /* 14 */
+ uint32_t err :1; /* 15 */
+} reg_int_t;
+
+typedef struct {
+ uint32_t led :1; /* 0 */
+ /* 0 - off */
+ /* 1 - on */
+ uint32_t width :1; /* 1 */
+ /* 0 - 1-bit */
+ /* 1 - 4-bit */
+ uint32_t speed :1; /* 2 */
+ /* 0 - normal */
+ /* 1 - high */
+ uint32_t dma :4 - 3 + 1; /* 4 - 3 */
+ /* 0 - sdma */
+ /* 2 - adma2 */
+ /* 3 - adma3 */
+ uint32_t ext_width :1; /* 5 */
+ /* 0 - default */
+ /* 1 - 8-bit */
+ uint32_t detect_lvl :1; /* 6 */
+ uint32_t detect_sig :1; /* 7 */
+} reg_ctl1_t;
+
+typedef struct {
+ uint32_t mode :2 - 0 + 1; /* 2 - 0 */
+ /* 0 - sdr12 */
+ /* 1 - sdr25 */
+ /* 2 - sdr50 */
+ /* 3 - sdr104 */
+ /* 4 - ddr50 */
+ /* 7 - uhs2 */
+ uint32_t signal :1; /* 3 */
+ /* 0 - 3.3V */
+ /* 1 - 1.8V */
+ uint32_t strength :1; /* TODO: 2? 5 - 4 */
+ /* 0 - TypeB */
+ /* 1 - TypeA */
+ /* 2 - TypeC */
+ /* 3 - TypeD */
+ uint32_t tune :1; /* 6 */
+ /* 0 - not */
+ /* 1 - execut */
+ uint32_t sample :1; /* 7 */
+ /* 0 - fixed clock */
+ /* 1 - tuned clock */
+ uint32_t _ :9 - 8 + 1; /* 9 - 8 */
+ uint32_t adma2_mode :1; /* 10 */
+ /* 0 - 16bit data len */
+ /* 1 - 26bit data len */
+ uint32_t cmd32 :1; /* 11 */
+ /* 0 - off */
+ /* 1 - on */
+ uint32_t version :1; /* 12 */
+ uint32_t __ :1; /* 13 */
+ uint32_t async :1; /* 14 */
+ /* 0 - off */
+ /* 1 - on */
+ uint32_t preset :1; /* 15 */
+} reg_ctl2_t;
+
+#define WAIT(X) ({ \
+ int Ret = 0; \
+ int Try = 100 * 1000; \
+ while (X) { \
+ if (!Try--) { \
+ Ret = -1; \
+ break; \
+ } \
+ udelay(1); \
+ }; \
+ Ret; \
+})
+
+enum SpeedMode {
+ SD_DEFAULT,
+ SD_HIGH,
+ SD_12,
+ SD_25,
+ SD_50,
+ SD_104,
+ DD_50
+};
+
+enum CmdType {
+ SdCommandTypeBc, /* Broadcast commands, no response */
+ SdCommandTypeBcr, /* Broadcast commands with response */
+ SdCommandTypeAc, /* Addressed(point-to-point) commands */
+ SdCommandTypeAdtc /* Addressed(point-to-point) data transfer commands */
+};
+
+enum RespType {
+ SdResponseTypeNo,
+ SdResponseTypeR1,
+ SdResponseTypeR1b,
+ SdResponseTypeR2,
+ SdResponseTypeR3,
+ SdResponseTypeR4,
+ SdResponseTypeR5,
+ SdResponseTypeR5b,
+ SdResponseTypeR6,
+ SdResponseTypeR7
+};
+
+typedef struct dw_mshc_params {
+ uintptr_t base;
+ int clk;
+ int width;
+ int flags;
+ enum mmc_device_type mmc_dev_type;
+} dw_mshc_params_t;
+
+int dw_mshc_init(void);
+int dw_mshc_read(uint32_t adr, void *dst, size_t size);
+int dw_mshc_write(uint32_t adr, void *src, size_t size);
+int dw_mshc_erase(uint32_t adr, size_t size);
+void dw_mshc_off(void);
+
+#define DIV_ROUND_UP(n, d) ((n) / (d) + !!((n) % (d)))
+#define ROUND_UP2(n, d) (((n) / (d) + !!((n) % (d))) * d)
+#define ROUND_DOWN2(n, d) (((n) / (d)) * (d))
+#define ROUND_UP(n) ROUND_UP2((n), MMC_BLOCK_SIZE)
+#define ROUND_DOWN(n) ROUND_DOWN2((n), MMC_BLOCK_SIZE)
+
+#endif /* BAIKAL_MSHC_H */
#define PVT_READ 0
#define PVT_WRITE 1
-uint32_t pvt_read_reg(const uintptr_t base, const unsigned offset);
-uint32_t pvt_write_reg(const uintptr_t base, const unsigned offset, const uint32_t val);
+uint32_t pvt_read_reg(const uintptr_t base, const unsigned int offset);
+uint32_t pvt_write_reg(const uintptr_t base, const unsigned int offset, const uint32_t val);
#endif /* BAIKAL_PVT_H */
/*
- * Copyright (c) 2020-2022, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2020-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
-#define BAIKAL_SMC_LCRU_ID 0x82000000
-#define BAIKAL_SMC_PVT_ID (BAIKAL_SMC_LCRU_ID + 0x001)
-#define BAIKAL_SMC_FLASH (BAIKAL_SMC_LCRU_ID + 0x002)
-#define BAIKAL_SMC_VDU_UPDATE (BAIKAL_SMC_LCRU_ID + 0x100)
-#define BAIKAL_SMC_SCP_LOG_DISABLE (BAIKAL_SMC_LCRU_ID + 0x200)
-#define BAIKAL_SMC_SCP_LOG_ENABLE (BAIKAL_SMC_LCRU_ID + 0x201)
-#define BAIKAL_SMC_VDEC_SMMU_SET_CACHE (BAIKAL_SMC_LCRU_ID + 0x300)
-#define BAIKAL_SMC_VDEC_SMMU_GET_CACHE (BAIKAL_SMC_LCRU_ID + 0x301)
-#define BAIKAL_SMC_CLK (BAIKAL_SMC_LCRU_ID + 0x400)
-
-#define BAIKAL_SMC_CLK_ROUND (BAIKAL_SMC_CLK + 0)
-#define BAIKAL_SMC_CLK_SET (BAIKAL_SMC_CLK + 1)
-#define BAIKAL_SMC_CLK_GET (BAIKAL_SMC_CLK + 2)
-#define BAIKAL_SMC_CLK_ENABLE (BAIKAL_SMC_CLK + 3)
-#define BAIKAL_SMC_CLK_DISABLE (BAIKAL_SMC_CLK + 4)
-#define BAIKAL_SMC_CLK_IS_ENABLED (BAIKAL_SMC_CLK + 5)
-
-#define BAIKAL_SMC_FLASH_WRITE (BAIKAL_SMC_FLASH + 0)
-#define BAIKAL_SMC_FLASH_READ (BAIKAL_SMC_FLASH + 1)
-#define BAIKAL_SMC_FLASH_ERASE (BAIKAL_SMC_FLASH + 2)
-#define BAIKAL_SMC_FLASH_PUSH (BAIKAL_SMC_FLASH + 3)
-#define BAIKAL_SMC_FLASH_PULL (BAIKAL_SMC_FLASH + 4)
-#define BAIKAL_SMC_FLASH_POSITION (BAIKAL_SMC_FLASH + 5)
-#define BAIKAL_SMC_FLASH_INIT (BAIKAL_SMC_FLASH + 6)
-#define BAIKAL_SMC_FLASH_LOCK (BAIKAL_SMC_FLASH + 7)
-
-#define BAIKAL_SMC_GMAC (BAIKAL_SMC_LCRU_ID + 0x500)
-#define BAIKAL_SMC_GMAC_DIV2_ENABLE (BAIKAL_SMC_GMAC + 0)
-#define BAIKAL_SMC_GMAC_DIV2_DISABLE (BAIKAL_SMC_GMAC + 1)
-
-#define BAIKAL_SMC_LSP_MUX (BAIKAL_SMC_LCRU_ID + 0x600)
+/* TODO: TF-A uses [0xc2000000:0xc200001f] range for PMF calls */
+#define BAIKAL_SMC_CMU_CMD 0xc2000000
+#define BAIKAL_SMC_PVT_CMD 0xc2000001
+#define BAIKAL_SMC_FLASH_WRITE 0xc2000002
+#define BAIKAL_SMC_FLASH_READ 0xc2000003
+#define BAIKAL_SMC_FLASH_ERASE 0xc2000004
+#define BAIKAL_SMC_FLASH_PUSH 0xc2000005
+#define BAIKAL_SMC_FLASH_PULL 0xc2000006
+#define BAIKAL_SMC_FLASH_POSITION 0xc2000007
+#define BAIKAL_SMC_FLASH_INIT 0xc2000008
+#define BAIKAL_SMC_FLASH_LOCK 0xc2000009
+#define BAIKAL_SMC_VDU_UPDATE 0xc2000100
+#define BAIKAL_SMC_SCP_LOG_DISABLE 0xc2000200
+#define BAIKAL_SMC_SCP_LOG_ENABLE 0xc2000201
+#define BAIKAL_SMC_EFUSE_GET_LOT 0xc2000202
+#define BAIKAL_SMC_EFUSE_GET_SERIAL 0xc2000203
+#define BAIKAL_SMC_EFUSE_GET_MAC 0xc2000204
+#define BAIKAL_SMC_VDEC_SMMU_SET_CACHE 0xc2000300
+#define BAIKAL_SMC_VDEC_SMMU_GET_CACHE 0xc2000301
+#define BAIKAL_SMC_CLK_ROUND 0xc2000400
+#define BAIKAL_SMC_CLK_SET 0xc2000401
+#define BAIKAL_SMC_CLK_GET 0xc2000402
+#define BAIKAL_SMC_CLK_ENABLE 0xc2000403
+#define BAIKAL_SMC_CLK_DISABLE 0xc2000404
+#define BAIKAL_SMC_CLK_IS_ENABLED 0xc2000405
+#define BAIKAL_SMC_GMAC_DIV2_ENABLE 0xc2000500
+#define BAIKAL_SMC_GMAC_DIV2_DISABLE 0xc2000501
+#define BAIKAL_SMC_LSP_MUX 0xc2000600
int64_t baikal_smc_flash_handler(const uint32_t smc,
- const uint64_t x1,
- const uint64_t x2,
- const uint64_t x3,
- const uint64_t x4,
- uint64_t *data);
-
-int64_t baikal_smc_clk_handler (const uint32_t smc,
- const uint64_t x1,
- const uint64_t x2,
- const uint64_t x3,
- const uint64_t x4);
+ const uint64_t x1,
+ const uint64_t x2,
+ const uint64_t x3,
+ const uint64_t x4,
+ uint64_t *data);
+
+int64_t baikal_smc_clk_handler(const uint32_t smc,
+ const uint64_t x1,
+ const uint64_t x2,
+ const uint64_t x3,
+ const uint64_t x4);
int64_t baikal_smc_gmac_handler(const uint32_t smc,
- const uint64_t x1,
- const uint64_t x2,
- const uint64_t x3,
- const uint64_t x4);
+ const uint64_t x1,
+ const uint64_t x2,
+ const uint64_t x3,
+ const uint64_t x4);
#endif /* BAIKAL_SIP_SVC_H */
#ifndef DW_GPIO_H
#define DW_GPIO_H
-void gpio_dir_clr(const uintptr_t base, const unsigned pin);
-void gpio_dir_set(const uintptr_t base, const unsigned pin);
-void gpio_out_rst(const uintptr_t base, const unsigned pin);
-void gpio_out_set(const uintptr_t base, const unsigned pin);
+void gpio_dir_clr(const uintptr_t base, const unsigned int pin);
+void gpio_dir_set(const uintptr_t base, const unsigned int pin);
+void gpio_out_rst(const uintptr_t base, const unsigned int pin);
+void gpio_out_set(const uintptr_t base, const unsigned int pin);
#endif /* DW_GPIO_H */
/*
- * Copyright (c) 2020-2021, Baikal Electronics, JSC. All rights reserved.
+ * Copyright (c) 2020-2023, Baikal Electronics, JSC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define DW_I2C_H
int i2c_txrx(const uintptr_t base,
- const unsigned addr,
+ const unsigned int iclk,
+ const unsigned int targetaddr,
const void *const txbuf,
- const unsigned txbufsize,
+ const unsigned int txbufsize,
void *const rxbuf,
- const unsigned rxbufsize);
+ const unsigned int rxbufsize);
#endif /* DW_I2C_H */
#include <stddef.h>
#include <stdint.h>
-int spi_flash_init( int line);
-int spi_flash_read( int line, uint32_t adr, void *data, size_t size);
+int spi_flash_init(int line);
+int spi_flash_read(int line, uint32_t adr, void *data, size_t size);
int spi_flash_erase(int line, uint32_t adr, size_t size);
int spi_flash_write(int line, uint32_t adr, void *data, size_t size);
int memtest_rand64(const uintptr_t base,
const size_t size,
- const unsigned incr,
+ const unsigned int incr,
const uint64_t seed);
int memtest_rand8(const uintptr_t base,
const size_t size,
- const unsigned incr,
+ const unsigned int incr,
const uint64_t seed);
#endif /* MEMTEST_H */
#ifndef SPD_H
#define SPD_H
-unsigned spd_get_baseconf_crc(const void *const baseconf);
+unsigned int spd_get_baseconf_crc(const void *const baseconf);
unsigned long long spd_get_baseconf_dimm_capacity(const void *const baseconf);
#endif /* SPD_H */
int memtest_rand64(const uintptr_t base,
const size_t size,
- const unsigned incr,
+ const unsigned int incr,
const uint64_t seed)
{
uint64_t *ptr;
int memtest_rand8(const uintptr_t base,
const size_t size,
- const unsigned incr,
+ const unsigned int incr,
const uint64_t seed)
{
uint8_t *ptr;
void ndelay(const uint64_t nsec)
{
- const unsigned div = 1000000000 / plat_get_syscnt_freq2();
+ const unsigned int div = 1000000000 / plat_get_syscnt_freq2();
const uint64_t expcnt = read_cntpct_el0() + (nsec + div - 1) / div;
- while (read_cntpct_el0() <= expcnt);
+ while (read_cntpct_el0() <= expcnt)
+ ;
}
#include <spd.h>
-unsigned spd_get_baseconf_crc(const void *const baseconf)
+unsigned int spd_get_baseconf_crc(const void *const baseconf)
{
const uint8_t *const spdbuf = baseconf;
+
return (spdbuf[127] << 8) | spdbuf[126];
}
}
unsigned long long total;
+
total = sdram_capacity_per_die;
total /= 8;
total *= primary_bus_width;
projects / arm-tf.git / commitdiff