marvell: comphy: cp110: add support for USB comphy polarity invert

The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't require USB
phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards. Enable the option for the ones that need it.

Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c
index e9dcfb86153fb39c38c5500862c7e011fa4fdc8e..d1c26f8d38de84d5fd6142c40a89f5782ff0b306 100644 (file)
--- a/drivers/marvell/comphy/phy-comphy-cp110.c
+++ b/drivers/marvell/comphy/phy-comphy-cp110.c
@@ -1922,6 +1922,7 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base,
 {
        uintptr_t hpipe_addr, comphy_addr, addr;
        uint32_t mask, data;
+       uint8_t ap_nr, cp_nr, phy_polarity_invert;
        int ret = 0;
 
        debug_enter();
@@ -1930,6 +1931,13 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base,
        mvebu_cp110_comphy_set_pipe_selector(comphy_base, comphy_index,
                                             comphy_mode);
 
+       mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
+
+       const struct usb_params *usb_static_values =
+                       &usb_static_values_tab[ap_nr][cp_nr][comphy_index];
+
+       phy_polarity_invert = usb_static_values->polarity_invert;
+
        hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
                                comphy_index);
        comphy_addr = COMPHY_ADDR(comphy_base, comphy_index);
@@ -2009,6 +2017,13 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base,
                0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
                HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
 
+       /* The polarity inversion for USB was not tested due to lack of hw
+        * design which requires it. Support is added for customer needs.
+        */
+       if (phy_polarity_invert)
+               mvebu_cp110_polarity_invert(hpipe_addr + HPIPE_SYNC_PATTERN_REG,
+                                           phy_polarity_invert);
+
        /* Start analog parameters from ETP(HW) */
        debug("stage: Analog parameters from ETP(HW)\n");
        /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */

diff --git a/drivers/marvell/comphy/phy-comphy-cp110.h b/drivers/marvell/comphy/phy-comphy-cp110.h
index 1dc3aa253e7da322b6effddf2d5ef0c7935ec9d3..b4a21024222c89f9776b3f51ce9e97dc566287ab 100644 (file)
--- a/drivers/marvell/comphy/phy-comphy-cp110.h
+++ b/drivers/marvell/comphy/phy-comphy-cp110.h
@@ -81,6 +81,10 @@ struct sata_params {
        _Bool valid;
 };
 
+struct usb_params {
+       uint8_t polarity_invert;
+};
+
 int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base,
                                     uint8_t comphy_index);
 int mvebu_cp110_comphy_power_off(uint64_t comphy_base,

diff --git a/drivers/marvell/comphy/phy-default-porting-layer.h b/drivers/marvell/comphy/phy-default-porting-layer.h
index 28bfcf2428cfa71b90540e0c13d506bc4d48448a..3c63c64b8ff64e1ac4539643347a70df4fb70e1a 100644 (file)
--- a/drivers/marvell/comphy/phy-default-porting-layer.h
+++ b/drivers/marvell/comphy/phy-default-porting-layer.h
@@ -49,4 +49,11 @@ static const struct sata_params
                .valid = 0x1
        },
 };
+
+static const struct usb_params
+       usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
+       [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
+               .polarity_invert = COMPHY_POLARITY_NO_INVERT
+       },
+};
 #endif /* PHY_DEFAULT_PORTING_LAYER_H */

diff --git a/plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h b/plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h
index f0800298bc93a75c0b527d6df9a1e014e7eb0e42..afa3be158c96f4bcdac4ded7b8a18a590c9a406f 100644 (file)
--- a/plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h
+++ b/plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h
@@ -182,4 +182,11 @@ static const struct sata_params
                },
        },
 };
+
+static const struct usb_params
+       usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
+       [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
+               .polarity_invert = COMPHY_POLARITY_NO_INVERT
+       },
+};
 #endif /* PHY_PORTING_LAYER_H */

diff --git a/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h b/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h
index 824465845df4e3c4afc3a7ad7cc61f2d4aa112f8..6b554074c9ab95142ba5fd2d810481ce837aae1b 100644 (file)
--- a/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h
+++ b/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h
@@ -136,4 +136,10 @@ SATA_PARAMS sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
        },
 };
 
+static const struct usb_params
+       usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
+       [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
+               .polarity_invert = COMPHY_POLARITY_NO_INVERT
+       },
+};
 #endif /* __PHY_PORTING_LAYER_H */