CONFIG_SPL_SYS_[DI]CACHE_OFF: add

While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.

Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 240d3bbedc02c357415d396571cfa478488aeb33..0cb97207db4c082a64633486e2a45edb208c6014 100644 (file)
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -114,12 +114,26 @@ config SYS_ICACHE_OFF
        help
          Do not enable instruction cache in U-Boot.
 
+config SPL_SYS_ICACHE_OFF
+       bool "Do not enable icache in SPL"
+       depends on SPL
+       default SYS_ICACHE_OFF
+       help
+         Do not enable instruction cache in SPL.
+
 config SYS_DCACHE_OFF
        bool "Do not enable dcache"
        default n
        help
          Do not enable data cache in U-Boot.
 
+config SPL_SYS_DCACHE_OFF
+       bool "Do not enable dcache in SPL"
+       depends on SPL
+       default SYS_DCACHE_OFF
+       help
+         Do not enable data cache in SPL.
+
 menuconfig ARC_DBG
        bool "ARC debugging"
        default n

diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 84959b41bdf5eafffd33b673780e2ddd83997db1..8c744f5be7f188879ad39751dc3d5c7b3380a3c5 100644 (file)
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -16,7 +16,7 @@ ENTRY(_start)
        lr      r5, [ARC_BCR_IC_BUILD]
        breq    r5, 0, 1f               ; I$ doesn't exist
        lr      r5, [ARC_AUX_IC_CTRL]
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        bclr    r5, r5, 0               ; 0 - Enable, 1 is Disable
 #else
        bset    r5, r5, 0               ; I$ exists, but is not used
@@ -37,7 +37,7 @@ ENTRY(_start)
        breq    r5, 0, 1f               ; D$ doesn't exist
        lr      r5, [ARC_AUX_DC_CTRL]
        bclr    r5, r5, 6               ; Invalidate (discard w/o wback)
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        bclr    r5, r5, 0               ; Enable (+Inv)
 #else
        bset    r5, r5, 0               ; Disable (+Inv)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6f510cc4a7c869a9a3dd9f7646bb64caf69b2f84..00be3d1721d0e5982cf22948a3de7ad52832c6a4 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -80,12 +80,26 @@ config SYS_ICACHE_OFF
        help
          Do not enable instruction cache in U-Boot.
 
+config SPL_SYS_ICACHE_OFF
+       bool "Do not enable icache in SPL"
+       depends on SPL
+       default SYS_ICACHE_OFF
+       help
+         Do not enable instruction cache in SPL.
+
 config SYS_DCACHE_OFF
        bool "Do not enable dcache"
        default n
        help
          Do not enable data cache in U-Boot.
 
+config SPL_SYS_DCACHE_OFF
+       bool "Do not enable dcache in SPL"
+       depends on SPL
+       default SYS_DCACHE_OFF
+       help
+         Do not enable data cache in SPL.
+
 config SYS_ARM_CACHE_CP15
        bool "CP15 based cache enabling support"
        help

diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
index 4aa704b9eeb8d1e01c4b83f95bcdf75d10589d74..8aee1539a9db8b7d2a6b6b76af02e603e096f84f 100644 (file)
--- a/arch/arm/cpu/arm11/cpu.c
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -51,7 +51,7 @@ static void cache_flush(void)
        asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void invalidate_dcache_all(void)
 {
        asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
@@ -87,7 +87,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
        asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 }
 
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 void invalidate_dcache_all(void)
 {
 }
@@ -95,15 +95,15 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
 void enable_caches(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        icache_enable();
 #endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        dcache_enable();
 #endif
 }

diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 22a55f52e0176914135e14a355dbaa107568c322..16eea693d12e8cc41b69ec52036b0dc0d981ad1d 100644 (file)
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -6,7 +6,7 @@
 #include <linux/types.h>
 #include <common.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void invalidate_dcache_all(void)
 {
        asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
@@ -46,7 +46,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 
        asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
 }
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 void invalidate_dcache_all(void)
 {
 }
@@ -54,7 +54,7 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 /*
  * Stub implementations for l2 cache operations
@@ -66,7 +66,7 @@ __weak void l2_cache_disable(void) {}
 __weak void invalidate_l2_cache(void) {}
 #endif
 
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 /* Invalidate entire I-cache and branch predictor array */
 void invalidate_icache_all(void)
 {
@@ -80,10 +80,10 @@ void invalidate_icache_all(void) {}
 
 void enable_caches(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        icache_enable();
 #endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        dcache_enable();
 #endif
 }

diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
index c3f1ee1fd102cd614d3cee5ee6b65f2752d82495..d7cffe8b690bfc9d18c24f6ec5c47654dd2476af 100644 (file)
--- a/arch/arm/cpu/arm926ejs/cpu.c
+++ b/arch/arm/cpu/arm926ejs/cpu.c
@@ -44,7 +44,7 @@ int cleanup_before_linux (void)
 /* flush I/D-cache */
 static void cache_flush (void)
 {
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
        unsigned long i = 0;
 
        asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));

diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 10456732924bc9edd9681534d8586a508a1fa1a0..ff592ba81017ec731c1691a0174d7488b3e2b8ec 100644 (file)
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -84,7 +84,7 @@ flush_dcache:
 
        /*
         * disable MMU and D cache
-        * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
+        * enable I cache if SYS_ICACHE_OFF is not defined
         */
        mrc     p15, 0, r0, c1, c0, 0
        bic     r0, r0, #0x00000300     /* clear bits 9:8 (---- --RS) */
@@ -95,7 +95,7 @@ flush_dcache:
        bic     r0, r0, #0x00002000     /* clear bit 13 (--V- ----) */
 #endif
        orr     r0, r0, #0x00000002     /* set bit 1 (A) Align */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
 #endif
        mcr     p15, 0, r0, c1, c0, 0

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 99484c2636378a2f340c5c4b6d647ec08bf53930..0dc4ebf694383a361c7fc4c7b35ea75203810969 100644 (file)
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -12,7 +12,7 @@
 #define ARMV7_DCACHE_INVAL_RANGE       1
 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 
 /* Asm functions from cache_v7_asm.S */
 void v7_flush_dcache_all(void);
@@ -149,7 +149,7 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
        flush_dcache_range(start, stop);
        v7_inval_tlb();
 }
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 void invalidate_dcache_all(void)
 {
 }
@@ -177,9 +177,9 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
 void arm_init_domains(void)
 {
 }
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 /* Invalidate entire I-cache and branch predictor array */
 void invalidate_icache_all(void)
 {

diff --git a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
index 8bf06a3e48f060bfacf97f264246ca5a398bb683..70431ecf6b15aec7e198ce89246306fb4be208b0 100644 (file)
--- a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
@@ -5,7 +5,7 @@
 
 #include <common.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/arch/arm/cpu/armv7/kona-common/hwinit-common.c b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
index 8783893cf68389770b7c70cae05da6c3b0b3b728..10e74888792be11e258a6c28f724292280db5ee1 100644 (file)
--- a/arch/arm/cpu/armv7/kona-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
@@ -6,7 +6,7 @@
 #include <common.h>
 #include <linux/sizes.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 7c4018ed1116be2deb099f2999d8206fcdac6f01..ecf9e869855e5ba0fa707514ac9a975bc9fcd503 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -26,7 +26,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 
 /*
  * Bit[1] of the descriptor indicates the descriptor type,
@@ -215,7 +215,7 @@ void enable_caches(void)
        invalidate_dcache_all();
        set_cr(get_cr() | CR_C);
 }
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 
 uint get_svr(void)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 0cb6dd39ccfc0584f4e6f01523fef9405c314763..dcb4195d7b48bc790ac696b2db47faf9cc72cc17 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -97,7 +97,7 @@ ENTRY(c_runtime_cpu_setup)
 /*
  * If I-cache is enabled invalidate it
  */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
        mcr     p15, 0, r0, c7, c10, 4  @ DSB
        mcr     p15, 0, r0, c7, c5, 4   @ ISB
@@ -155,7 +155,7 @@ ENTRY(cpu_init_cp15)
        bic     r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
        orr     r0, r0, #0x00000002     @ set bit 1 (--A-) Align
        orr     r0, r0, #0x00000800     @ set bit 11 (Z---) BTB
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        bic     r0, r0, #0x00001000     @ clear bit 12 (I) I-cache
 #else
        orr     r0, r0, #0x00001000     @ set bit 12 (I) I-cache

diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index 90fa695e98e55c7221fa1d4f73f6a5a08740144b..f96290348417e4d11b0e8225c1ba5ee998fd3e54 100644 (file)
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -360,7 +360,7 @@ int get_clocks(void)
        return 0;
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)

diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
index 815e623c29d3802f957d12087139f3a1ba99bf71..1106bead41168049a268a28aacb7a2c864302762 100644 (file)
--- a/arch/arm/cpu/armv7m/cache.c
+++ b/arch/arm/cpu/armv7m/cache.c
@@ -54,7 +54,7 @@ enum cache_action {
        FLUSH_INVAL_SET_WAY,    /* d-cache clean & invalidate by set/ways */
 };
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 struct dcache_config {
        u32 ways;
        u32 sets;
@@ -292,7 +292,7 @@ void invalidate_dcache_all(void)
 }
 #endif
 
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 
 void invalidate_icache_all(void)
 {
@@ -349,10 +349,10 @@ int icache_status(void)
 
 void enable_caches(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        icache_enable();
 #endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        dcache_enable();
 #endif
 }

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 9ca397e73c9b9776ac9ad9ec172dd94ed5ff11a5..e500e722e51260c031696f6a346e1a37c79b225f 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -13,7 +13,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 
 /*
  *  With 4k page granule, a virtual address is split into 4 lookup parts
@@ -657,7 +657,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
        __asm_invalidate_tlb_all();
 }
 
-#else  /* CONFIG_SYS_DCACHE_OFF */
+#else  /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 /*
  * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
@@ -694,9 +694,9 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 {
 }
 
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 
 void icache_enable(void)
 {
@@ -720,7 +720,7 @@ void invalidate_icache_all(void)
        __asm_invalidate_l3_icache();
 }
 
-#else  /* CONFIG_SYS_ICACHE_OFF */
+#else  /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
 
 void icache_enable(void)
 {
@@ -739,7 +739,7 @@ void invalidate_icache_all(void)
 {
 }
 
-#endif /* CONFIG_SYS_ICACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
 
 /*
  * Enable dCache & iCache, whether cache is actually enabled

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 978d46b32fcb18cbbad8459df6c603417bed1d54..12d709e23ec1fabe9d2c823ac64f813d564158df 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -388,7 +388,7 @@ void cpu_name(char *name)
                strcpy(name, "unknown");
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 /*
  * To start MMU before DDR is available, we create MMU table in SRAM.
  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
@@ -611,7 +611,7 @@ void enable_caches(void)
        icache_enable();
        dcache_enable();
 }
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 #ifdef CONFIG_TFABOOT
 enum boot_src __get_boot_src(u32 porsr1)

diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c
index 1fa6841eaf783e8ad4cc662bb647cd00145e95b5..b4cb67a66a3b9754f685da5d766b50fc03c6a975 100644 (file)
--- a/arch/arm/cpu/armv8/s32v234/cpu.c
+++ b/arch/arm/cpu/armv8/s32v234/cpu.c
@@ -16,7 +16,7 @@ u32 cpu_mask(void)
        return readl(MC_ME_CS);
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 
 #define S32V234_IRAM_BASE        0x3e800000UL
 #define S32V234_IRAM_SIZE        0x800000UL

diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c
index 8b932b10e1b1498836f5ac05ad0484ee12592be1..5cd4a9524bc6527d8e530cebb9e21d555cb42347 100644 (file)
--- a/arch/arm/cpu/pxa/cache.c
+++ b/arch/arm/cpu/pxa/cache.c
@@ -6,7 +6,7 @@
 #include <linux/types.h>
 #include <common.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void invalidate_dcache_all(void)
 {
        /* Flush/Invalidate I cache */
@@ -35,7 +35,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 {
        return invalidate_dcache_range(start, stop);
 }
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 void invalidate_dcache_all(void)
 {
 }
@@ -43,7 +43,7 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 /*
  * Stub implementations for l2 cache operations

diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c
index b9fd41ece25c41e006b896b9972dc377f0fb816e..0b28f0a3ef60ffe4278c1eca0cee0d5b6ff699e9 100644 (file)
--- a/arch/arm/cpu/pxa/pxa2xx.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -286,10 +286,10 @@ void reset_cpu(ulong ignored)
 
 void enable_caches(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        icache_enable();
 #endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        dcache_enable();
 #endif
 }

diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index c3ee5f0c7b3b905357e57cedfa47f34d25627b07..a81b1061df9ff4e9a5a585b32c8f55c37ece659c 100644 (file)
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -35,7 +35,7 @@ struct arch_global_data {
        unsigned int tbl;
        unsigned long lastinc;
        unsigned long long timer_reset_value;
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
        unsigned long tlb_addr;
        unsigned long tlb_size;
 #if defined(CONFIG_ARM64)

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 0688f1e6a679fb77ea0836669235df87dbe18d28..b2913e8165a8c85ba473adb4f5abe7a210570364 100644 (file)
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -10,7 +10,7 @@
 #include <linux/compiler.h>
 #include <asm/armv7_mpu.h>
 
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -246,7 +246,7 @@ static void cache_disable(uint32_t cache_bit)
 }
 #endif
 
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 void icache_enable (void)
 {
        return;
@@ -278,7 +278,7 @@ int icache_status(void)
 }
 #endif
 
-#ifdef CONFIG_SYS_DCACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void dcache_enable (void)
 {
        return;

diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 565fbbe1097460617609fc8ef17bc159ec75968e..449544d11cff52ccf34adc03b3e946550a4e26ad 100644 (file)
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -87,7 +87,7 @@ void noncached_init(void)
        noncached_end = end;
        noncached_next = start;
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
 #endif
 }

diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index 589e16c5ad6f6a9be677313a3a29619c38ac0f42..2ae9a43b4e8d20d6e67c924f9b87493fb8d03335 100644 (file)
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -25,7 +25,7 @@ void reset_cpu(ulong addr)
 #endif
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
index 75e1f54c6a7d97c19e826a3f14e28576ae335fbf..a60594250335289bc26a401fbe6b6dc377f86a5c 100644 (file)
--- a/arch/arm/mach-imx/cache.c
+++ b/arch/arm/mach-imx/cache.c
@@ -37,7 +37,7 @@ static void enable_ca7_smp(void)
        }
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)

diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 2c425357b56a5ecc620b7779e937dc74cb02bd2d..53f9a8735ad6dcd41bc38fc851019879c655a73a 100644 (file)
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -446,7 +446,7 @@ void enable_caches(void)
        dcache_enable();
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 u64 get_page_table_size(void)
 {
        u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);

diff --git a/arch/arm/mach-imx/mx5/soc.c b/arch/arm/mach-imx/mx5/soc.c
index 43d6c08b42d1a9ddd226d3cfd6339a7210826503..bbb335e275b565208a72ad22fa8a3579bca426f0 100644 (file)
--- a/arch/arm/mach-imx/mx5/soc.c
+++ b/arch/arm/mach-imx/mx5/soc.c
@@ -62,7 +62,7 @@ u32 __weak get_board_rev(void)
 }
 #endif
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index f43b3dcbfa382fc279aa2230797c4bd469e098eb..3dee300d77fb53d25cd5dda7cdcb402eba298fc7 100644 (file)
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -204,7 +204,7 @@ void reset_cpu(ulong addr)
 
 void enable_caches(void)
 {
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        /* Enable D-cache. I-cache is already enabled in start.S */
        dcache_enable();
 #endif

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 0777a0c99810807cabab50dfcc9f0d50b10cc83f..bb01eab80e674d6754665ee7ecbb7a94f49c3067 100644 (file)
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -34,7 +34,7 @@ obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
 endif
 endif
 
-ifeq ($(CONFIG_SYS_DCACHE_OFF),)
+ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),)
 obj-y  += omap-cache.o
 endif
 

diff --git a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
index 6dc92a6bfa355249153061d62b0312d058ab10f1..32de9d3d4fd23b4586dd9d9d8a961b97e4a74574 100644 (file)
--- a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
+++ b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
@@ -16,7 +16,7 @@
 
 .arch_extension sec
 
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 .global flush_dcache_range
 #endif
 
@@ -79,7 +79,7 @@ ENTRY(omap_smc_sec_cpu1)
        push    {r4, r5, lr}
        ldr     r4, =omap_smc_sec_cpu1_args
        stm     r4, {r0,r1,r2,r3}       @ Save args to memory
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        mov     r0, r4
        mov     r1, #CONFIG_SYS_CACHELINE_SIZE
        add     r1, r0, r1              @ dcache is not enabled on CPU1, so
@@ -109,7 +109,7 @@ ENDPROC(omap_smc_sec_cpu1)
  */
 .section .data
 omap_smc_sec_cpu1_args:
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        .balign CONFIG_SYS_CACHELINE_SIZE
        .rept  CONFIG_SYS_CACHELINE_SIZE/4
        .word 0

diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c
index 600a31280c7af631f3b9aa2590232edf63159e46..b45d3ee544910758575375bd02a5ab8999aa1d51 100644 (file)
--- a/arch/arm/mach-omap2/sec-common.c
+++ b/arch/arm/mach-omap2/sec-common.c
@@ -333,7 +333,7 @@ int secure_tee_install(u32 addr)
        debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0);
        debug("tee_file_size = %d\n", tee_file_size);
 
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        flush_dcache_range(
                rounddown((u32)loadptr, ARCH_DMA_MINALIGN),
                roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN));
@@ -356,7 +356,7 @@ int secure_tee_install(u32 addr)
                /* Reuse the tee_info buffer for SMC params */
                smc_cpu1_params = (u32 *)&tee_info;
                smc_cpu1_params[0] = 0;
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
                flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params +
                                roundup(sizeof(u32), ARCH_DMA_MINALIGN));
 #endif

diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index b0686ed2035c3e8905c701de50e179ce16937b9d..784a2a28d5c2cadd7ada9348210f4e5b2a3f42f4 100644 (file)
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -17,7 +17,7 @@ int arch_cpu_init(void)
 
 /* R-Car Gen3 D-cache is enabled in memmap-gen3.c */
 #ifndef CONFIG_RCAR_GEN3
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        dcache_enable();

diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c
index 2094a4336d0b584be2f51255cf97ad1bdbf3db7c..e6ea0e9a6ae520b4018457e5377f25a0048ad152 100644 (file)
--- a/arch/arm/mach-rockchip/rk3036-board.c
+++ b/arch/arm/mach-rockchip/rk3036-board.c
@@ -48,7 +48,7 @@ int dram_init(void)
 }
 #endif
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c
index b1c66382e356911cdee3838c991c0b91ead50eb1..fa71685af80dcf8e882c585cc35beefd6df6c337 100644 (file)
--- a/arch/arm/mach-rockchip/rk3128-board.c
+++ b/arch/arm/mach-rockchip/rk3128-board.c
@@ -57,7 +57,7 @@ int dram_init_banksize(void)
        return 0;
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c
index e03759f78929abdfc6b85c12c46cefda51d4d0e6..80d8c4241ec36a77575b9b300b271621cdf5e87d 100644 (file)
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ b/arch/arm/mach-rockchip/rk3188-board.c
@@ -75,7 +75,7 @@ err:
 #endif
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c
index 6170c76f8b944297493bf87840fe62e03b2673a2..e7a1e54874d6d01641c730d477e1b03f01283fb8 100644 (file)
--- a/arch/arm/mach-rockchip/rk322x-board.c
+++ b/arch/arm/mach-rockchip/rk322x-board.c
@@ -58,7 +58,7 @@ int dram_init_banksize(void)
        return 0;
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
index 41e9786d46fa473658252ca9ee0d16c7a503b6bc..e2de5b2fddba5afe51c9c693e4b73d685bcf87ff 100644 (file)
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -186,7 +186,7 @@ err:
 #endif
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c
index 33596f628c9effe10ad2d37747c456e9968a3c31..66aeb3ffcc9094f07e97ef3db69044e3eaa5ca5c 100644 (file)
--- a/arch/arm/mach-rockchip/rv1108/rv1108.c
+++ b/arch/arm/mach-rockchip/rv1108/rv1108.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/arch/arm/mach-s5pc1xx/cache.c b/arch/arm/mach-s5pc1xx/cache.c
index 12c9d7ce3af181c9a7288a022093a28b1eafbb2b..0b879b545dde27d2371a746c7407d2fc8b03b77d 100644 (file)
--- a/arch/arm/mach-s5pc1xx/cache.c
+++ b/arch/arm/mach-s5pc1xx/cache.c
@@ -9,7 +9,7 @@
 
 #include <common.h>
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        dcache_enable();

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index d887f0201f7b050a0815e4e8dd64997c3ace13dd..db1983dc311dd1617a11323818f802d9b5e5b284 100644 (file)
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -48,10 +48,10 @@ int dram_init(void)
 
 void enable_caches(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        icache_enable();
 #endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        dcache_enable();
 #endif
 }

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index c6dd7b8e54b05c74c04394064cdb7d6139ec7a03..7f5b633e0125067d5acee73beb7ccc4bf9760756 100644 (file)
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -300,7 +300,7 @@ void reset_cpu(ulong addr)
 #endif
 }
 
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index f8fc042a1dcc273a1f3967f2073b00f9981cfe30..4e159075d379bdb90aad5253ef2088dc6dfbc5f8 100644 (file)
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -226,7 +226,7 @@ U_BOOT_DEVICE(ns16550_com1) = {
 };
 #endif
 
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index a3422cd5cf2c059e7d91b1e6a6526b193dd959e2..e5f557716b7b004f97069089856b4de8967b4ccb 100644 (file)
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -83,7 +83,7 @@ void reset_cpu(ulong addr)
                ;
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig
index 89d8af5142cd0c4b61f947db1547e1667ab3fdc9..b6f16bf1244662c91ad9bdac861c684600b955e0 100644 (file)
--- a/arch/nds32/Kconfig
+++ b/arch/nds32/Kconfig
@@ -22,12 +22,26 @@ config SYS_ICACHE_OFF
        help
          Do not enable instruction cache in U-Boot.
 
+config SPL_SYS_ICACHE_OFF
+       bool "Do not enable icache in SPL"
+       depends on SPL
+       default SYS_ICACHE_OFF
+       help
+         Do not enable instruction cache in SPL.
+
 config SYS_DCACHE_OFF
        bool "Do not enable dcache"
        default n
        help
          Do not enable data cache in U-Boot.
 
+config SPL_SYS_DCACHE_OFF
+       bool "Do not enable dcache in SPL"
+       depends on SPL
+       default SYS_DCACHE_OFF
+       help
+         Do not enable data cache in SPL.
+
 source "board/AndesTech/adp-ag101p/Kconfig"
 source "board/AndesTech/adp-ae3xx/Kconfig"
 

diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
index 4e6a0e7a31e7b63c6a28e8e6c840d335b640e28c..691888157fb1b9db41dab6ec62cd298770bd22a0 100644 (file)
--- a/arch/nds32/cpu/n1213/start.S
+++ b/arch/nds32/cpu/n1213/start.S
@@ -129,7 +129,7 @@ set_ivb:
        mfsr    $r1, $mr8
        and     $r1, $r1, $r0
        mtsr    $r1, $mr8
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
 /*
  * MMU_CTL NTC0 Cacheable/Write-Back
  */
@@ -139,7 +139,7 @@ set_ivb:
        mtsr    $r1, $mr0
 #endif
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_ARCH_MAP_SYSMEM
 /*
  * MMU_CTL NTC1 Non-cacheable
@@ -158,14 +158,14 @@ set_ivb:
 #endif
 #endif
 
-#if !defined(CONFIG_SYS_ICACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        li      $r0, 0x1
        mfsr    $r1, $mr8
        or      $r1, $r1, $r0
        mtsr    $r1, $mr8
 #endif
 
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        li      $r0, 0x2
        mfsr    $r1, $mr8
        or      $r1, $r1, $r0

diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c
index 3e5aa7cda8a78717d5a33818a2d2d76820e58973..27065136dd2df2e25f573df6e53e726236ac10de 100644 (file)
--- a/arch/nds32/lib/cache.c
+++ b/arch/nds32/lib/cache.c
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
 static inline unsigned long CACHE_SET(unsigned char cache)
 {
        if (cache == ICACHE)
@@ -38,7 +38,7 @@ static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
 }
 #endif
 
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 void invalidate_icache_all(void)
 {
        unsigned long end, line_size;
@@ -133,7 +133,7 @@ int icache_status(void)
 
 #endif
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void dcache_wbinval_all(void)
 {
        unsigned long end, line_size;

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c993809a6a3fcebe1c5050077e8db796926457f7..0d04d91ad49517f10962180105a0009ccfe41d4a 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -25,12 +25,26 @@ config SYS_ICACHE_OFF
        help
          Do not enable instruction cache in U-Boot.
 
+config SPL_SYS_ICACHE_OFF
+       bool "Do not enable icache in SPL"
+       depends on SPL
+       default SYS_ICACHE_OFF
+       help
+         Do not enable instruction cache in SPL.
+
 config SYS_DCACHE_OFF
        bool "Do not enable dcache"
        default n
        help
          Do not enable data cache in U-Boot.
 
+config SPL_SYS_DCACHE_OFF
+       bool "Do not enable dcache in SPL"
+       depends on SPL
+       default SYS_DCACHE_OFF
+       help
+         Do not enable data cache in SPL.
+
 # board-specific options below
 source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 228fc55f56bc9bf9667a400474d87c66e1e8d2e4..cd95058d9d839c05113e55712dba95354477857c 100644 (file)
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -30,7 +30,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
 
 void icache_enable(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
        asm volatile (
                "csrr t1, mcache_ctl\n\t"
@@ -43,7 +43,7 @@ void icache_enable(void)
 
 void icache_disable(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
        asm volatile (
                "fence.i\n\t"
@@ -57,7 +57,7 @@ void icache_disable(void)
 
 void dcache_enable(void)
 {
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
        asm volatile (
                "csrr t1, mcache_ctl\n\t"
@@ -70,7 +70,7 @@ void dcache_enable(void)
 
 void dcache_disable(void)
 {
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
        asm volatile (
                "fence\n\t"

diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index c8b72ebf05e84aa3e16c36b6461f360a8b3c3bd5..6de31e8c1e05d0e94bb099a8bd74d5102bf5dc3d 100644 (file)
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -22,12 +22,26 @@ config SYS_ICACHE_OFF
        help
          Do not enable instruction cache in U-Boot.
 
+config SPL_SYS_ICACHE_OFF
+       bool "Do not enable icache in SPL"
+       depends on SPL
+       default SYS_ICACHE_OFF
+       help
+         Do not enable instruction cache in SPL.
+
 config SYS_DCACHE_OFF
        bool "Do not enable dcache"
        default n
        help
          Do not enable data cache in U-Boot.
 
+config SPL_SYS_DCACHE_OFF
+       bool "Do not enable dcache in SPL"
+       depends on SPL
+       default SYS_DCACHE_OFF
+       help
+         Do not enable data cache in SPL.
+
 source "board/cadence/xtfpga/Kconfig"
 
 endmenu

diff --git a/arch/xtensa/cpu/start.S b/arch/xtensa/cpu/start.S
index 0fafb1c4f8e6df9999274774452afbc3bc6ec2d5..38d2fa2fe13b5a0f397b9128eb955b81b1afa5b9 100644 (file)
--- a/arch/xtensa/cpu/start.S
+++ b/arch/xtensa/cpu/start.S
@@ -164,18 +164,19 @@ _start:
         * enable data/instruction cache for relocated image.
         */
 #if XCHAL_HAVE_SPANNING_WAY && \
-       !(defined(CONFIG_SYS_DCACHE_OFF) && defined(CONFIG_SYS_ICACHE_OFF))
+       !(CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && \
+         CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
        srli    a7, a4, 29
        slli    a7, a7, 29
        addi    a7, a7, XCHAL_SPANNING_WAY
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        rdtlb1  a8, a7
        srli    a8, a8, 4
        slli    a8, a8, 4
        addi    a8, a8, CA_WRITEBACK
        wdtlb   a8, a7
 #endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        ritlb1  a8, a7
        srli    a8, a8, 4
        slli    a8, a8, 4

diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c
index b4fc8f3ce16ea66fa2fa8a350f7386d10c77916e..111e64b995ff8e44f51593851ab8edb5ba75f422 100644 (file)
--- a/board/st/stih410-b2260/board.c
+++ b/board/st/stih410-b2260/board.c
@@ -26,7 +26,7 @@ int dram_init_banksize(void)
        return 0;
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void enable_caches(void)
 {
        /* Enable D-cache. I-cache is already enabled in start.S */

diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index cbeba6ba28f771e3ce9ddf3d13efea6d9298350c..f576e226ee90e6630c63feab269e46eb281c4b15 100644 (file)
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -321,7 +321,7 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
        print_eths();
 #endif
        print_baudrate();
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
        print_num("TLB addr", gd->arch.tlb_addr);
 #endif
        print_num("relocaddr", gd->relocaddr);

diff --git a/common/board_f.c b/common/board_f.c
index 7ef20f204231335088c0c8ec7f191987d7416b09..c25eb188fb2506b8399edc25571998baafae64e6 100644 (file)
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -381,7 +381,7 @@ static int reserve_round_4k(void)
 #ifdef CONFIG_ARM
 __weak int reserve_mmu(void)
 {
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
        /* reserve TLB table */
        gd->arch.tlb_size = PGTABLE_SIZE;
        gd->relocaddr -= gd->arch.tlb_size;

diff --git a/common/lcd.c b/common/lcd.c
index cd630405d44a3345438e88787b602d7a7e822b26..95526b1e17e8f00e64722830274633206838ff0d 100644 (file)
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -61,7 +61,7 @@ void lcd_sync(void)
         * architectures do not actually implement it. Is there a way to find
         * out whether it exists? For now, ARM is safe.
         */
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        int line_length;
 
        if (lcd_flush_dcache)

diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index bcc5a0aa4aaa806e87f118cf920171432d264a98..73febdf42383c51e9131f090195e34a023e91338 100644 (file)
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_THUMB_BUILD=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set

diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig
index 63acd28c7e76f6726aa5cdfde0af881fd38e1018..3787a9573a3b3e7f0b3836dc84b1c62488913bf1 100644 (file)
--- a/configs/bitmain_antminer_s9_defconfig
+++ b/configs/bitmain_antminer_s9_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="bitmain"
 CONFIG_SYS_BOARD="antminer_s9"
 CONFIG_SYS_CONFIG_NAME="bitmain_antminer_s9"
 CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_ENV_OFFSET=0x300000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 6811a62bd11cc74ff104c6daaa772fd8f347479f..73831248518347f02c93dcb564bf15a8f7efad6c 100644 (file)
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -1,5 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8M=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x40200000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_IMX8MQ_EVK=y

diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index 238d44d1f58f6e98a60eeb9d59974372e275574b..1a6ce3abf85d663eeeb7aeff7d5a4200b0f6ae9f 100644 (file)
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -1,5 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index 59675e56b926a61f09762e92888547f314775f79..c4a8cf3881a9393d7c698a8bd9241824b0d5ad6e 100644 (file)
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -1,5 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 005b6e904467f6222400aff96b0eb53d76a28ce0..ffe50b1fd79498822f3bd6a9dcab7f517998f19c 100644 (file)
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -2,6 +2,8 @@ CONFIG_ARM=y
 CONFIG_SPL_SYS_THUMB_BUILD=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_AT91=y
 CONFIG_SYS_TEXT_BASE=0x23000000
 CONFIG_TARGET_SMARTWEB=y

diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 896232a715bb0bd37f1cff45e33c99680a9c9b2f..5616b3e23ac7a11ad2e383b78e76d32ac35c3493 100644 (file)
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_VENDOR="opalkelly"
 CONFIG_SYS_CONFIG_NAME="syzygy_hub"
 CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y

diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 02a89592d747bb5d31ca6eb24c6e2dbb96288cd5..8af7dd7c3ab128784a8d88a7b810007fda4de011 100644 (file)
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -2,6 +2,8 @@ CONFIG_ARM=y
 CONFIG_SYS_THUMB_BUILD=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_AT91=y
 CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
 CONFIG_SYS_TEXT_BASE=0x21000000

diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index b55885669d22b789bda8eef9ac7a5a230849c1ff..bb8d37a370df268cde91db0e8f0c21d133278d46 100644 (file)
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_VENDOR="topic"
 CONFIG_SYS_CONFIG_NAME="topic_miami"
 CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y

diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 69832451734c9099642db60ef3d3cb028ad03c32..87af8c81d3d48d9260fbf062a267dc501b59d20e 100644 (file)
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_VENDOR="topic"
 CONFIG_SYS_CONFIG_NAME="topic_miami"
 CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y

diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index 89461ee6d20795403b2d6ae8b3c087aca3e3d016..874ca8a7469485215a30817ed5eec2f0b3c36d4c 100644 (file)
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_SYS_VENDOR="topic"
 CONFIG_SYS_CONFIG_NAME="topic_miami"
 CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y

diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig
index 089df8db15183c063977e3c9d71a3aa379e2de5a..966bb150d16f3a0be5728ff167b6c4a7b9e06d5b 100644 (file)
--- a/configs/zynq_cc108_defconfig
+++ b/configs/zynq_cc108_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 62ed8f73e1ee2d0be0da6cf7ccfd71e8bafbcd5a..76b85d4cb3902ec69288c1fb7349abf5319cb9ce 100644 (file)
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="zynq_cse"
 CONFIG_SYS_ICACHE_OFF=y
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0x100000
 CONFIG_ENV_SIZE=0x190
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index 2e9a54e50ac8759ddcc3ddddd9da2756219f1021..fad7b5d66e05bfde59e24928cf82ad9f324c5c59 100644 (file)
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="zynq_cse"
 CONFIG_SYS_ICACHE_OFF=y
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_SYS_TEXT_BASE=0xFFFC0000
 CONFIG_ENV_SIZE=0x190
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig
index 913581e504b065d58e2f30ca2cb712ef8a385c63..f9d2b31aacfafcbdd3738ce6d03374fe8a393830 100644 (file)
--- a/configs/zynq_dlc20_rev1_0_defconfig
+++ b/configs/zynq_dlc20_rev1_0_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 83fa967641e7de1cee59a995ba006a5acde5b01a..5e7ff1666e237cbadeaccfbb5e9ea4483a8d043c 100644 (file)
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig
index 809fa91e96960a5e8e37013f5a533ba35d7d37d1..f253483b4888a1e9c26fd6835c8e412c47b90503 100644 (file)
--- a/configs/zynq_minized_defconfig
+++ b/configs/zynq_minized_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 09d78dc8baa66a1d10378037045674fb147e53a6..0650ce2624af7fff8421df1004b46e42f0575b4e 100644 (file)
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig
index f24fe31dc79774a06fc2b0602cace2839adf0cf6..4839ee238fc1582a78f3b447fda8510052d3c51c 100644 (file)
--- a/configs/zynq_z_turn_defconfig
+++ b/configs/zynq_z_turn_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 748b080c7c2708f727e94e3807b53d17650c81ab..71559b09b075af70bcb94ead5002e4ca30d7f30e 100644 (file)
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 9b0ddb0c937d0642ec259137dddc4fee3e921979..132ef6c0d75b73f5be709dcaa676d11a606c387d 100644 (file)
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 8653d7a6797f2bf3108e76f8cb5be51c16b5c319..8ba35cb98309c2c8ab094660cf84b33f3fffb3d5 100644 (file)
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index eb2583609768033d45e2a4134c3a5e87f44e5389..84f46a79244c81bd1877fb02babdb3e1b759102a 100644 (file)
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig
index 4e403394e053f335d7190ef72a4a7c071096e4fd..43ff1f4d16c1f0e7aa51327133a5ef69f3044aa1 100644 (file)
--- a/configs/zynq_zc770_xm011_x16_defconfig
+++ b/configs/zynq_zc770_xm011_x16_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 868b73b59054adcf3263cd124af5a40ecbe861f1..2adf6868814c3e6079056c6cd802fe3ce3ac0359 100644 (file)
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index b1d19f1cc27f0e7db7900931abbe7ae46e8fe3d6..ed6506d1ca5ebdeb86b446ff80779b9fcca1df80 100644 (file)
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 09fc1c3b7205d568f44cd656368068da0ecc7592..2da6d40b49fce3491c3c8201a4502bdd31710e04 100644 (file)
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 607bc276b4a5e51f850a9fdeceb223cf42826f1a..b51272b354b18c733acadfb0e902ba57dce01e87 100644 (file)
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig
index 81da0d28acc0859831b6d15f836459e4f7a69a6d..4deb14eefa27c413478dd491467b33abff7323df 100644 (file)
--- a/configs/zynq_zybo_z7_defconfig
+++ b/configs/zynq_zybo_z7_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
 CONFIG_SPL_STACK_R_ADDR=0x200000

diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 017cc89a89ff9ef15b72b19634e27753a5bd10f7..ac589feeb7d8bd7bb3446ade1820b1ae254782b6 100644 (file)
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -81,7 +81,7 @@ static int mxs_dma_read_semaphore(int channel)
        return tmp;
 }
 
-#ifndef        CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
 {
        uint32_t addr;

diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index be4ee2c7f8a809f2ef08702bde29c2e4d94919ea..b93d77a39518ed0db5d48e7d151790bb04fcf172 100644 (file)
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -50,7 +50,7 @@ struct nand_ecclayout fake_ecc_layout;
 /*
  * Cache management functions
  */
-#ifndef        CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
 {
        uint32_t addr = (uint32_t)info->data_buf;

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9f1c5af46e992aec87b4ff826adc68ba27ccf47f..590e756f5c6ba8b265ed5b8b394b24f098c7bd53 100644 (file)
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -241,7 +241,7 @@ struct eqos_tegra186_regs {
  */
 #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
-       !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+       !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
 #warning Cache line size is larger than descriptor size
 #endif
 #endif

diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index bc052e72564bcd257233392d5ab0f873c379fffc..521e5909a256ebfd4b39a60a43e8278d4f984a2d 100644 (file)
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -302,7 +302,7 @@ static unsigned char rxdata[RX_BUF_LEN];
  */
 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
-       !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+       !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
 #warning cache-line size is larger than descriptor size
 #endif
 #endif

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 8e54e7cc7a7feaa7d0815f516b6751fffc960b84..da79b766a62241e4708af9d5f27cc6e09d0edc81 100644 (file)
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -34,7 +34,8 @@
 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
 #endif
 
-#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
+       !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #define flush_cache_wback(addr, len)    \
                flush_dcache_range((u32)addr, \
                (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))

diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index 14aac88d6d277576758ee3369bb4e76a179b8635..b19bfb4f2ff587e821c959afd511ad289737da8d 100644 (file)
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -149,7 +149,7 @@ void video_sync(struct udevice *vid, bool force)
         * architectures do not actually implement it. Is there a way to find
         * out whether it exists? For now, ARM is safe.
         */
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        struct video_priv *priv = dev_get_uclass_priv(vid);
 
        if (priv->flush_dcache) {

diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index 5bd63929735ebfa82383ff23e0a6f96fd10f449c..2af5a4fe3e613abce5118fea8651a05b2115acca 100644 (file)
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -167,7 +167,7 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #define CONFIG_CMD_CACHE
 #endif
 

diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 0d0c6bdc69d9e2251173d601310e065ac841de82..776d7d7970531b007c069e704a32fa27f3d28713 100644 (file)
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -216,11 +216,6 @@
 #define CONFIG_SYS_MCKR_CSS            (0x02 | CONFIG_SYS_MCKR)
 #define CONFIG_SYS_AT91_PLLB           0x10483f0e
 
-#if defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#endif
-
 #define CONFIG_SPL_PAD_TO              CONFIG_SYS_NAND_U_BOOT_OFFS
 #define CONFIG_SYS_SPL_LEN             CONFIG_SPL_PAD_TO
 

diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 45a4a800c5809726641b47a861194d76fb180156..dbb01af43979a525139d63bd39ba97380b3f29b6 100644 (file)
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -21,10 +21,6 @@
 #include <asm/hardware.h>
 #include <linux/sizes.h>
 
-#if defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#endif
 /*
  * Warning: changing CONFIG_SYS_TEXT_BASE requires
  * adapting the initial boot program.

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 523d4da56b2ebc79fafa3d46a23a53d460cc77f9..143dc7bb22471a257cebc402a9f6284823eaf4d9 100644 (file)
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -284,11 +284,6 @@
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot.img"
 #endif
 
-/* Disable dcache for SPL just for sure */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_DCACHE_OFF
-#endif
-
 /* Address in RAM where the parameters must be copied by SPL. */
 #define CONFIG_SYS_SPL_ARGS_ADDR       0x10000000