--- /dev/null
+/*
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <common/runtime_svc.h>
+#include <cortex_a57.h>
+#include <platform_def.h>
+
+#include "rcar_def.h"
+
+ .globl plat_get_my_entrypoint
+ .extern plat_set_my_stack
+ .globl platform_mem_init
+
+ .globl plat_crash_console_init
+ .globl plat_crash_console_putc
+ .globl plat_crash_console_flush
+ .globl plat_invalidate_icache
+ .globl plat_report_exception
+ .globl plat_secondary_reset
+ .globl plat_reset_handler
+ .globl plat_my_core_pos
+ .extern rcar_log_init
+
+ .extern console_rcar_init
+ .extern console_rcar_putc
+ .extern console_rcar_flush
+
+#if IMAGE_BL2
+ #define INT_ID_MASK (0x3ff)
+ .extern bl2_interrupt_error_type
+ .extern bl2_interrupt_error_id
+ .globl bl2_enter_bl31
+ .extern gicv2_acknowledge_interrupt
+ .extern rcar_swdt_exec
+#endif
+
+ /* -----------------------------------------------------
+ * void platform_get_core_pos (mpidr)
+ * -----------------------------------------------------
+ */
+func platform_get_core_pos
+ and x1, x0, #MPIDR_CPU_MASK
+ and x0, x0, #MPIDR_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+endfunc platform_get_core_pos
+
+ /* -----------------------------------------------------
+ * void platform_my_core_pos
+ * -----------------------------------------------------
+ */
+func plat_my_core_pos
+ mrs x0, mpidr_el1
+ b platform_get_core_pos
+endfunc plat_my_core_pos
+
+ /* -----------------------------------------------------
+ * void platform_get_my_entrypoint (unsigned int mpid);
+ *
+ * Main job of this routine is to distinguish between
+ * a cold and warm boot.
+ * On a cold boot the secondaries first wait for the
+ * platform to be initialized after which they are
+ * hotplugged in. The primary proceeds to perform the
+ * platform initialization.
+ * On a warm boot, each cpu jumps to the address in its
+ * mailbox.
+ *
+ * TODO: Not a good idea to save lr in a temp reg
+ * -----------------------------------------------------
+ */
+func plat_get_my_entrypoint
+ mrs x0, mpidr_el1
+ mov x9, x30 /* lr */
+
+#if defined(IMAGE_BL2)
+ /* always cold boot on bl2 */
+ mov x0, #0
+ ret x9
+#else
+ ldr x1, =BOOT_KIND_BASE
+ ldr x21, [x1]
+
+ /* Check the reset info */
+ and x1, x21, #0x000c
+ cmp x1, #0x0008
+ beq el3_panic
+ cmp x1, #0x000c
+ beq el3_panic
+
+ /* Check the boot kind */
+ and x1, x21, #0x0003
+ cmp x1, #0x0002
+ beq el3_panic
+ cmp x1, #0x0003
+ beq el3_panic
+
+ /* warm boot or cold boot */
+ and x1, x21, #1
+ cmp x1, #0
+ bne warm_reset
+
+ /* Cold boot */
+ mov x0, #0
+ b exit
+
+warm_reset:
+ /* --------------------------------------------------------------------
+ * A per-cpu mailbox is maintained in the trusted SDRAM. Its flushed out
+ * of the caches after every update using normal memory so its safe to
+ * read it here with SO attributes
+ * ---------------------------------------------------------------------
+ */
+ ldr x10, =MBOX_BASE
+ bl platform_get_core_pos
+ lsl x0, x0, #CACHE_WRITEBACK_SHIFT
+ ldr x0, [x10, x0]
+ cbz x0, _panic
+exit:
+ ret x9
+_panic:
+ b do_panic
+#endif
+
+endfunc plat_get_my_entrypoint
+
+ /* ---------------------------------------------
+ * plat_secondary_reset
+ *
+ * ---------------------------------------------
+ */
+func plat_secondary_reset
+ mrs x0, sctlr_el3
+ bic x0, x0, #SCTLR_EE_BIT
+ msr sctlr_el3, x0
+ isb
+
+ mrs x0, cptr_el3
+ bic w0, w0, #TCPAC_BIT
+ bic w0, w0, #TTA_BIT
+ bic w0, w0, #TFP_BIT
+ msr cptr_el3, x0
+
+ mov_imm x0, PARAMS_BASE
+ mov_imm x2, BL31_BASE
+ ldr x3, =BOOT_KIND_BASE
+ mov x1, #0x1
+ str x1, [x3]
+ br x2 /* jump to BL31 */
+ nop
+ nop
+ nop
+endfunc plat_secondary_reset
+
+ /* ---------------------------------------------
+ * plat_enter_bl31
+ *
+ * ---------------------------------------------
+ */
+func bl2_enter_bl31
+ mov x20, x0
+ /*
+ * MMU needs to be disabled because both BL2 and BL31 execute
+ * in EL3, and therefore share the same address space.
+ * BL31 will initialize the address space according to its
+ * own requirement.
+ */
+#if RCAR_BL2_DCACHE == 1
+ /* Disable mmu and data cache */
+ bl disable_mmu_el3
+ /* Data cache clean and invalidate */
+ mov x0, #DCCISW
+ bl dcsw_op_all
+ /* TLB invalidate all, EL3 */
+ tlbi alle3
+#endif /* RCAR_BL2_DCACHE == 1 */
+ bl disable_mmu_icache_el3
+ /* Invalidate instruction cache */
+ ic iallu
+ dsb sy
+ isb
+ ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
+ msr elr_el3, x0
+ msr spsr_el3, x1
+ exception_return
+endfunc bl2_enter_bl31
+
+ /* -----------------------------------------------------
+ * void platform_mem_init (void);
+ *
+ * Zero out the mailbox registers in the shared memory
+ * and set the rcar_boot_kind_flag.
+ * The mmu is turned off right now and only the primary can
+ * ever execute this code. Secondaries will read the
+ * mailboxes using SO accesses.
+ * -----------------------------------------------------
+ */
+func platform_mem_init
+#if !IMAGE_BL2
+ ldr x0, =MBOX_BASE
+ mov w1, #PLATFORM_CORE_COUNT
+loop:
+ str xzr, [x0], #CACHE_WRITEBACK_GRANULE
+ subs w1, w1, #1
+ b.gt loop
+#endif
+ ret
+endfunc platform_mem_init
+
+ /* ---------------------------------------------
+ * void plat_report_exception(unsigned int type)
+ * Function to report an unhandled exception
+ * with platform-specific means.
+ * ---------------------------------------------
+ */
+func plat_report_exception
+ /* Switch to SP_EL0 */
+ msr spsel, #0
+#if IMAGE_BL2
+ mov w1, #FIQ_SP_EL0
+ cmp w0, w1
+ beq rep_exec_fiq_elx
+ b rep_exec_panic_type
+rep_exec_fiq_elx:
+ bl gicv2_acknowledge_interrupt
+ mov x2, #INT_ID_MASK
+ and x0, x0, x2
+ mov x1, #ARM_IRQ_SEC_WDT
+ cmp x0, x1
+ bne rep_exec_panic_id
+ mrs x0, ELR_EL3
+ b rcar_swdt_exec
+rep_exec_panic_type:
+ /* x0 is interrupt TYPE */
+ b bl2_interrupt_error_type
+rep_exec_panic_id:
+ /* x0 is interrupt ID */
+ b bl2_interrupt_error_id
+rep_exec_end:
+#endif
+ ret
+endfunc plat_report_exception
+
+ /* ---------------------------------------------
+ * int plat_crash_console_init(void)
+ * Function to initialize log area
+ * ---------------------------------------------
+ */
+func plat_crash_console_init
+#if IMAGE_BL2
+ mov x0, #0
+#else
+ mov x1, sp
+ mov_imm x2, RCAR_CRASH_STACK
+ mov sp, x2
+ str x1, [sp, #-16]!
+ str x30, [sp, #-16]!
+ bl console_rcar_init
+ ldr x30, [sp], #16
+ ldr x1, [sp], #16
+ mov sp, x1
+#endif
+ ret
+endfunc plat_crash_console_init
+
+ /* ---------------------------------------------
+ * int plat_crash_console_putc(int c)
+ * Function to store a character to log area
+ * ---------------------------------------------
+ */
+func plat_crash_console_putc
+ mov x1, sp
+ mov_imm x2, RCAR_CRASH_STACK
+ mov sp, x2
+ str x1, [sp, #-16]!
+ str x30, [sp, #-16]!
+ str x3, [sp, #-16]!
+ str x4, [sp, #-16]!
+ str x5, [sp, #-16]!
+ bl console_rcar_putc
+ ldr x5, [sp], #16
+ ldr x4, [sp], #16
+ ldr x3, [sp], #16
+ ldr x30, [sp], #16
+ ldr x1, [sp], #16
+ mov sp, x1
+ ret
+endfunc plat_crash_console_putc
+
+ /* ---------------------------------------------
+ * void plat_crash_console_flush()
+ * ---------------------------------------------
+ */
+func plat_crash_console_flush
+ b console_rcar_flush
+endfunc plat_crash_console_flush
+
+ /* --------------------------------------------------------------------
+ * void plat_reset_handler(void);
+ *
+ * Before adding code in this function, refer to the guidelines in
+ * docs/firmware-design.md to determine whether the code should reside
+ * within the FIRST_RESET_HANDLER_CALL block or not.
+ *
+ * For R-Car H3:
+ * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
+ * - Set the L2 Data setup latency to 1 (i.e. 1 cycles) for Cortex-A57
+ * - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57
+ * For R-Car M3/M3N:
+ * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
+ * - Set the L2 Data setup latency to 0 (i.e. 0 cycles) for Cortex-A57
+ * - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57
+ *
+ * --------------------------------------------------------------------
+ */
+func plat_reset_handler
+ /*
+ * On R-Car H3 : x2 := 0
+ * On R-Car M3/M3N: x2 := 1
+ */
+ /* read PRR */
+ ldr x0, =0xFFF00044
+ ldr w0, [x0]
+ ubfx w0, w0, 8, 8
+ /* H3? */
+ cmp w0, #0x4F
+ b.eq RCARH3
+ /* set R-Car M3/M3N */
+ mov x2, #1
+ b CHK_A5x
+RCARH3:
+ /* set R-Car H3 */
+ mov x2, #0
+ /* --------------------------------------------------------------------
+ * Determine whether this code is executed on a Cortex-A53 or on a
+ * Cortex-A57 core.
+ * --------------------------------------------------------------------
+ */
+CHK_A5x:
+ mrs x0, midr_el1
+ ubfx x1, x0, MIDR_PN_SHIFT, #12
+ cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+ b.eq A57
+ ret
+A57:
+ /* Get data from CORTEX_A57_L2CTLR_EL1 */
+ mrs x0, CORTEX_A57_L2CTLR_EL1
+ /*
+ * On R-Car H3/M3/M3N
+ *
+ * L2 Tag RAM latency is bit8-6 of CORTEX_A57_L2CTLR_EL1
+ * L2 Data RAM setup is bit5 of CORTEX_A57_L2CTLR_EL1
+ * L2 Data RAM latency is bit2-0 of CORTEX_A57_L2CTLR_EL1
+ */
+ /* clear bit of L2 RAM */
+ /* ~(0x1e7) -> x1 */
+ mov x1, #0x1e7
+ neg x1, x1
+ /* clear bit of L2 RAM -> x0 */
+ and x0, x0, x1
+ /* L2 Tag RAM latency (3 cycles) */
+ orr x0, x0, #0x2 << 6
+ /* If M3/M3N then L2 RAM setup is 0 */
+ cbnz x2, M3_L2
+ /* L2 Data RAM setup (1 cycle) */
+ orr x0, x0, #0x1 << 5
+M3_L2:
+ /* L2 Data RAM latency (4 cycles) */
+ orr x0, x0, #0x3
+ /* Store data to L2CTLR_EL1 */
+ msr CORTEX_A57_L2CTLR_EL1, x0
+apply_l2_ram_latencies:
+ ret
+endfunc plat_reset_handler
+
+ /* ---------------------------------------------
+ * void plat_invalidate_icache(void)
+ * Instruction Cache Invalidate All to PoU
+ * ---------------------------------------------
+ */
+func plat_invalidate_icache
+ ic iallu
+
+ ret
+endfunc plat_invalidate_icache
--- /dev/null
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/interrupt_props.h>
+#include <drivers/arm/gicv2.h>
+#include <drivers/arm/gic_common.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <plat/common/platform.h>
+
+#include "rcar_def.h"
+#include "rcar_private.h"
+#include "rcar_version.h"
+
+#if (IMAGE_BL2)
+extern void rcar_read_certificate(uint64_t cert, uint32_t *len, uintptr_t *p);
+extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert);
+#endif
+
+const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
+ __attribute__ ((__section__("ro"))) = VERSION_OF_RENESAS;
+
+#define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \
+ RCAR_SHARED_MEM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+#define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
+ FLASH0_SIZE, \
+ MT_MEMORY | MT_RO | MT_SECURE)
+
+#define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
+ DRAM1_NS_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#define MAP_DEVICE_RCAR MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
+ DEVICE_RCAR_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_DEVICE_RCAR2 MAP_REGION_FLAT(DEVICE_RCAR_BASE2, \
+ DEVICE_RCAR_SIZE2, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_SRAM MAP_REGION_FLAT(DEVICE_SRAM_BASE, \
+ DEVICE_SRAM_SIZE, \
+ MT_MEMORY | MT_RO | MT_SECURE)
+
+#define MAP_SRAM_STACK MAP_REGION_FLAT(DEVICE_SRAM_STACK_BASE, \
+ DEVICE_SRAM_STACK_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+#define MAP_ATFW_CRASH MAP_REGION_FLAT(RCAR_BL31_CRASH_BASE, \
+ RCAR_BL31_CRASH_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+#define MAP_ATFW_LOG MAP_REGION_FLAT(RCAR_BL31_LOG_BASE, \
+ RCAR_BL31_LOG_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+#if IMAGE_BL2
+#define MAP_DRAM0 MAP_REGION_FLAT(DRAM1_BASE, \
+ DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+#define MAP_REG0 MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
+ DEVICE_RCAR_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_RAM0 MAP_REGION_FLAT(RCAR_SYSRAM_BASE, \
+ RCAR_SYSRAM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+#define MAP_REG1 MAP_REGION_FLAT(REG1_BASE, \
+ REG1_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_ROM MAP_REGION_FLAT(ROM0_BASE, \
+ ROM0_SIZE, \
+ MT_MEMORY | MT_RO | MT_SECURE)
+
+#define MAP_REG2 MAP_REGION_FLAT(REG2_BASE, \
+ REG2_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_DRAM1 MAP_REGION_FLAT(DRAM_40BIT_BASE, \
+ DRAM_40BIT_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+#endif
+
+#ifdef BL32_BASE
+#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_BASE, \
+ BL32_LIMIT - BL32_BASE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+#endif
+
+#if IMAGE_BL2
+static const mmap_region_t rcar_mmap[] = {
+ MAP_FLASH0, /* 0x08000000 - 0x0BFFFFFF RPC area */
+ MAP_DRAM0, /* 0x40000000 - 0xBFFFFFFF DRAM area(Legacy) */
+ MAP_REG0, /* 0xE6000000 - 0xE62FFFFF SoC register area */
+ MAP_RAM0, /* 0xE6300000 - 0xE6303FFF System RAM area */
+ MAP_REG1, /* 0xE6400000 - 0xEAFFFFFF SoC register area */
+ MAP_ROM, /* 0xEB100000 - 0xEB127FFF boot ROM area */
+ MAP_REG2, /* 0xEC000000 - 0xFFFFFFFF SoC register area */
+ MAP_DRAM1, /* 0x0400000000 - 0x07FFFFFFFF DRAM area(4GB over) */
+ {0}
+};
+#endif
+
+#if IMAGE_BL31
+static const mmap_region_t rcar_mmap[] = {
+ MAP_SHARED_RAM,
+ MAP_ATFW_CRASH,
+ MAP_ATFW_LOG,
+ MAP_DEVICE_RCAR,
+ MAP_DEVICE_RCAR2,
+ MAP_SRAM,
+ MAP_SRAM_STACK,
+ {0}
+};
+#endif
+
+#if IMAGE_BL32
+static const mmap_region_t rcar_mmap[] = {
+ MAP_DEVICE0,
+ MAP_DEVICE1,
+ {0}
+};
+#endif
+
+CASSERT(ARRAY_SIZE(rcar_mmap) + RCAR_BL_REGIONS
+ <= MAX_MMAP_REGIONS, assert_max_mmap_regions);
+
+/*
+ * Macro generating the code for the function setting up the pagetables as per
+ * the platform memory map & initialize the mmu, for the given exception level
+ */
+#if USE_COHERENT_MEM
+void rcar_configure_mmu_el3(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long ro_start,
+ unsigned long ro_limit,
+ unsigned long coh_start,
+ unsigned long coh_limit)
+{
+ mmap_add_region(total_base, total_base, total_size,
+ MT_MEMORY | MT_RW | MT_SECURE);
+ mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
+ MT_MEMORY | MT_RO | MT_SECURE);
+ mmap_add_region(coh_start, coh_start, coh_limit - coh_start,
+ MT_DEVICE | MT_RW | MT_SECURE);
+ mmap_add(rcar_mmap);
+
+ init_xlat_tables();
+ enable_mmu_el3(0);
+}
+#else
+void rcar_configure_mmu_el3(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long ro_start,
+ unsigned long ro_limit)
+{
+ mmap_add_region(total_base, total_base, total_size,
+ MT_MEMORY | MT_RW | MT_SECURE);
+ mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
+ MT_MEMORY | MT_RO | MT_SECURE);
+ mmap_add(rcar_mmap);
+
+ init_xlat_tables();
+ enable_mmu_el3(0);
+}
+#endif
+
+uintptr_t plat_get_ns_image_entrypoint(void)
+{
+#if (IMAGE_BL2)
+ uint32_t cert, len;
+ uintptr_t dst;
+ int32_t ret;
+
+ ret = rcar_get_certificate(NON_TRUSTED_FW_CONTENT_CERT_ID, &cert);
+ if (ret) {
+ ERROR("%s : cert file load error", __func__);
+ return NS_IMAGE_OFFSET;
+ }
+
+ rcar_read_certificate((uint64_t) cert, &len, &dst);
+
+ return dst;
+#else
+ return NS_IMAGE_OFFSET;
+#endif
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ unsigned int freq;
+
+ freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
+ if (freq == 0)
+ panic();
+
+ return freq;
+}
+
+void plat_rcar_gic_init(void)
+{
+ gicv2_distif_init();
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+}
+
+static const interrupt_prop_t interrupt_props[] = {
+#if IMAGE_BL2
+ INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+#else
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+ INTR_PROP_DESC(ARM_IRQ_SEC_RPC, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+ INTR_PROP_DESC(ARM_IRQ_SEC_TIMER, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+ INTR_PROP_DESC(ARM_IRQ_SEC_TIMER_UP, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+ INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+ INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+ INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_SecPKA, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+ INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_PubPKA, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+#endif
+};
+
+static const gicv2_driver_data_t plat_gicv2_driver_data = {
+ .interrupt_props = interrupt_props,
+ .interrupt_props_num = (uint32_t) ARRAY_SIZE(interrupt_props),
+ .gicd_base = RCAR_GICD_BASE,
+ .gicc_base = RCAR_GICC_BASE,
+};
+
+void plat_rcar_gic_driver_init(void)
+{
+ gicv2_driver_init(&plat_gicv2_driver_data);
+}
lib/cpus/aarch64/cortex_a57.S \
${LIBFDT_SRCS} \
common/desc_image_load.c \
+ plat/renesas/common/aarch64/platform_common.c \
+ plat/renesas/common/aarch64/plat_helpers.S \
drivers/renesas/common/console/rcar_printf.c \
drivers/renesas/common/scif/scif.S \
drivers/renesas/common/common.c \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
plat/common/plat_psci_common.c \
+ plat/renesas/common/aarch64/plat_helpers.S \
+ plat/renesas/common/aarch64/platform_common.c \
drivers/renesas/common/console/rcar_console.S \
drivers/renesas/common/console/rcar_printf.c \
drivers/renesas/common/delay/micro_delay.c \
+++ /dev/null
-/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <common/runtime_svc.h>
-#include <cortex_a57.h>
-#include <platform_def.h>
-
-#include "rcar_def.h"
-
- .globl plat_get_my_entrypoint
- .extern plat_set_my_stack
- .globl platform_mem_init
-
- .globl plat_crash_console_init
- .globl plat_crash_console_putc
- .globl plat_crash_console_flush
- .globl plat_invalidate_icache
- .globl plat_report_exception
- .globl plat_secondary_reset
- .globl plat_reset_handler
- .globl plat_my_core_pos
- .extern rcar_log_init
-
- .extern console_rcar_init
- .extern console_rcar_putc
- .extern console_rcar_flush
-
-#if IMAGE_BL2
- #define INT_ID_MASK (0x3ff)
- .extern bl2_interrupt_error_type
- .extern bl2_interrupt_error_id
- .globl bl2_enter_bl31
- .extern gicv2_acknowledge_interrupt
- .extern rcar_swdt_exec
-#endif
-
- /* -----------------------------------------------------
- * void platform_get_core_pos (mpidr)
- * -----------------------------------------------------
- */
-func platform_get_core_pos
- and x1, x0, #MPIDR_CPU_MASK
- and x0, x0, #MPIDR_CLUSTER_MASK
- add x0, x1, x0, LSR #6
- ret
-endfunc platform_get_core_pos
-
- /* -----------------------------------------------------
- * void platform_my_core_pos
- * -----------------------------------------------------
- */
-func plat_my_core_pos
- mrs x0, mpidr_el1
- b platform_get_core_pos
-endfunc plat_my_core_pos
-
- /* -----------------------------------------------------
- * void platform_get_my_entrypoint (unsigned int mpid);
- *
- * Main job of this routine is to distinguish between
- * a cold and warm boot.
- * On a cold boot the secondaries first wait for the
- * platform to be initialized after which they are
- * hotplugged in. The primary proceeds to perform the
- * platform initialization.
- * On a warm boot, each cpu jumps to the address in its
- * mailbox.
- *
- * TODO: Not a good idea to save lr in a temp reg
- * -----------------------------------------------------
- */
-func plat_get_my_entrypoint
- mrs x0, mpidr_el1
- mov x9, x30 /* lr */
-
-#if defined(IMAGE_BL2)
- /* always cold boot on bl2 */
- mov x0, #0
- ret x9
-#else
- ldr x1, =BOOT_KIND_BASE
- ldr x21, [x1]
-
- /* Check the reset info */
- and x1, x21, #0x000c
- cmp x1, #0x0008
- beq el3_panic
- cmp x1, #0x000c
- beq el3_panic
-
- /* Check the boot kind */
- and x1, x21, #0x0003
- cmp x1, #0x0002
- beq el3_panic
- cmp x1, #0x0003
- beq el3_panic
-
- /* warm boot or cold boot */
- and x1, x21, #1
- cmp x1, #0
- bne warm_reset
-
- /* Cold boot */
- mov x0, #0
- b exit
-
-warm_reset:
- /* --------------------------------------------------------------------
- * A per-cpu mailbox is maintained in the trusted SDRAM. Its flushed out
- * of the caches after every update using normal memory so its safe to
- * read it here with SO attributes
- * ---------------------------------------------------------------------
- */
- ldr x10, =MBOX_BASE
- bl platform_get_core_pos
- lsl x0, x0, #CACHE_WRITEBACK_SHIFT
- ldr x0, [x10, x0]
- cbz x0, _panic
-exit:
- ret x9
-_panic:
- b do_panic
-#endif
-
-endfunc plat_get_my_entrypoint
-
- /* ---------------------------------------------
- * plat_secondary_reset
- *
- * ---------------------------------------------
- */
-func plat_secondary_reset
- mrs x0, sctlr_el3
- bic x0, x0, #SCTLR_EE_BIT
- msr sctlr_el3, x0
- isb
-
- mrs x0, cptr_el3
- bic w0, w0, #TCPAC_BIT
- bic w0, w0, #TTA_BIT
- bic w0, w0, #TFP_BIT
- msr cptr_el3, x0
-
- mov_imm x0, PARAMS_BASE
- mov_imm x2, BL31_BASE
- ldr x3, =BOOT_KIND_BASE
- mov x1, #0x1
- str x1, [x3]
- br x2 /* jump to BL31 */
- nop
- nop
- nop
-endfunc plat_secondary_reset
-
- /* ---------------------------------------------
- * plat_enter_bl31
- *
- * ---------------------------------------------
- */
-func bl2_enter_bl31
- mov x20, x0
- /*
- * MMU needs to be disabled because both BL2 and BL31 execute
- * in EL3, and therefore share the same address space.
- * BL31 will initialize the address space according to its
- * own requirement.
- */
-#if RCAR_BL2_DCACHE == 1
- /* Disable mmu and data cache */
- bl disable_mmu_el3
- /* Data cache clean and invalidate */
- mov x0, #DCCISW
- bl dcsw_op_all
- /* TLB invalidate all, EL3 */
- tlbi alle3
-#endif /* RCAR_BL2_DCACHE == 1 */
- bl disable_mmu_icache_el3
- /* Invalidate instruction cache */
- ic iallu
- dsb sy
- isb
- ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
- msr elr_el3, x0
- msr spsr_el3, x1
- exception_return
-endfunc bl2_enter_bl31
-
- /* -----------------------------------------------------
- * void platform_mem_init (void);
- *
- * Zero out the mailbox registers in the shared memory
- * and set the rcar_boot_kind_flag.
- * The mmu is turned off right now and only the primary can
- * ever execute this code. Secondaries will read the
- * mailboxes using SO accesses.
- * -----------------------------------------------------
- */
-func platform_mem_init
-#if !IMAGE_BL2
- ldr x0, =MBOX_BASE
- mov w1, #PLATFORM_CORE_COUNT
-loop:
- str xzr, [x0], #CACHE_WRITEBACK_GRANULE
- subs w1, w1, #1
- b.gt loop
-#endif
- ret
-endfunc platform_mem_init
-
- /* ---------------------------------------------
- * void plat_report_exception(unsigned int type)
- * Function to report an unhandled exception
- * with platform-specific means.
- * ---------------------------------------------
- */
-func plat_report_exception
- /* Switch to SP_EL0 */
- msr spsel, #0
-#if IMAGE_BL2
- mov w1, #FIQ_SP_EL0
- cmp w0, w1
- beq rep_exec_fiq_elx
- b rep_exec_panic_type
-rep_exec_fiq_elx:
- bl gicv2_acknowledge_interrupt
- mov x2, #INT_ID_MASK
- and x0, x0, x2
- mov x1, #ARM_IRQ_SEC_WDT
- cmp x0, x1
- bne rep_exec_panic_id
- mrs x0, ELR_EL3
- b rcar_swdt_exec
-rep_exec_panic_type:
- /* x0 is interrupt TYPE */
- b bl2_interrupt_error_type
-rep_exec_panic_id:
- /* x0 is interrupt ID */
- b bl2_interrupt_error_id
-rep_exec_end:
-#endif
- ret
-endfunc plat_report_exception
-
- /* ---------------------------------------------
- * int plat_crash_console_init(void)
- * Function to initialize log area
- * ---------------------------------------------
- */
-func plat_crash_console_init
-#if IMAGE_BL2
- mov x0, #0
-#else
- mov x1, sp
- mov_imm x2, RCAR_CRASH_STACK
- mov sp, x2
- str x1, [sp, #-16]!
- str x30, [sp, #-16]!
- bl console_rcar_init
- ldr x30, [sp], #16
- ldr x1, [sp], #16
- mov sp, x1
-#endif
- ret
-endfunc plat_crash_console_init
-
- /* ---------------------------------------------
- * int plat_crash_console_putc(int c)
- * Function to store a character to log area
- * ---------------------------------------------
- */
-func plat_crash_console_putc
- mov x1, sp
- mov_imm x2, RCAR_CRASH_STACK
- mov sp, x2
- str x1, [sp, #-16]!
- str x30, [sp, #-16]!
- str x3, [sp, #-16]!
- str x4, [sp, #-16]!
- str x5, [sp, #-16]!
- bl console_rcar_putc
- ldr x5, [sp], #16
- ldr x4, [sp], #16
- ldr x3, [sp], #16
- ldr x30, [sp], #16
- ldr x1, [sp], #16
- mov sp, x1
- ret
-endfunc plat_crash_console_putc
-
- /* ---------------------------------------------
- * void plat_crash_console_flush()
- * ---------------------------------------------
- */
-func plat_crash_console_flush
- b console_rcar_flush
-endfunc plat_crash_console_flush
-
- /* --------------------------------------------------------------------
- * void plat_reset_handler(void);
- *
- * Before adding code in this function, refer to the guidelines in
- * docs/firmware-design.md to determine whether the code should reside
- * within the FIRST_RESET_HANDLER_CALL block or not.
- *
- * For R-Car H3:
- * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
- * - Set the L2 Data setup latency to 1 (i.e. 1 cycles) for Cortex-A57
- * - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57
- * For R-Car M3/M3N:
- * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
- * - Set the L2 Data setup latency to 0 (i.e. 0 cycles) for Cortex-A57
- * - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57
- *
- * --------------------------------------------------------------------
- */
-func plat_reset_handler
- /*
- * On R-Car H3 : x2 := 0
- * On R-Car M3/M3N: x2 := 1
- */
- /* read PRR */
- ldr x0, =0xFFF00044
- ldr w0, [x0]
- ubfx w0, w0, 8, 8
- /* H3? */
- cmp w0, #0x4F
- b.eq RCARH3
- /* set R-Car M3/M3N */
- mov x2, #1
- b CHK_A5x
-RCARH3:
- /* set R-Car H3 */
- mov x2, #0
- /* --------------------------------------------------------------------
- * Determine whether this code is executed on a Cortex-A53 or on a
- * Cortex-A57 core.
- * --------------------------------------------------------------------
- */
-CHK_A5x:
- mrs x0, midr_el1
- ubfx x1, x0, MIDR_PN_SHIFT, #12
- cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
- b.eq A57
- ret
-A57:
- /* Get data from CORTEX_A57_L2CTLR_EL1 */
- mrs x0, CORTEX_A57_L2CTLR_EL1
- /*
- * On R-Car H3/M3/M3N
- *
- * L2 Tag RAM latency is bit8-6 of CORTEX_A57_L2CTLR_EL1
- * L2 Data RAM setup is bit5 of CORTEX_A57_L2CTLR_EL1
- * L2 Data RAM latency is bit2-0 of CORTEX_A57_L2CTLR_EL1
- */
- /* clear bit of L2 RAM */
- /* ~(0x1e7) -> x1 */
- mov x1, #0x1e7
- neg x1, x1
- /* clear bit of L2 RAM -> x0 */
- and x0, x0, x1
- /* L2 Tag RAM latency (3 cycles) */
- orr x0, x0, #0x2 << 6
- /* If M3/M3N then L2 RAM setup is 0 */
- cbnz x2, M3_L2
- /* L2 Data RAM setup (1 cycle) */
- orr x0, x0, #0x1 << 5
-M3_L2:
- /* L2 Data RAM latency (4 cycles) */
- orr x0, x0, #0x3
- /* Store data to L2CTLR_EL1 */
- msr CORTEX_A57_L2CTLR_EL1, x0
-apply_l2_ram_latencies:
- ret
-endfunc plat_reset_handler
-
- /* ---------------------------------------------
- * void plat_invalidate_icache(void)
- * Instruction Cache Invalidate All to PoU
- * ---------------------------------------------
- */
-func plat_invalidate_icache
- ic iallu
-
- ret
-endfunc plat_invalidate_icache
+++ /dev/null
-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <common/interrupt_props.h>
-#include <drivers/arm/gicv2.h>
-#include <drivers/arm/gic_common.h>
-#include <lib/mmio.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include <plat/common/platform.h>
-
-#include "rcar_def.h"
-#include "rcar_private.h"
-#include "rcar_version.h"
-
-#if (IMAGE_BL2)
-extern void rcar_read_certificate(uint64_t cert, uint32_t *len, uintptr_t *p);
-extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert);
-#endif
-
-const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
- __attribute__ ((__section__("ro"))) = VERSION_OF_RENESAS;
-
-#define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \
- RCAR_SHARED_MEM_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-
-#define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
- FLASH0_SIZE, \
- MT_MEMORY | MT_RO | MT_SECURE)
-
-#define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
- DRAM1_NS_SIZE, \
- MT_MEMORY | MT_RW | MT_NS)
-
-#define MAP_DEVICE_RCAR MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
- DEVICE_RCAR_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define MAP_DEVICE_RCAR2 MAP_REGION_FLAT(DEVICE_RCAR_BASE2, \
- DEVICE_RCAR_SIZE2, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define MAP_SRAM MAP_REGION_FLAT(DEVICE_SRAM_BASE, \
- DEVICE_SRAM_SIZE, \
- MT_MEMORY | MT_RO | MT_SECURE)
-
-#define MAP_SRAM_STACK MAP_REGION_FLAT(DEVICE_SRAM_STACK_BASE, \
- DEVICE_SRAM_STACK_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-
-#define MAP_ATFW_CRASH MAP_REGION_FLAT(RCAR_BL31_CRASH_BASE, \
- RCAR_BL31_CRASH_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-
-#define MAP_ATFW_LOG MAP_REGION_FLAT(RCAR_BL31_LOG_BASE, \
- RCAR_BL31_LOG_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-#if IMAGE_BL2
-#define MAP_DRAM0 MAP_REGION_FLAT(DRAM1_BASE, \
- DRAM1_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-
-#define MAP_REG0 MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
- DEVICE_RCAR_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define MAP_RAM0 MAP_REGION_FLAT(RCAR_SYSRAM_BASE, \
- RCAR_SYSRAM_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-
-#define MAP_REG1 MAP_REGION_FLAT(REG1_BASE, \
- REG1_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define MAP_ROM MAP_REGION_FLAT(ROM0_BASE, \
- ROM0_SIZE, \
- MT_MEMORY | MT_RO | MT_SECURE)
-
-#define MAP_REG2 MAP_REGION_FLAT(REG2_BASE, \
- REG2_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define MAP_DRAM1 MAP_REGION_FLAT(DRAM_40BIT_BASE, \
- DRAM_40BIT_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-#endif
-
-#ifdef BL32_BASE
-#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_BASE, \
- BL32_LIMIT - BL32_BASE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-#endif
-
-#if IMAGE_BL2
-static const mmap_region_t rcar_mmap[] = {
- MAP_FLASH0, /* 0x08000000 - 0x0BFFFFFF RPC area */
- MAP_DRAM0, /* 0x40000000 - 0xBFFFFFFF DRAM area(Legacy) */
- MAP_REG0, /* 0xE6000000 - 0xE62FFFFF SoC register area */
- MAP_RAM0, /* 0xE6300000 - 0xE6303FFF System RAM area */
- MAP_REG1, /* 0xE6400000 - 0xEAFFFFFF SoC register area */
- MAP_ROM, /* 0xEB100000 - 0xEB127FFF boot ROM area */
- MAP_REG2, /* 0xEC000000 - 0xFFFFFFFF SoC register area */
- MAP_DRAM1, /* 0x0400000000 - 0x07FFFFFFFF DRAM area(4GB over) */
- {0}
-};
-#endif
-
-#if IMAGE_BL31
-static const mmap_region_t rcar_mmap[] = {
- MAP_SHARED_RAM,
- MAP_ATFW_CRASH,
- MAP_ATFW_LOG,
- MAP_DEVICE_RCAR,
- MAP_DEVICE_RCAR2,
- MAP_SRAM,
- MAP_SRAM_STACK,
- {0}
-};
-#endif
-
-#if IMAGE_BL32
-static const mmap_region_t rcar_mmap[] = {
- MAP_DEVICE0,
- MAP_DEVICE1,
- {0}
-};
-#endif
-
-CASSERT(ARRAY_SIZE(rcar_mmap) + RCAR_BL_REGIONS
- <= MAX_MMAP_REGIONS, assert_max_mmap_regions);
-
-/*
- * Macro generating the code for the function setting up the pagetables as per
- * the platform memory map & initialize the mmu, for the given exception level
- */
-#if USE_COHERENT_MEM
-void rcar_configure_mmu_el3(unsigned long total_base,
- unsigned long total_size,
- unsigned long ro_start,
- unsigned long ro_limit,
- unsigned long coh_start,
- unsigned long coh_limit)
-{
- mmap_add_region(total_base, total_base, total_size,
- MT_MEMORY | MT_RW | MT_SECURE);
- mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
- MT_MEMORY | MT_RO | MT_SECURE);
- mmap_add_region(coh_start, coh_start, coh_limit - coh_start,
- MT_DEVICE | MT_RW | MT_SECURE);
- mmap_add(rcar_mmap);
-
- init_xlat_tables();
- enable_mmu_el3(0);
-}
-#else
-void rcar_configure_mmu_el3(unsigned long total_base,
- unsigned long total_size,
- unsigned long ro_start,
- unsigned long ro_limit)
-{
- mmap_add_region(total_base, total_base, total_size,
- MT_MEMORY | MT_RW | MT_SECURE);
- mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
- MT_MEMORY | MT_RO | MT_SECURE);
- mmap_add(rcar_mmap);
-
- init_xlat_tables();
- enable_mmu_el3(0);
-}
-#endif
-
-uintptr_t plat_get_ns_image_entrypoint(void)
-{
-#if (IMAGE_BL2)
- uint32_t cert, len;
- uintptr_t dst;
- int32_t ret;
-
- ret = rcar_get_certificate(NON_TRUSTED_FW_CONTENT_CERT_ID, &cert);
- if (ret) {
- ERROR("%s : cert file load error", __func__);
- return NS_IMAGE_OFFSET;
- }
-
- rcar_read_certificate((uint64_t) cert, &len, &dst);
-
- return dst;
-#else
- return NS_IMAGE_OFFSET;
-#endif
-}
-
-unsigned int plat_get_syscnt_freq2(void)
-{
- unsigned int freq;
-
- freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
- if (freq == 0)
- panic();
-
- return freq;
-}
-
-void plat_rcar_gic_init(void)
-{
- gicv2_distif_init();
- gicv2_pcpu_distif_init();
- gicv2_cpuif_enable();
-}
-
-static const interrupt_prop_t interrupt_props[] = {
-#if IMAGE_BL2
- INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
-#else
- INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
- INTR_PROP_DESC(ARM_IRQ_SEC_RPC, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
- INTR_PROP_DESC(ARM_IRQ_SEC_TIMER, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
- INTR_PROP_DESC(ARM_IRQ_SEC_TIMER_UP, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
- INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
- INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
- INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_SecPKA, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
- INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_PubPKA, GIC_HIGHEST_SEC_PRIORITY,
- GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
-#endif
-};
-
-static const gicv2_driver_data_t plat_gicv2_driver_data = {
- .interrupt_props = interrupt_props,
- .interrupt_props_num = (uint32_t) ARRAY_SIZE(interrupt_props),
- .gicd_base = RCAR_GICD_BASE,
- .gicc_base = RCAR_GICC_BASE,
-};
-
-void plat_rcar_gic_driver_init(void)
-{
- gicv2_driver_init(&plat_gicv2_driver_data);
-}
-Idrivers/renesas/common/pwrc \
-Idrivers/renesas/common/io
-BL2_SOURCES += plat/renesas/rcar/aarch64/platform_common.c \
- plat/renesas/rcar/aarch64/plat_helpers.S \
- plat/renesas/rcar/bl2_interrupt_error.c \
+BL2_SOURCES += plat/renesas/rcar/bl2_interrupt_error.c \
plat/renesas/rcar/bl2_secure_setting.c \
plat/renesas/rcar/bl2_plat_setup.c \
plat/renesas/rcar/plat_storage.c \
drivers/renesas/rcar/board/board.c
BL31_SOURCES += plat/renesas/rcar/plat_topology.c \
- plat/renesas/rcar/aarch64/plat_helpers.S \
- plat/renesas/rcar/aarch64/platform_common.c \
plat/renesas/rcar/bl31_plat_setup.c \
plat/renesas/rcar/plat_pm.c
projects / arm-tf.git / commitdiff