dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
+dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \
+ at91sam9g25-gardena-smart-gateway.dtb
+
dtb-$(CONFIG_TARGET_ETHERNUT5) += ethernut5.dtb
dtb-$(CONFIG_TARGET_USB_A9263) += usb_a9263.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+&dbgu {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for the GARDENA smart Gateway (AT91SAM)
+ *
+ * Copyright (C) 2012 Atmel,
+ * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ */
+
+/dts-v1/;
+
+#include "at91sam9g25.dtsi"
+
+/ {
+ model = "GARDENA smart Gateway (AT91SAM)";
+ compatible = "gardena,smart-gateway-at91sam", "atmel,at91sam9";
+
+ aliases {
+ serial0 = &dbgu;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x20000000 0x8000000>;
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power_blue {
+ label = "smartgw:power:blue";
+ gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ power_green {
+ label = "smartgw:power:green";
+ gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ power_red {
+ label = "smartgw:power:red";
+ gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ radio_blue {
+ label = "smartgw:radio:blue";
+ gpios = <&pioC 18 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ radio_green {
+ label = "smartgw:radio:green";
+ gpios = <&pioC 17 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ radio_red {
+ label = "smartgw:radio:red";
+ gpios = <&pioC 16 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ internet_blue {
+ label = "smartgw:internet:blue";
+ gpios = <&pioC 15 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ internet_green {
+ label = "smartgw:internet:green";
+ gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ internet_red {
+ label = "smartgw:internet:red";
+ gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&dbgu {
+ status = "okay";
+};
+
+&macb0 {
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&nand0 {
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ atmel,has-pmecc; /* Enable PMECC */
+ atmel,pmecc-cap = <2>;
+ atmel,pmecc-sector-size = <512>;
+ nand-on-flash-bbt;
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+ timeout-sec = <16>;
+};
select BOARD_LATE_INIT
select SUPPORT_SPL
+config TARGET_GARDENA_SMART_GATEWAY_AT91SAM
+ bool "GARDENA smart Gateway (AT91SAM)"
+ select AT91SAM9X5
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select SUPPORT_SPL
+
config TARGET_SAMA5D2_PTC_EK
bool "SAMA5D2 PTC EK board"
select BOARD_EARLY_INIT_F
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
+source "board/gardena/smart-gateway-at91sam/Kconfig"
source "board/l+g/vinco/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
source "board/ronetix/pm9261/Kconfig"
--- /dev/null
+if TARGET_GARDENA_SMART_GATEWAY_AT91SAM
+
+config SYS_BOARD
+ default "smart-gateway-at91sam"
+
+config SYS_VENDOR
+ default "gardena"
+
+config SYS_CONFIG_NAME
+ default "gardena-smart-gateway-at91sam"
+
+endif
--- /dev/null
+GARDENA_SMART_GATEWAY_AT91SAM BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/gardena/smart-gateway-at91sam/
+F: include/configs/gardena-smart-gateway-at91sam.h
+F: configs/gardena-smart-gateway-at91sam_defconfig
+F: arch/arm/dts/gardena-smart-gateway-at91sam.dts
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += board.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ * Copyright (C) 2019 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <led.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void at91_prepare_cpu_var(void)
+{
+ env_set("cpu", get_cpu_name());
+}
+
+int board_late_init(void)
+{
+ at91_prepare_cpu_var();
+
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ at91_seriald_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ * Copyright (C) 2019 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <spl.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+
+static void at91sam9x5ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+
+ /* NAND flash on D16 */
+ csa |= AT91_MATRIX_NFD0_ON_D16;
+
+ /* Configure IO drive */
+ csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(1),
+ &smc->cs[3].mode);
+
+ at91_periph_clk_enable(ATMEL_ID_PIOCD);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
+}
+
+void at91_spl_board_init(void)
+{
+ at91sam9x5ek_nand_hw_init();
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_13 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+ ddr2->rtr = 0x411;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct atmel_mpddrc_config ddr2;
+ unsigned long csa;
+
+ ddr2_conf(&ddr2);
+
+ /* Enable DDR2 clock */
+ writel(AT91_PMC_DDR, &pmc->scer);
+
+ /* Chip select 1 is for DDR2/SDRAM */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+ csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+ csa |= AT91_MATRIX_EBI_DBPD_OFF;
+ csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+ writel(csa, &matrix->ebicsa);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
+}
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_ARCH_AT91=y
+CONFIG_SYS_TEXT_BASE=0x22900000
+CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xfffff200
+CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_SMBIOS_PRODUCT_NAME="at91sam9x5ek"
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_NAND_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_TPL_BANNER_PRINT is not set
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DM=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand0"
+CONFIG_MTDPARTS_DEFAULT="nand0:1536k(uboot),1024k(unused),512k(dtb_old),4608k(kernel_old),86528k(ubi),-(rootfs_old)"
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupts interrupt-parent interrupts-extended dmas dma-names"
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_BLK=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_DM_GPIO=y
+CONFIG_AT91_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+# CONFIG_MMC is not set
+CONFIG_NAND_ATMEL=y
+CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
+# CONFIG_CONFIG_UBI_SILENCE_MSG is not set
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_ATMEL_USART=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+# CONFIG_SYS_WHITE_ON_BLACK is not set
+CONFIG_WATCHDOG=y
+CONFIG_WDT=y
+CONFIG_WDT_AT91=y
+# CONFIG_UBIFS_SILENCE_MSG is not set
+CONFIG_USE_TINY_PRINTF=y
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ * Copyright (C) 2019 Stefan Roese <sr@denx.de>
+ *
+ * Configuation settings for the GARDENA smart Gateway (AT91SAM9G25)
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
+
+/* NAND flash */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+/* environment organization */
+#define CONFIG_ENV_UBI_PART "ubi"
+#define CONFIG_ENV_UBI_VOLUME "env"
+#define CONFIG_ENV_UBI_VOLUME_REDUND "env_r"
+#define CONFIG_ENV_SIZE (64 << 10)
+
+/* SPL */
+#define CONFIG_SPL_TEXT_BASE 0x300000
+#define CONFIG_SPL_MAX_SIZE 0x7000
+#define CONFIG_SPL_STACK 0x308000
+
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
+#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CONFIG_SYS_AT91_PLLA 0x20c73f03
+#define CONFIG_SYS_MCKR 0x1301
+#define CONFIG_SYS_MCKR_CSS 0x1302
+
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
+
+#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
+
+#endif
projects / uboot.git / commitdiff