drm/i915/tgl: Don't treat unslice registers as masked

The UNSLICE_UNIT_LEVEL_CLKGATE and UNSLICE_UNIT_LEVEL_CLKGATE2 registers
that we update in a few engine workarounds are not masked registers
(i.e., we don't have to write a mask bit in the top 16 bits when
updating one of the lower 16 bits).  As such, these workarounds should
be applied via wa_write_or() rather than wa_masked_en()

v2:
 - Rebase

Reported-by: Nick Desaulniers <ndesaulniers@google.com>
Reported-by: kernelci.org bot <bot@kernelci.org>
References: https://github.com/ClangBuiltLinux/linux/issues/918
Fixes: f85de99d49d2 ("drm/i915/tgl: Move and restrict Wa_1408615072")
Fixes: e3747f971acc ("drm/i915/gen11: Moving WAs to rcs_engine_wa_init()")
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Tested-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200306171139.1414649-1-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1d42bea21ab08d3d1e8b4654b07510db6b00f1a6..391f39b1fb2665fda666d879dab784496b3b1785 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1382,8 +1382,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
 
                /* Wa_1408615072:tgl */
-               wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
-                            VSUNIT_CLKGATE_DIS_TGL);
+               wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
+                           VSUNIT_CLKGATE_DIS_TGL);
        }
 
        if (IS_TIGERLAKE(i915)) {
@@ -1472,12 +1472,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                 * Wa_1408615072:icl,ehl  (vsunit)
                 * Wa_1407596294:icl,ehl  (hsunit)
                 */
-               wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
-                            VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
+               wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
+                           VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
 
                /* Wa_1407352427:icl,ehl */
-               wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
-                            PSDUNIT_CLKGATE_DIS);
+               wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
+                           PSDUNIT_CLKGATE_DIS);
        }
 
        if (IS_GEN_RANGE(i915, 9, 12)) {