]> git.baikalelectronics.ru Git - uboot.git/commitdiff
Convert CONFIG_SYS_FSL_MAX_NUM_OF_SEC to Kconfig
authorTom Rini <trini@konsulko.com>
Mon, 1 Aug 2022 01:08:26 +0000 (21:08 -0400)
committerTom Rini <trini@konsulko.com>
Fri, 12 Aug 2022 20:10:49 +0000 (16:10 -0400)
This converts the following to Kconfig:
   CONFIG_SYS_FSL_MAX_NUM_OF_SEC

Signed-off-by: Tom Rini <trini@konsulko.com>
arch/arm/include/asm/arch-fsl-layerscape/config.h
arch/arm/include/asm/arch-imx8/imx-regs.h
arch/arm/include/asm/arch-imx8m/imx-regs.h
arch/arm/include/asm/arch-ls102xa/config.h
arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-mx7/imx-regs.h
arch/arm/include/asm/arch-mx7ulp/imx-regs.h
arch/powerpc/include/asm/config_mpc85xx.h
drivers/crypto/fsl/Kconfig

index 587d585412bb72de736dbd844461c61abeeb9e1e..1b108dde535512caa1f4ba2a6ee5533bf966956b 100644 (file)
@@ -94,8 +94,6 @@
 #define EPU_EPCTR5             0x700060a14ULL
 #define EPU_EPGCR              0x700060000ULL
 
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
-
 #elif defined(CONFIG_ARCH_LS1088A)
 #define CONFIG_SYS_FSL_NUM_CC_PLLS             3
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1 }
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
 /* DCFG - GUR */
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE       0x00200000 /* 2M space */
 #define CONFIG_SYS_FSL_OCRAM_SIZE      0x00020000 /* Real size 128K */
 
 /* DCFG - GUR */
 
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
-
 #elif defined(CONFIG_ARCH_LS1028A)
 #define CONFIG_SYS_FSL_NUM_CC_PLLS             3
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1 }
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
 /* SEC */
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 
 /* DCFG - GUR */
 
 #define GIC_ADDR_BIT           31
 #define SCFG_GIC400_ALIGN      0x1570188
 
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
-
 #elif defined(CONFIG_ARCH_LS1012A)
 #define GICD_BASE              0x01401000
 #define GICC_BASE              0x01402000
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC           1
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE              0x01410000
 #define GICC_BASE              0x01420000
-
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 #else
 #error SoC not defined
 #endif
index 2d64b0604b92e33a9ec2900568dcf38456a86887..3d32b7a02a183b985dbc74d13e72b90360f2bdfa 100644 (file)
@@ -48,6 +48,5 @@
 #define USB_PHY0_BASE_ADDR     0x5b100000
 
 #define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 
 #endif /* __ASM_ARCH_IMX8_REGS_H__ */
index 6969cde26cc85b1bd5c832729799b6a1db3f1f28..ff3b9ddd9f777b42fdf886575829b03eeebb1f07 100644 (file)
@@ -92,7 +92,6 @@
 #define CONFIG_SYS_FSL_JR0_OFFSET       (0x1000)
 #define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
                                         CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC   1
 #if !defined(__ASSEMBLY__)
 #include <asm/types.h>
 #include <linux/bitops.h>
index 1b2be8fcde79d0ab395575a77c02b8e0b99495cb..0e32828b4f1eb97dcffb2efd4a4452dd7964b6b8 100644 (file)
@@ -82,7 +82,6 @@
 #define DCU_LAYER_MAX_NUM                      16
 
 #ifdef CONFIG_ARCH_LS1021A
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 #else
 #error SoC not defined
 #endif
index a8a5bf7a5754a1a80d5393faf26686d59fe2776a..56b3a58d478aaf1b76d7805dd8cdf93853ab181f 100644 (file)
 #define CONFIG_SYS_FSL_JR0_OFFSET   0x1000
 #define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + \
                                     CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 
 #define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
index 5cab12f30d88166018e97c56d736c9c3ad89ccb0..1e9d11b7a5c1cb90b4c1757649e5825c3bd78daa 100644 (file)
 #define CONFIG_SYS_FSL_JR0_OFFSET       0x1000
 #define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
                                         CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC   1
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/mach-imx/regs-lcdif.h>
 #include <asm/types.h>
index cb0c2c15c03b4b397075dc3d2099b9bb274b71b2..ffa170f4d2553022f6c962148831ee8943ca1771 100644 (file)
 #define CONFIG_SYS_FSL_JR0_OFFSET       0x1000
 #define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
                                         CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC   1
 
 #define IOMUXC_DPCR_DDR_DQS0   ((IOMUXC_DDR_RBASE + (4 * 32)))
 #define IOMUXC_DPCR_DDR_DQS1   ((IOMUXC_DDR_RBASE + (4 * 33)))
index 543b0c55358e75475f2e6e7cc07338db6cbbb7e3..b5b59a015046b15b1bca01c3bcbebf446c3485a8 100644 (file)
 #define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_TSECV2_1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  3
 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET  0x20000
 
 #endif
 
-#if !defined(CONFIG_ARCH_C29X)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
-#endif
-
 #endif /* _ASM_MPC85xx_CONFIG_H_ */
index e03fcdd9c7e49c621d801286a5146f9757bf6fab..b04c70183d24c8173d583af2609a84afd855a17f 100644 (file)
@@ -10,6 +10,11 @@ config FSL_CAAM
          Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses
          Job Ring as interface to communicate with CAAM.
 
+config SYS_FSL_MAX_NUM_OF_SEC
+       int "Number of job rings in the CAAM"
+       depends on FSL_CAAM
+       default 1
+
 config CAAM_64BIT
        bool
        default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8