crypto: hisilicon/sec - only HW V2 needs to change the BD err detection

The base register address of V2 and V3 are different. HW V3 not needs
to change the BD err detection.

Signed-off-by: Kai Ye <yekai13@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c
index bdb690aaed12ac9dfef5691e01e4991b5e4b871e..2c0be91c0b094a6f4160ee412c388d54b69d4914 100644 (file)
--- a/drivers/crypto/hisilicon/sec2/sec_main.c
+++ b/drivers/crypto/hisilicon/sec2/sec_main.c
@@ -508,16 +508,17 @@ static int sec_engine_init(struct hisi_qm *qm)
 
        writel(SEC_SAA_ENABLE, qm->io_base + SEC_SAA_EN_REG);
 
-       /* HW V2 enable sm4 extra mode, as ctr/ecb */
-       if (qm->ver < QM_HW_V3)
+       if (qm->ver < QM_HW_V3) {
+               /* HW V2 enable sm4 extra mode, as ctr/ecb */
                writel_relaxed(SEC_BD_ERR_CHK_EN0,
                               qm->io_base + SEC_BD_ERR_CHK_EN_REG0);
 
-       /* Enable sm4 xts mode multiple iv */
-       writel_relaxed(SEC_BD_ERR_CHK_EN1,
-                      qm->io_base + SEC_BD_ERR_CHK_EN_REG1);
-       writel_relaxed(SEC_BD_ERR_CHK_EN3,
-                      qm->io_base + SEC_BD_ERR_CHK_EN_REG3);
+               /* HW V2 enable sm4 xts mode multiple iv */
+               writel_relaxed(SEC_BD_ERR_CHK_EN1,
+                              qm->io_base + SEC_BD_ERR_CHK_EN_REG1);
+               writel_relaxed(SEC_BD_ERR_CHK_EN3,
+                              qm->io_base + SEC_BD_ERR_CHK_EN_REG3);
+       }
 
        /* config endian */
        sec_set_endian(qm);