net: mvpp2: improve Packet Processor version check

Use >= MVPP22 instead of != MVPP21.
Non functional change.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 9127dc29d52bbae6c977bc08eecf1e8c60e0318a..4e1a24c0aa3dd8cb35625ce7923e746b77b41b90 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -329,7 +329,7 @@ static int mvpp2_get_nrxqs(struct mvpp2 *priv)
 {
        unsigned int nrxqs;
 
-       if (priv->hw_version != MVPP21 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
+       if (priv->hw_version >= MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
                return 1;
 
        /* According to the PPv2.2 datasheet and our experiments on
@@ -469,7 +469,7 @@ static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
                                      MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
        *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
 
-       if (priv->hw_version != MVPP21) {
+       if (priv->hw_version >= MVPP22) {
                u32 val;
                u32 dma_addr_highbits, phys_addr_highbits;
 
@@ -963,7 +963,7 @@ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
        if (test_bit(thread, &port->priv->lock_map))
                spin_lock_irqsave(&port->bm_lock[thread], flags);
 
-       if (port->priv->hw_version != MVPP21) {
+       if (port->priv->hw_version >= MVPP22) {
                u32 val = 0;
 
                if (sizeof(dma_addr_t) == 8)
@@ -1462,7 +1462,7 @@ static bool mvpp2_port_supports_xlg(struct mvpp2_port *port)
 
 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
 {
-       return !(port->priv->hw_version != MVPP21 && port->gop_id == 0);
+       return !(port->priv->hw_version >= MVPP22 && port->gop_id == 0);
 }
 
 /* Port configuration routines */
@@ -2125,7 +2125,7 @@ static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
              MVPP2_GMAC_PORT_RESET_MASK;
        writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
 
-       if (port->priv->hw_version != MVPP21 && port->gop_id == 0) {
+       if (port->priv->hw_version >= MVPP22 && port->gop_id == 0) {
                val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
                      ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
                writel(val, port->base + MVPP22_XLG_CTRL0_REG);
@@ -4016,7 +4016,7 @@ static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port,
                                   struct mvpp2_tx_desc *desc)
 {
        /* We only need to clear the low bits */
-       if (port->priv->hw_version != MVPP21)
+       if (port->priv->hw_version >= MVPP22)
                desc->pp22.ptp_descriptor &=
                        cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
 }
@@ -4528,7 +4528,7 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
        /* Enable interrupts on all threads */
        mvpp2_interrupts_enable(port);
 
-       if (port->priv->hw_version != MVPP21)
+       if (port->priv->hw_version >= MVPP22)
                mvpp22_mode_reconfigure(port);
 
        if (port->phylink) {
@@ -4746,7 +4746,7 @@ static int mvpp2_open(struct net_device *dev)
                valid = true;
        }
 
-       if (priv->hw_version != MVPP21 && port->port_irq) {
+       if (priv->hw_version >= MVPP22 && port->port_irq) {
                err = request_irq(port->port_irq, mvpp2_port_isr, 0,
                                  dev->name, port);
                if (err) {
@@ -6399,7 +6399,7 @@ static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode,
                             MVPP2_GMAC_PORT_RESET_MASK,
                             MVPP2_GMAC_PORT_RESET_MASK);
 
-               if (port->priv->hw_version != MVPP21) {
+               if (port->priv->hw_version >= MVPP22) {
                        mvpp22_gop_mask_irq(port);
 
                        phy_power_off(port->comphy);
@@ -6453,7 +6453,7 @@ static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode,
 {
        struct mvpp2_port *port = mvpp2_phylink_to_port(config);
 
-       if (port->priv->hw_version != MVPP21 &&
+       if (port->priv->hw_version >= MVPP22 &&
            port->phy_interface != interface) {
                port->phy_interface = interface;
 
@@ -7200,7 +7200,7 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
        if (dram_target_info)
                mvpp2_conf_mbus_windows(dram_target_info, priv);
 
-       if (priv->hw_version != MVPP21)
+       if (priv->hw_version >= MVPP22)
                mvpp2_axi_init(priv);
 
        /* Disable HW PHY polling */
@@ -7350,7 +7350,7 @@ static int mvpp2_probe(struct platform_device *pdev)
                        priv->global_tx_fc = true;
        }
 
-       if (priv->hw_version != MVPP21 && dev_of_node(&pdev->dev)) {
+       if (priv->hw_version >= MVPP22 && dev_of_node(&pdev->dev)) {
                priv->sysctrl_base =
                        syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
                                                        "marvell,system-controller");
@@ -7363,7 +7363,7 @@ static int mvpp2_probe(struct platform_device *pdev)
                        priv->sysctrl_base = NULL;
        }
 
-       if (priv->hw_version != MVPP21 &&
+       if (priv->hw_version >= MVPP22 &&
            mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
                priv->percpu_pools = 1;
 
@@ -7408,7 +7408,7 @@ static int mvpp2_probe(struct platform_device *pdev)
                if (err < 0)
                        goto err_pp_clk;
 
-               if (priv->hw_version != MVPP21) {
+               if (priv->hw_version >= MVPP22) {
                        priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
                        if (IS_ERR(priv->mg_clk)) {
                                err = PTR_ERR(priv->mg_clk);
@@ -7449,7 +7449,7 @@ static int mvpp2_probe(struct platform_device *pdev)
                return -EINVAL;
        }
 
-       if (priv->hw_version != MVPP21) {
+       if (priv->hw_version >= MVPP22) {
                err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
                if (err)
                        goto err_axi_clk;
@@ -7514,7 +7514,7 @@ static int mvpp2_probe(struct platform_device *pdev)
                goto err_port_probe;
        }
 
-       if (priv->global_tx_fc && priv->hw_version != MVPP21) {
+       if (priv->global_tx_fc && priv->hw_version >= MVPP22) {
                err = mvpp2_enable_global_fc(priv);
                if (err)
                        dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n");
@@ -7536,10 +7536,10 @@ err_axi_clk:
        clk_disable_unprepare(priv->axi_clk);
 
 err_mg_core_clk:
-       if (priv->hw_version != MVPP21)
+       if (priv->hw_version >= MVPP22)
                clk_disable_unprepare(priv->mg_core_clk);
 err_mg_clk:
-       if (priv->hw_version != MVPP21)
+       if (priv->hw_version >= MVPP22)
                clk_disable_unprepare(priv->mg_clk);
 err_gop_clk:
        clk_disable_unprepare(priv->gop_clk);