]> git.baikalelectronics.ru Git - arm-tf.git/commitdiff
drivers: renesas: rpc: Move to common
authorBiju Das <biju.das.jz@bp.renesas.com>
Wed, 16 Dec 2020 11:15:33 +0000 (11:15 +0000)
committerBiju Das <biju.das.jz@bp.renesas.com>
Wed, 13 Jan 2021 13:03:49 +0000 (13:03 +0000)
Move rpc driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I04805d720d95b8edcc14e652f897fadc7f432197

drivers/renesas/common/rpc/rpc_driver.c [new file with mode: 0644]
drivers/renesas/common/rpc/rpc_registers.h [new file with mode: 0644]
drivers/renesas/rcar/rpc/rpc_driver.c [deleted file]
drivers/renesas/rcar/rpc/rpc_registers.h [deleted file]
plat/renesas/common/common.mk
plat/renesas/rcar/platform.mk

diff --git a/drivers/renesas/common/rpc/rpc_driver.c b/drivers/renesas/common/rpc/rpc_driver.c
new file mode 100644 (file)
index 0000000..63de5b8
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "cpg_registers.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
+#include "rpc_registers.h"
+
+#define MSTPSR9_RPC_BIT                (0x00020000U)
+#define RPC_CMNCR_MD_BIT       (0x80000000U)
+#define RPC_PHYCNT_CAL         BIT(31)
+#define RPC_PHYCNT_STRTIM_M3V1 (0x6 << 15UL)
+#define RPC_PHYCNT_STRTIM      (0x7 << 15UL)
+
+static void rpc_enable(void)
+{
+       /* Enable clock supply to RPC. */
+       mstpcr_write(CPG_SMSTPCR9, CPG_MSTPSR9, MSTPSR9_RPC_BIT);
+}
+
+static void rpc_setup(void)
+{
+       uint32_t product, cut, reg, phy_strtim;
+
+       if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT)
+               mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT);
+
+       product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
+       cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
+
+       if ((product ==  PRR_PRODUCT_M3) && (cut < PRR_PRODUCT_30))
+               phy_strtim = RPC_PHYCNT_STRTIM_M3V1;
+       else
+               phy_strtim = RPC_PHYCNT_STRTIM;
+
+       reg = mmio_read_32(RPC_PHYCNT);
+       reg &= ~RPC_PHYCNT_STRTIM;
+       reg |= phy_strtim;
+       mmio_write_32(RPC_PHYCNT, reg);
+       reg |= RPC_PHYCNT_CAL;
+       mmio_write_32(RPC_PHYCNT, reg);
+}
+
+void rcar_rpc_init(void)
+{
+       rpc_enable();
+       rpc_setup();
+}
diff --git a/drivers/renesas/common/rpc/rpc_registers.h b/drivers/renesas/common/rpc/rpc_registers.h
new file mode 100644 (file)
index 0000000..79aea85
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RPC_REGISTERS_H
+#define RPC_REGISTERS_H
+
+#define RPC_BASE       (0xEE200000U)
+#define RPC_CMNCR      (RPC_BASE + 0x0000U)
+#define RPC_SSLDR      (RPC_BASE + 0x0004U)
+#define RPC_DRCR       (RPC_BASE + 0x000CU)
+#define RPC_DRCMR      (RPC_BASE + 0x0010U)
+#define RPC_DRENR      (RPC_BASE + 0x001CU)
+#define RPC_SMCR       (RPC_BASE + 0x0020U)
+#define RPC_SMCMR      (RPC_BASE + 0x0024U)
+#define RPC_SMENR      (RPC_BASE + 0x0030U)
+#define RPC_CMNSR      (RPC_BASE + 0x0048U)
+#define RPC_DRDMCR     (RPC_BASE + 0x0058U)
+#define RPC_DRDRENR    (RPC_BASE + 0x005CU)
+#define RPC_PHYCNT     (RPC_BASE + 0x007CU)
+#define RPC_PHYINT     (RPC_BASE + 0x0088U)
+
+#endif /* RPC_REGISTERS_H */
diff --git a/drivers/renesas/rcar/rpc/rpc_driver.c b/drivers/renesas/rcar/rpc/rpc_driver.c
deleted file mode 100644 (file)
index 63de5b8..0000000
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "cpg_registers.h"
-#include "rcar_def.h"
-#include "rcar_private.h"
-#include "rpc_registers.h"
-
-#define MSTPSR9_RPC_BIT                (0x00020000U)
-#define RPC_CMNCR_MD_BIT       (0x80000000U)
-#define RPC_PHYCNT_CAL         BIT(31)
-#define RPC_PHYCNT_STRTIM_M3V1 (0x6 << 15UL)
-#define RPC_PHYCNT_STRTIM      (0x7 << 15UL)
-
-static void rpc_enable(void)
-{
-       /* Enable clock supply to RPC. */
-       mstpcr_write(CPG_SMSTPCR9, CPG_MSTPSR9, MSTPSR9_RPC_BIT);
-}
-
-static void rpc_setup(void)
-{
-       uint32_t product, cut, reg, phy_strtim;
-
-       if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT)
-               mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT);
-
-       product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
-       cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
-
-       if ((product ==  PRR_PRODUCT_M3) && (cut < PRR_PRODUCT_30))
-               phy_strtim = RPC_PHYCNT_STRTIM_M3V1;
-       else
-               phy_strtim = RPC_PHYCNT_STRTIM;
-
-       reg = mmio_read_32(RPC_PHYCNT);
-       reg &= ~RPC_PHYCNT_STRTIM;
-       reg |= phy_strtim;
-       mmio_write_32(RPC_PHYCNT, reg);
-       reg |= RPC_PHYCNT_CAL;
-       mmio_write_32(RPC_PHYCNT, reg);
-}
-
-void rcar_rpc_init(void)
-{
-       rpc_enable();
-       rpc_setup();
-}
diff --git a/drivers/renesas/rcar/rpc/rpc_registers.h b/drivers/renesas/rcar/rpc/rpc_registers.h
deleted file mode 100644 (file)
index 79aea85..0000000
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RPC_REGISTERS_H
-#define RPC_REGISTERS_H
-
-#define RPC_BASE       (0xEE200000U)
-#define RPC_CMNCR      (RPC_BASE + 0x0000U)
-#define RPC_SSLDR      (RPC_BASE + 0x0004U)
-#define RPC_DRCR       (RPC_BASE + 0x000CU)
-#define RPC_DRCMR      (RPC_BASE + 0x0010U)
-#define RPC_DRENR      (RPC_BASE + 0x001CU)
-#define RPC_SMCR       (RPC_BASE + 0x0020U)
-#define RPC_SMCMR      (RPC_BASE + 0x0024U)
-#define RPC_SMENR      (RPC_BASE + 0x0030U)
-#define RPC_CMNSR      (RPC_BASE + 0x0048U)
-#define RPC_DRDMCR     (RPC_BASE + 0x0058U)
-#define RPC_DRDRENR    (RPC_BASE + 0x005CU)
-#define RPC_PHYCNT     (RPC_BASE + 0x007CU)
-#define RPC_PHYINT     (RPC_BASE + 0x0088U)
-
-#endif /* RPC_REGISTERS_H */
index 46035714e78a8d7707e22b2f452cd77cc138a931..b342bdc08a1747c60aea7a38f6b9c8e5a314d35d 100644 (file)
@@ -85,6 +85,7 @@ BL2_SOURCES   +=      ${RCAR_GIC_SOURCES}                             \
                        drivers/renesas/common/io/io_memdrv.c           \
                        drivers/renesas/common/io/io_rcar.c             \
                        drivers/renesas/common/auth/auth_mod.c          \
+                       drivers/renesas/common/rpc/rpc_driver.c         \
                        drivers/renesas/common/dma/dma_driver.c         \
                        drivers/renesas/common/avs/avs_driver.c         \
                        drivers/renesas/common/delay/micro_delay.c      \
index 35dd0ef136bfe84decde9406718e8f461e6502f3..542b36e2287bf8124f0f394d6f634fe1051845db 100644 (file)
@@ -320,7 +320,6 @@ BL2_SOURCES +=      plat/renesas/rcar/aarch64/platform_common.c     \
                        plat/renesas/rcar/bl2_plat_mem_params_desc.c    \
                        plat/renesas/rcar/plat_image_load.c             \
                        plat/renesas/rcar/bl2_cpg_init.c                \
-                       drivers/renesas/rcar/rpc/rpc_driver.c           \
                        drivers/renesas/rcar/board/board.c
 
 BL31_SOURCES   +=      plat/renesas/rcar/plat_topology.c               \