drm/amd/display: Allow clock sharing b/w HDMI and DVI

[why]
HDMI and DVI share the same PHY clock and single link
DVI and HDMI both use 4 lanes, so they should be allowed
to be sharing the same clock source if all other parameters
are satisfied.

[how]
Change a check for general DVI to Dual DVI.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 4ca41d6e3bcf2cb89dce5227eed4cf55add06236..964ba1af7b07979601e477428a15d5d246f30db7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -372,11 +372,11 @@ static bool is_sharable_clk_src(
                return false;
 
        if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
-                       && dc_is_dvi_signal(pipe->stream->signal))
+                       && dc_is_dual_link_signal(pipe->stream->signal))
                return false;
 
        if (dc_is_hdmi_signal(pipe->stream->signal)
-                       && dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
+                       && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
                return false;
 
        if (!resource_are_streams_timing_synchronizable(