MIPS: Add defs & probing of [X]ContextConfig

The CP0_[X]ContextConfig registers are present if CP0_Config3.CTXTC or
CP0_Config3.SM are set, and provide more control over which bits of
CP0_[X]Context are set to the faulting virtual address on a TLB
exception.

KVM/VZ will need to be able to save and restore these registers in the
guest context, so add the relevant definitions and probing of the
ContextConfig feature in the root context first.

[ralf@linux-mips.org: resolve merge conflict.]

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13225/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 5d82b01ef8b50f0c5b66f1b902079684c819ad21..7962b257cc163bbb5eba8718c0afa4532d2f465d 100644 (file)
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -450,4 +450,8 @@
 # define cpu_has_badinstrp     (cpu_data[0].options & MIPS_CPU_BADINSTRP)
 #endif
 
+#ifndef cpu_has_contextconfig
+# define cpu_has_contextconfig (cpu_data[0].options & MIPS_CPU_CTXTC)
+#endif
+
 #endif /* __ASM_CPU_FEATURES_H */

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 0cf90d67c1af7ce1d6cc0757b1b70a32b7f785a9..ddcb2abd44baa5c68238f690b8154a52c6ecbbd2 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -407,6 +407,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_EBASE_WG      MBIT_ULL(43)    /* CPU has EBase.WG */
 #define MIPS_CPU_BADINSTR      MBIT_ULL(44)    /* CPU has BadInstr register */
 #define MIPS_CPU_BADINSTRP     MBIT_ULL(45)    /* CPU has BadInstrP register */
+#define MIPS_CPU_CTXTC         MBIT_ULL(46)    /* CPU has [X]ConfigContext registers */
 
 /*
  * CPU ASE encodings

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index b1f8f8436fd1850e09bc9320c0ecbe1797a89794..08864cbbb27b7003fe4971d6cde3997b93a806c9 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1228,9 +1228,15 @@ do {                                                                     \
 #define read_c0_context()      __read_ulong_c0_register($4, 0)
 #define write_c0_context(val)  __write_ulong_c0_register($4, 0, val)
 
+#define read_c0_contextconfig()                __read_32bit_c0_register($4, 1)
+#define write_c0_contextconfig(val)    __write_32bit_c0_register($4, 1, val)
+
 #define read_c0_userlocal()    __read_ulong_c0_register($4, 2)
 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
 
+#define read_c0_xcontextconfig()       __read_ulong_c0_register($4, 3)
+#define write_c0_xcontextconfig(val)   __write_ulong_c0_register($4, 3, val)
+
 #define read_c0_pagemask()     __read_32bit_c0_register($5, 0)
 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
 

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 8e54d51c14bc471a92ea7d6857bf01deca2e0c15..963ce7ef29df5b7790fbe20e30b0af21fdb81598 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -687,10 +687,12 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 
        if (config3 & MIPS_CONF3_SM) {
                c->ases |= MIPS_ASE_SMARTMIPS;
-               c->options |= MIPS_CPU_RIXI;
+               c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
        }
        if (config3 & MIPS_CONF3_RXI)
                c->options |= MIPS_CPU_RIXI;
+       if (config3 & MIPS_CONF3_CTXTC)
+               c->options |= MIPS_CPU_CTXTC;
        if (config3 & MIPS_CONF3_DSP)
                c->ases |= MIPS_ASE_DSP;
        if (config3 & MIPS_CONF3_DSP2P) {