mips: fix erros on registers macros of pll-ddr-config1-nfrac for QCA956X

See details in chapter 8.6.2 and 8.6.4 (page 140-141) of qca9563 datasheet,

   NFRAC[17:0]

So the mask of [17:5] is 0x1fff not 0x3fff.

Signed-off-by: Rosy Song <rosysong@rosinson.com>
Changes for v2-v3:
   - add more information for this commit

Changes for v4-v5:
   - coding style cleanup

diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index 5d371bb5828d013898a78c45085f036d213b19a3..3506ed1da4911a5964d081f93ba9bc5085a0e039 100644 (file)
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -528,7 +528,7 @@
 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT          0
 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK           0x1f
 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT          5
-#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK           0x3fff
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK           0x1fff
 #define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT             18
 #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK              0x1ff
 
@@ -540,7 +540,7 @@
 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT          0
 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK           0x1f
 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT          5
-#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK           0x3fff
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK           0x1fff
 #define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT             18
 #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK              0x1ff