drm/i915: Expose C8 on VLV/CHV sprite planes

VLV/CHV sprite planes also support the C8 format. Let's expose that.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191031165652.10868-5-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 8726e7f38a0784bc9ab88ff6cd13d58f9b1eb68e..3364eeb0ea07e4cdb99bfffca469cd3b92f6023f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -943,6 +943,9 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
        case DRM_FORMAT_VYUY:
                sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
                break;
+       case DRM_FORMAT_C8:
+               sprctl |= SP_FORMAT_8BPP;
+               break;
        case DRM_FORMAT_RGB565:
                sprctl |= SP_FORMAT_BGR565;
                break;
@@ -2384,6 +2387,7 @@ static const u32 snb_plane_formats[] = {
 };
 
 static const u32 vlv_plane_formats[] = {
+       DRM_FORMAT_C8,
        DRM_FORMAT_RGB565,
        DRM_FORMAT_ABGR8888,
        DRM_FORMAT_ARGB8888,
@@ -2398,6 +2402,7 @@ static const u32 vlv_plane_formats[] = {
 };
 
 static const u32 chv_pipe_b_sprite_formats[] = {
+       DRM_FORMAT_C8,
        DRM_FORMAT_RGB565,
        DRM_FORMAT_XRGB8888,
        DRM_FORMAT_XBGR8888,
@@ -2638,6 +2643,7 @@ static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
        }
 
        switch (format) {
+       case DRM_FORMAT_C8:
        case DRM_FORMAT_RGB565:
        case DRM_FORMAT_ABGR8888:
        case DRM_FORMAT_ARGB8888:

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 78dfdcfc724a651f351613849701efc7928a6181..a607ea520829ecde2cb62f209abccae5fb6061ed 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6629,6 +6629,7 @@ enum {
 #define   SP_GAMMA_ENABLE              (1 << 30)
 #define   SP_PIXFORMAT_MASK            (0xf << 26)
 #define   SP_FORMAT_YUV422             (0x0 << 26)
+#define   SP_FORMAT_8BPP               (0x2 << 26)
 #define   SP_FORMAT_BGR565             (0x5 << 26)
 #define   SP_FORMAT_BGRX8888           (0x6 << 26)
 #define   SP_FORMAT_BGRA8888           (0x7 << 26)