perf/x86/intel: Add EPT-Friendly PEBS for Ice Lake Server

Add support for EPT-Friendly PEBS, a new CPU feature that enlightens PEBS
to translate guest linear address through EPT, and facilitates handling
VM-Exits that occur when accessing PEBS records.  More information can
be found in the December 2021 release of Intel's SDM, Volume 3,
18.9.5 "EPT-Friendly PEBS". This new hardware facility makes sure the
guest PEBS records will not be lost, which is available on Intel Ice Lake
Server platforms (and later).

KVM will check this field through perf_get_x86_pmu_capability() instead
of hard coding the CPU models in the KVM code. If it is supported, the
guest PEBS capability will be exposed to the guest. Guest PEBS can be
enabled when and only when "EPT-Friendly PEBS" is supported and
EPT is enabled.

Cc: linux-perf-users@vger.kernel.org
Signed-off-by: Like Xu <likexu@tencent.com>
Message-Id: <20220411101946.20262-2-likexu@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 30788894124f0e265ddda6fd4b76b8ea1c82b3fd..a9ebd096dfb443f27eb11067de6680a6a4b447b8 100644 (file)
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -3002,5 +3002,6 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
        cap->bit_width_fixed    = x86_pmu.cntval_bits;
        cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
        cap->events_mask_len    = x86_pmu.events_mask_len;
+       cap->pebs_ept           = x86_pmu.pebs_ept;
 }
 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 45024abd929f0aba75664f24be3898edb6325ed9..96bb0ac7462bd0a2b892d3107e3ca0ca546263f9 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6138,6 +6138,7 @@ __init int intel_pmu_init(void)
 
        case INTEL_FAM6_ICELAKE_X:
        case INTEL_FAM6_ICELAKE_D:
+               x86_pmu.pebs_ept = 1;
                pmem = true;
                fallthrough;
        case INTEL_FAM6_ICELAKE_L:

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 21a5482bcf8458c29a62fb6670a4eadaa4aaa683..4910dc41433bc273c050766885027af0a1368756 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -818,7 +818,8 @@ struct x86_pmu {
                        pebs_prec_dist          :1,
                        pebs_no_tlb             :1,
                        pebs_no_isolation       :1,
-                       pebs_block              :1;
+                       pebs_block              :1,
+                       pebs_ept                :1;
        int             pebs_record_size;
        int             pebs_buffer_size;
        int             max_pebs_events;

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 409725e86f42c4453306c6d446ff04207e1b594d..f95ab4da6fea85407daf45fde8937f19a13fb6e0 100644 (file)
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -206,6 +206,7 @@ struct x86_pmu_capability {
        int             bit_width_fixed;
        unsigned int    events_mask;
        int             events_mask_len;
+       unsigned int    pebs_ept        :1;
 };
 
 /*