drm/i915/dg1: Increase mmio size to 4MB

On DGFX the register range has been extended to go up to 8MB. However we
only actually use up to address 280000h, so let's increase it to 4MB.

v2 (Lucas):  add bspec reference and reword commit message to explain
   the 4 vs 8 MB used (requested by Matt Roper)

Bspec: 53616

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michael J. Ruhl <michael.j.ruhl@intel.com>
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201007002210.3678024-4-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 263ffcb832b79faba564e1e8af80f19d6db2b73b..54e201fdeba4b8c595fd38e3cd98dc2d8658232c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1701,11 +1701,15 @@ static int uncore_mmio_setup(struct intel_uncore *uncore)
         * clobbering the GTT which we want ioremap_wc instead. Fortunately,
         * the register BAR remains the same size for all the earlier
         * generations up to Ironlake.
+        * For dgfx chips register range is expanded to 4MB.
         */
        if (INTEL_GEN(i915) < 5)
                mmio_size = 512 * 1024;
+       else if (IS_DGFX(i915))
+               mmio_size = 4 * 1024 * 1024;
        else
                mmio_size = 2 * 1024 * 1024;
+
        uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
        if (uncore->regs == NULL) {
                drm_err(&i915->drm, "failed to map registers\n");