watchdog: rza_wdt: Support longer timeouts

The RZ/A2 watchdog timer extends the clock source options in order to
allow for longer timeouts.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>

diff --git a/drivers/watchdog/rza_wdt.c b/drivers/watchdog/rza_wdt.c
index c63ef03e24f6bc43764854e6441566c48a821648..781bb572e6af3de3f2d4caa3120df8d24a1090f1 100644 (file)
--- a/drivers/watchdog/rza_wdt.c
+++ b/drivers/watchdog/rza_wdt.c
@@ -11,6 +11,7 @@
 #include <linux/delay.h>
 #include <linux/module.h>
 #include <linux/of_address.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/watchdog.h>
 
@@ -31,12 +32,45 @@
 #define WRCSR_RSTE             BIT(6)
 #define WRCSR_CLEAR_WOVF       0xA500  /* special value */
 
+/* The maximum CKS register setting value to get the longest timeout */
+#define CKS_3BIT               0x7
+#define CKS_4BIT               0xF
+
+#define DIVIDER_3BIT           16384   /* Clock divider when CKS = 0x7 */
+#define DIVIDER_4BIT           4194304 /* Clock divider when CKS = 0xF */
+
 struct rza_wdt {
        struct watchdog_device wdev;
        void __iomem *base;
        struct clk *clk;
+       u8 count;
+       u8 cks;
 };
 
+static void rza_wdt_calc_timeout(struct rza_wdt *priv, int timeout)
+{
+       unsigned long rate = clk_get_rate(priv->clk);
+       unsigned int ticks;
+
+       if (priv->cks == CKS_4BIT) {
+               ticks = DIV_ROUND_UP(timeout * rate, DIVIDER_4BIT);
+
+               /*
+                * Since max_timeout was set in probe, we know that the timeout
+                * value passed will never calculate to a tick value greater
+                * than 256.
+                */
+               priv->count = 256 - ticks;
+
+       } else {
+               /* Start timer with longest timeout */
+               priv->count = 0;
+       }
+
+       pr_debug("%s: timeout set to %u (WTCNT=%d)\n", __func__,
+                timeout, priv->count);
+}
+
 static int rza_wdt_start(struct watchdog_device *wdev)
 {
        struct rza_wdt *priv = watchdog_get_drvdata(wdev);
@@ -48,13 +82,12 @@ static int rza_wdt_start(struct watchdog_device *wdev)
        readb(priv->base + WRCSR);
        writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);
 
-       /*
-        * Start timer with slowest clock source and reset option enabled.
-        */
+       rza_wdt_calc_timeout(priv, wdev->timeout);
+
        writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR);
-       writew(WTCNT_MAGIC | 0, priv->base + WTCNT);
-       writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME | WTSCR_CKS(7),
-              priv->base + WTCSR);
+       writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT);
+       writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME |
+              WTSCR_CKS(priv->cks), priv->base + WTCSR);
 
        return 0;
 }
@@ -72,8 +105,17 @@ static int rza_wdt_ping(struct watchdog_device *wdev)
 {
        struct rza_wdt *priv = watchdog_get_drvdata(wdev);
 
-       writew(WTCNT_MAGIC | 0, priv->base + WTCNT);
+       writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT);
 
+       pr_debug("%s: timeout = %u\n", __func__, wdev->timeout);
+
+       return 0;
+}
+
+static int rza_set_timeout(struct watchdog_device *wdev, unsigned int timeout)
+{
+       wdev->timeout = timeout;
+       rza_wdt_start(wdev);
        return 0;
 }
 
@@ -118,6 +160,7 @@ static const struct watchdog_ops rza_wdt_ops = {
        .start = rza_wdt_start,
        .stop = rza_wdt_stop,
        .ping = rza_wdt_ping,
+       .set_timeout = rza_set_timeout,
        .restart = rza_wdt_restart,
 };
 
@@ -147,20 +190,28 @@ static int rza_wdt_probe(struct platform_device *pdev)
                return -ENOENT;
        }
 
-       /* Assume slowest clock rate possible (CKS=7) */
-       rate /= 16384;
-
        priv->wdev.info = &rza_wdt_ident,
        priv->wdev.ops = &rza_wdt_ops,
        priv->wdev.parent = &pdev->dev;
 
-       /*
-        * Since the max possible timeout of our 8-bit count register is less
-        * than a second, we must use max_hw_heartbeat_ms.
-        */
-       priv->wdev.max_hw_heartbeat_ms = (1000 * U8_MAX) / rate;
-       dev_dbg(&pdev->dev, "max hw timeout of %dms\n",
-                priv->wdev.max_hw_heartbeat_ms);
+       priv->cks = (u8)(uintptr_t)of_device_get_match_data(&pdev->dev);
+       if (priv->cks == CKS_4BIT) {
+               /* Assume slowest clock rate possible (CKS=0xF) */
+               priv->wdev.max_timeout = (DIVIDER_4BIT * U8_MAX) / rate;
+
+       } else if (priv->cks == CKS_3BIT) {
+               /* Assume slowest clock rate possible (CKS=7) */
+               rate /= DIVIDER_3BIT;
+
+               /*
+                * Since the max possible timeout of our 8-bit count
+                * register is less than a second, we must use
+                * max_hw_heartbeat_ms.
+                */
+               priv->wdev.max_hw_heartbeat_ms = (1000 * U8_MAX) / rate;
+               dev_dbg(&pdev->dev, "max hw timeout of %dms\n",
+                        priv->wdev.max_hw_heartbeat_ms);
+       }
 
        priv->wdev.min_timeout = 1;
        priv->wdev.timeout = DEFAULT_TIMEOUT;
@@ -176,7 +227,8 @@ static int rza_wdt_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id rza_wdt_of_match[] = {
-       { .compatible = "renesas,rza-wdt", },
+       { .compatible = "renesas,r7s9210-wdt",  .data = (void *)CKS_4BIT, },
+       { .compatible = "renesas,rza-wdt",      .data = (void *)CKS_3BIT, },
        { /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, rza_wdt_of_match);