drm/i915/gt: fix platform prefix

gen8_clear_engine_error_register() is actually not used by
GRAPHICS_VER >= 8, since for those we are using another register that is
not engine-dependent. Fix the platform prefix, to make clear we are not
using any GEN6_RING_FAULT_REG_* one GRAPHICS_VER >= 8.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210720232014.3302645-2-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index acfdd53b26781dc1919c4295b7748a5c990fb37a..46441607d18b64d7ce713634a6f362bcff23c1ab 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -205,7 +205,7 @@ static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
        intel_uncore_rmw(uncore, reg, 0, 0);
 }
 
-static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
+static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
 {
        GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
        GEN6_RING_FAULT_REG_POSTING_READ(engine);
@@ -251,7 +251,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
                enum intel_engine_id id;
 
                for_each_engine_masked(engine, gt, engine_mask, id)
-                       gen8_clear_engine_error_register(engine);
+                       gen6_clear_engine_error_register(engine);
        }
 }