drm/amd/powerplay: fix spelling typo in function name

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
index 953e0c9ad7cdde7bd6762c83eac057d391f8dc6d..49733c7817179ccc811257750885141e84ce04b2 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
@@ -470,7 +470,7 @@ uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr)
  * SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ.
  * voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE
  */
-bool atomctrl_is_voltage_controled_by_gpio_v3(
+bool atomctrl_is_voltage_controlled_by_gpio_v3(
                struct pp_hwmgr *hwmgr,
                uint8_t voltage_type,
                uint8_t voltage_mode)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
index e9fe2e84006b164693f20846bc8d68b51f72f0c0..8d4188ad941afa0e67a0ea2f9c38216d29d3dbd7 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
@@ -291,7 +291,7 @@ extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
 extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
 extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
 extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
-extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
+extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
 extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
 extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
                uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index f1f1e4b390ca00f6e8100b11074dbf9ae39e224b..03075c6ac512714740d33e2c1474cf2a4bda3ea7 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -1392,13 +1392,13 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
        }
 
        data->fast_watermark_threshold = 100;
-       if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
+       if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
                        VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
                data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
 
        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_ControlVDDGFX)) {
-               if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
+               if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
                        VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
                        data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
                }
@@ -1406,10 +1406,10 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 
        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_EnableMVDDControl)) {
-               if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
+               if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
                                VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
                        data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
-               else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
+               else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
                                VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
                        data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
        }
@@ -1421,10 +1421,10 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 
        if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                        PHM_PlatformCaps_ControlVDDCI)) {
-               if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
+               if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
                                VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
                        data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
-               else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
+               else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
                                VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
                        data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
        }

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
index 8712f093d6d90afcc3b64274c71424d55ec2af61..9f612dd395ac04f1b6e229355113e947ad529dd3 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
@@ -398,11 +398,6 @@ static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
        return 0;
 }
 
-static int fiji_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
-{
-       return 0;
-}
-
 static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
 {
        struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
@@ -472,12 +467,6 @@ static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
                                        "Attempt to populate GnbLPML Failed!",
                                        return -EINVAL);
 
-               /* DW19 */
-               if (fiji_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
-                       PP_ASSERT_WITH_CODE(false,
-                                       "Attempt to populate GnbLPML Min and Max Vid Failed!",
-                                       return -EINVAL);
-
                /* DW20 */
                if (fiji_populate_bapm_vddc_base_leakage_sidd(hwmgr))
                        PP_ASSERT_WITH_CODE(false,

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
index 51adf04ab4b387dafadce6d98325f330841cd7cb..1ed3214a965f20b6fcaa0528514c7b08f9f36eda 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
@@ -193,11 +193,6 @@ static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
        return 0;
 }
 
-static int iceland_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
-{
-       return 0;
-}
-
 static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
 {
        struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
@@ -317,12 +312,6 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
                                        "Attempt to populate GnbLPML Failed!",
                                        return -EINVAL);
 
-               /* DW17 */
-               if (iceland_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
-                       PP_ASSERT_WITH_CODE(false,
-                                       "Attempt to populate GnbLPML Min and Max Vid Failed!",
-                                       return -EINVAL);
-
                /* DW18 */
                if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr))
                        PP_ASSERT_WITH_CODE(false,
@@ -339,7 +328,7 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
        return 0;
 }
 
-static int iceland_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
+static int iceland_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
        struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
        uint32_t clock, uint32_t *vol)
 {
@@ -749,7 +738,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
        result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
 
        /* populate graphics levels*/
-       result = iceland_get_dependecy_volt_by_clk(hwmgr,
+       result = iceland_get_dependency_volt_by_clk(hwmgr,
                hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
                &graphic_level->MinVddc);
        PP_ASSERT_WITH_CODE((0 == result),
@@ -1104,7 +1093,7 @@ static int iceland_populate_single_memory_level(
        uint32_t mclk_strobe_mode_threshold = 40000;
 
        if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
-               result = iceland_get_dependecy_volt_by_clk(hwmgr,
+               result = iceland_get_dependency_volt_by_clk(hwmgr,
                        hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
                PP_ASSERT_WITH_CODE((0 == result),
                        "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
@@ -1113,7 +1102,7 @@ static int iceland_populate_single_memory_level(
        if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) {
                memory_level->MinVddci = memory_level->MinVddc;
        } else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
-               result = iceland_get_dependecy_volt_by_clk(hwmgr,
+               result = iceland_get_dependency_volt_by_clk(hwmgr,
                                hwmgr->dyn_state.vddci_dependency_on_mclk,
                                memory_clock,
                                &memory_level->MinVddci);
@@ -1776,7 +1765,7 @@ static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
        CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);
        CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);
 
-       dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bamp_temp_gradient);
+       dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
        def1 = defaults->bapmti_r;
        def2 = defaults->bapmti_rc;
 

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h
index 8eae01b37c40112e21b315f159ee93cb9ad5823e..802472530d34689c4711479b4e1208ab41434cff 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h
@@ -39,7 +39,7 @@ struct iceland_pt_defaults {
        uint8_t   tdc_waterfall_ctl;
        uint8_t   dte_ambient_temp_base;
        uint32_t  display_cac;
-       uint32_t  bamp_temp_gradient;
+       uint32_t  bapm_temp_gradient;
        uint16_t  bapmti_r[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS];
        uint16_t  bapmti_rc[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS];
 };

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
index 99a00bd39256586b501414fcca02b13d198c8c1e..2d444bb4802a2a2c96089cd16046fee2172ec2b0 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
@@ -288,11 +288,6 @@ static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
        return 0;
 }
 
-static int polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
-{
-       return 0;
-}
-
 static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
 {
        struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
@@ -358,11 +353,6 @@ static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
                                        "Attempt to populate GnbLPML Failed!",
                                        return -EINVAL);
 
-               if (polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
-                       PP_ASSERT_WITH_CODE(false,
-                                       "Attempt to populate GnbLPML Min and Max Vid Failed!",
-                                       return -EINVAL);
-
                if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
                        PP_ASSERT_WITH_CODE(false,
                                        "Attempt to populate BapmVddCBaseLeakage Hi and Lo "

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
index 65d3a4893958297dd0fa30d8f446187c73c40091..a628eec5e6dac259ce9dd3f2f8fc537089fb8c0e 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
@@ -97,7 +97,7 @@ static const uint8_t tonga_clock_stretch_amount_conversion[2][6] = {
  */
 
 
-static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
+static int tonga_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
        phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
        uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
 {
@@ -539,7 +539,7 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
        result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
 
        /* populate graphics levels*/
-       result = tonga_get_dependecy_volt_by_clk(hwmgr,
+       result = tonga_get_dependency_volt_by_clk(hwmgr,
                pptable_info->vdd_dep_on_sclk, engine_clock,
                &graphic_level->MinVoltage, &mvdd);
        PP_ASSERT_WITH_CODE((!result),
@@ -895,7 +895,7 @@ static int tonga_populate_single_memory_level(
        uint32_t mclk_strobe_mode_threshold = 40000;
 
        if (NULL != pptable_info->vdd_dep_on_mclk) {
-               result = tonga_get_dependecy_volt_by_clk(hwmgr,
+               result = tonga_get_dependency_volt_by_clk(hwmgr,
                                pptable_info->vdd_dep_on_mclk,
                                memory_clock,
                                &memory_level->MinVoltage, &mvdd);
@@ -1838,7 +1838,7 @@ static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
        dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
 
        dpm_table->BAPM_TEMP_GRADIENT =
-                               PP_HOST_TO_SMC_UL(defaults->bamp_temp_gradient);
+                               PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
        pdef1 = defaults->bapmti_r;
        pdef2 = defaults->bapmti_rc;
 
@@ -1958,11 +1958,6 @@ static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
        return 0;
 }
 
-static int tonga_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
-{
-       return 0;
-}
-
 static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
 {
        struct tonga_smumgr *smu_data =
@@ -2035,13 +2030,6 @@ static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
                                "Attempt to populate GnbLPML Failed !",
                                return -EINVAL);
 
-               /* DW19 */
-               if (tonga_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
-                       PP_ASSERT_WITH_CODE(false,
-                               "Attempt to populate GnbLPML "
-                               "Min and Max Vid Failed !",
-                               return -EINVAL);
-
                /* DW20 */
                if (tonga_populate_bapm_vddc_base_leakage_sidd(hwmgr))
                        PP_ASSERT_WITH_CODE(

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h
index 962860f13f24d49e8677baf11dd0dfb146990d95..9d6a78a65976cf2a0af18afe2ec71f72749a602c 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.h
@@ -40,7 +40,7 @@ struct tonga_pt_defaults {
        uint8_t   tdc_waterfall_ctl;
        uint8_t   dte_ambient_temp_base;
        uint32_t  display_cac;
-       uint32_t  bamp_temp_gradient;
+       uint32_t  bapm_temp_gradient;
        uint16_t  bapmti_r[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
        uint16_t  bapmti_rc[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
 };