fix(intel): fix pinmux handoff bug on Agilex

Incorrect number of FPGA pinmux registers was copied from handoff data.
This caused pinmux_emac0_usefpga register to always be zero meaning
"EMAC0 uses HPS IO Pins" even if handoff data for this register was one
meaning "EMAC0 uses the FPGA Inteface".

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ia0bd832c61d25f66ef13f39fe28b054cb96af9a1

diff --git a/plat/intel/soc/agilex/soc/agilex_pinmux.c b/plat/intel/soc/agilex/soc/agilex_pinmux.c
index 0b908cfa3f5bda4fd8e23830bad4bae62e01b772..2367c21c7f652c01ee5e7c43cb1314d2ec264a02 100644 (file)
--- a/plat/intel/soc/agilex/soc/agilex_pinmux.c
+++ b/plat/intel/soc/agilex/soc/agilex_pinmux.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -208,7 +208,7 @@ void config_pinmux(handoff *hoff_ptr)
                        hoff_ptr->pinmux_io_array[i+1]);
        }
 
-       for (i = 0; i < 42; i += 2) {
+       for (i = 0; i < 40; i += 2) {
                mmio_write_32(AGX_PINMUX_PINMUX_EMAC0_USEFPGA +
                        hoff_ptr->pinmux_fpga_array[i],
                        hoff_ptr->pinmux_fpga_array[i+1]);