Kinibi now has 60MB (instead of 64MB).
Increase XLAT tables for BL31
Change-Id: I6843d26198a7d8bdb812e394e4482b1c35afa4c0
Signed-off-by: vallau01 <valentin.laurent@trustonic.com>
Signed-off-by: Lukas Hanel <lukas.hanel@trustonic.com>
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <drivers/console.h>
#include <drivers/generic_delay_timer.h>
#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <hi3660.h>
void bl31_plat_arch_setup(void)
{
+#if SPMC_AT_EL3
+ mmap_add_region(DDR2_SEC_BASE, DDR2_SEC_BASE, DDR2_SEC_SIZE,
+ MT_MEMORY | MT_RW | MT_SECURE);
+#endif
+
hikey960_init_mmu_el3(BL31_BASE,
BL31_LIMIT - BL31_BASE,
BL_CODE_BASE,
}
}
+#if SPMC_AT_EL3
+/*
+ * On the hikey960 platform when using the EL3 SPMC implementation allocate the
+ * datastore for tracking shared memory descriptors in the RAM2 DRAM section
+ * to ensure sufficient storage can be allocated.
+ * Provide an implementation of the accessor method to allow the datastore
+ * details to be retrieved by the SPMC.
+ * The SPMC will take care of initializing the memory region.
+ */
+
+#define SPMC_SHARED_MEMORY_OBJ_SIZE (512 * 1024)
+
+__section("ram2_region") uint8_t plat_spmc_shmem_datastore[SPMC_SHARED_MEMORY_OBJ_SIZE];
+
+int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size)
+{
+ *datastore = plat_spmc_shmem_datastore;
+ *size = SPMC_SHARED_MEMORY_OBJ_SIZE;
+ return 0;
+}
+#endif
+
void bl31_platform_setup(void)
{
/* Initialize the GIC driver, cpu and distributor interfaces */
* DDR for TEE (80MB from 0x3E00000-0x43000FFF) is divided into several
* regions:
* - SPMC manifest (4KB at the top) used by SPMC_AT_EL3 and the TEE
- * - Secure DDR (default is the top 64MB) used by OP-TEE
+ * - Datastore for SPMC_AT_EL3 (4MB at the top) used by BL31
+ * - Secure DDR (default is the top 60MB) used by OP-TEE
* - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
* - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
* - Non-secure DDR (8MB) reserved for OP-TEE's future use
*/
-#define DDR_SEC_SIZE 0x04000000 /* reserve 64MB secure memory */
+#define DDR_SEC_SIZE 0x03C00000 /* reserve 60MB secure memory */
#define DDR_SEC_BASE 0x3F000000
+#define DDR2_SEC_SIZE 0x00400000 /* SPMC_AT_EL3: 4MB for BL31 RAM2 */
+#define DDR2_SEC_BASE 0x42C00000
#define DDR_SEC_CONFIG_SIZE 0x00001000 /* SPMC_AT_EL3: SPMC manifest */
#define DDR_SEC_CONFIG_BASE 0x43000000
--- /dev/null
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLAT_LD_S
+#define PLAT_LD_S
+
+#include <lib/xlat_tables/xlat_tables_defs.h>
+
+MEMORY {
+ RAM2 (rw): ORIGIN = DDR2_SEC_BASE, LENGTH = DDR2_SEC_SIZE
+}
+
+SECTIONS
+{
+ ram2_region (NOLOAD) : {
+ *(ram2_region)
+ }>RAM2
+}
+
+#endif /* PLAT_LD_S */
#define MAX_XLAT_TABLES 3
#endif
-#if defined(IMAGE_BL2) || defined(IMAGE_BL31)
+#if defined(IMAGE_BL2)
#define MAX_XLAT_TABLES 5
#endif
+#if defined(IMAGE_BL31)
+#if defined(SPMC_AT_EL3)
+#define MAX_XLAT_TABLES 17
+#else
+#define MAX_XLAT_TABLES 5
+#endif
+#endif
+
#define MAX_MMAP_REGIONS 16
/*
# SPM dispatcher
ifeq (${SPD},spmd)
+ifeq (${SPMC_AT_EL3},1)
+# Add support for platform supplied linker script for BL31 build
+$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
+endif
+
ifeq ($(PLAT_SP_MANIFEST_DTS),)
$(error "Error: A SP manifest is required for the SPMC.")
endif