controller register space
- Serial Ports:
- CONFIG_PL011_CLOCK
+ CFG_PL011_CLOCK
If you have Amba PrimeCell PL011 UARTs, set this variable to
the clock speed of the UARTs.
/* set clock */
clk_disable(clk);
- clk_set_rate(clk, CONFIG_PL011_CLOCK);
+ clk_set_rate(clk, CFG_PL011_CLOCK);
clk_enable(clk);
}
#endif
static const struct pl01x_serial_plat serial_plat = {
.base = UART0_BASE,
.type = TYPE_PL011,
- .clock = CONFIG_PL011_CLOCK,
+ .clock = CFG_PL011_CLOCK,
};
U_BOOT_DRVINFO(total_compute_serials) = {
static const struct pl01x_serial_plat serial_plat = {
.base = V2M_UART0,
.type = TYPE_PL011,
- .clock = CONFIG_PL011_CLOCK,
+ .clock = CFG_PL011_CLOCK,
};
U_BOOT_DRVINFO(vexpress_serials) = {
#if defined(CONFIG_PL011_SERIAL)
pl01x_type = TYPE_PL011;
- clock = CONFIG_PL011_CLOCK;
+ clock = CFG_PL011_CLOCK;
#endif
base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
{}
};
-#ifndef CONFIG_PL011_CLOCK
-#define CONFIG_PL011_CLOCK 0
+#ifndef CFG_PL011_CLOCK
+#define CFG_PL011_CLOCK 0
#endif
int pl01x_serial_of_to_plat(struct udevice *dev)
return -EINVAL;
plat->base = addr;
- plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
+ plat->clock = dev_read_u32_default(dev, "clock", CFG_PL011_CLOCK);
ret = clk_get_by_index(dev, 0, &clk);
if (!ret) {
ret = clk_enable(&clk);
#define V2M_BASE 0x80000000
-#define CONFIG_PL011_CLOCK 50000000
+#define CFG_PL011_CLOCK 50000000
/* Physical Memory Map */
#define PHYS_SDRAM_1 (V2M_BASE)
#define CFG_SYS_BOOTMAPSZ (16 << 20)
-#define CONFIG_PL011_CLOCK 150000000
+#define CFG_PL011_CLOCK 150000000
/*
* Miscellaneous configurable options
/* Serial Port */
-#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
+#define CFG_PL011_CLOCK (get_bus_freq(0) / 4)
#define CFG_SYS_SERIAL0 0x21c0000
#define CFG_SYS_SERIAL1 0x21d0000
#define CFG_SYS_SERIAL2 0x21e0000
* DUART Serial Driver.
* Conflicts with AUART driver which can be set by board.
*/
-#define CONFIG_PL011_CLOCK 24000000
+#define CFG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
/* Default baudrate can be overridden by board! */
/*-----------------------------------------------------------------------
* serial console configuration
*/
-#define CONFIG_PL011_CLOCK 50000000
+#define CFG_PL011_CLOCK 50000000
#define CONFIG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \
(void *)PHY_BASEADDR_UART1, \
(void *)PHY_BASEADDR_UART2, \
/* Serial (pl011) */
#define UART_CLK (62500000)
-#define CONFIG_PL011_CLOCK UART_CLK
+#define CFG_PL011_CLOCK UART_CLK
#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
/* Support MTD */
/* PL011 Serial Configuration */
-#define CONFIG_PL011_CLOCK 24000000
+#define CFG_PL011_CLOCK 24000000
/* Generic Interrupt Controller Definitions */
#define GICD_BASE (0x801000000000)
#define UART0_BASE 0x7ff80000
/* PL011 Serial Configuration */
-#define CONFIG_PL011_CLOCK 7372800
+#define CFG_PL011_CLOCK 7372800
/* Miscellaneous configurable options */
/* PL011 Serial Configuration */
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
-#define CONFIG_PL011_CLOCK 7372800
+#define CFG_PL011_CLOCK 7372800
#else
-#define CONFIG_PL011_CLOCK 24000000
+#define CFG_PL011_CLOCK 24000000
#endif
/* Physical Memory Map */
#define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
/* PL011 Serial Configuration */
-#define CONFIG_PL011_CLOCK 24000000
+#define CFG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \
(void *)CFG_SYS_SERIAL1}