]> git.baikalelectronics.ru Git - uboot.git/commitdiff
global: Migrate CONFIG_PL011_CLOCK to CFG
authorTom Rini <trini@konsulko.com>
Sun, 4 Dec 2022 15:13:30 +0000 (10:13 -0500)
committerTom Rini <trini@konsulko.com>
Fri, 23 Dec 2022 15:14:51 +0000 (10:14 -0500)
Perform a simple rename of CONFIG_PL011_CLOCK to CFG_PL011_CLOCK

Signed-off-by: Tom Rini <trini@konsulko.com>
15 files changed:
README
arch/arm/cpu/armv7/s5p4418/cpu.c
board/armltd/total_compute/total_compute.c
board/armltd/vexpress64/vexpress64.c
drivers/serial/serial_pl01x.c
include/configs/corstone1000.h
include/configs/highbank.h
include/configs/lx2160a_common.h
include/configs/mxs.h
include/configs/s5p4418_nanopi2.h
include/configs/synquacer.h
include/configs/thunderx_88xx.h
include/configs/total_compute.h
include/configs/vexpress_aemv8.h
include/configs/vexpress_common.h

diff --git a/README b/README
index 05618352fa9331c57faf2c868a158ff9ab490486..8354cf5699b94d4ff79b3148a713b30c6a8e2132 100644 (file)
--- a/README
+++ b/README
@@ -413,7 +413,7 @@ The following options need to be configured:
                                        controller register space
 
 - Serial Ports:
-               CONFIG_PL011_CLOCK
+               CFG_PL011_CLOCK
 
                If you have Amba PrimeCell PL011 UARTs, set this variable to
                the clock speed of the UARTs.
index 3baa761ec7a9015a742f885b16c71a6587fe15a4..7ba9c0b032369308fd4e860b3abd79bcb31c97d3 100644 (file)
@@ -64,7 +64,7 @@ static void serial_device_init(void)
 
        /* set clock   */
        clk_disable(clk);
-       clk_set_rate(clk, CONFIG_PL011_CLOCK);
+       clk_set_rate(clk, CFG_PL011_CLOCK);
        clk_enable(clk);
 }
 #endif
index b7772f79a31a86a27096d209de81d64dadc49b91..53941b5f5f2887cffc52cb09ed55f8d3a38351a8 100644 (file)
@@ -13,7 +13,7 @@
 static const struct pl01x_serial_plat serial_plat = {
        .base = UART0_BASE,
        .type = TYPE_PL011,
-       .clock = CONFIG_PL011_CLOCK,
+       .clock = CFG_PL011_CLOCK,
 };
 
 U_BOOT_DRVINFO(total_compute_serials) = {
index 4ca544f1017da13bc449c6e758f84a495b279fe6..99fb67ecedc2bd03033e2876e35ecd9b7f39d5fe 100644 (file)
@@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static const struct pl01x_serial_plat serial_plat = {
        .base = V2M_UART0,
        .type = TYPE_PL011,
-       .clock = CONFIG_PL011_CLOCK,
+       .clock = CFG_PL011_CLOCK,
 };
 
 U_BOOT_DRVINFO(vexpress_serials) = {
index d3c3d3e2d1882eb375513af58fc5533bd91a2f27..dd2881931dfddb0c913d527c81db3d8783c9f47c 100644 (file)
@@ -193,7 +193,7 @@ static void pl01x_serial_init_baud(int baudrate)
 
 #if defined(CONFIG_PL011_SERIAL)
        pl01x_type = TYPE_PL011;
-       clock = CONFIG_PL011_CLOCK;
+       clock = CFG_PL011_CLOCK;
 #endif
        base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
 
@@ -343,8 +343,8 @@ static const struct udevice_id pl01x_serial_id[] ={
        {}
 };
 
-#ifndef CONFIG_PL011_CLOCK
-#define CONFIG_PL011_CLOCK 0
+#ifndef CFG_PL011_CLOCK
+#define CFG_PL011_CLOCK 0
 #endif
 
 int pl01x_serial_of_to_plat(struct udevice *dev)
@@ -359,7 +359,7 @@ int pl01x_serial_of_to_plat(struct udevice *dev)
                return -EINVAL;
 
        plat->base = addr;
-       plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
+       plat->clock = dev_read_u32_default(dev, "clock", CFG_PL011_CLOCK);
        ret = clk_get_by_index(dev, 0, &clk);
        if (!ret) {
                ret = clk_enable(&clk);
index 8aec52d508e26a2eb0937dcdc57cb2c0effaa050..3347c11792d5737c4b5c5e9076ce4a7caed29190 100644 (file)
@@ -16,7 +16,7 @@
 
 #define V2M_BASE               0x80000000
 
-#define CONFIG_PL011_CLOCK     50000000
+#define CFG_PL011_CLOCK        50000000
 
 /* Physical Memory Map */
 #define PHYS_SDRAM_1           (V2M_BASE)
index 76e6054b0cc1efdc4abc25d1364c4eecd184565b..97bb439f7357bccc763132f166071a9831daad06 100644 (file)
@@ -8,7 +8,7 @@
 
 #define CFG_SYS_BOOTMAPSZ              (16 << 20)
 
-#define CONFIG_PL011_CLOCK             150000000
+#define CFG_PL011_CLOCK                150000000
 
 /*
  * Miscellaneous configurable options
index c1a98fd3e4cb511dabef8b4df1249c090e571d50..f8a20ea16f9d3a4624f00fd0c30874f349f92b8c 100644 (file)
@@ -39,7 +39,7 @@
 
 
 /* Serial Port */
-#define CONFIG_PL011_CLOCK             (get_bus_freq(0) / 4)
+#define CFG_PL011_CLOCK                (get_bus_freq(0) / 4)
 #define CFG_SYS_SERIAL0                0x21c0000
 #define CFG_SYS_SERIAL1                0x21d0000
 #define CFG_SYS_SERIAL2                0x21e0000
index 32e0e06617e5b27ecdf763414c6a080d4dc35814..90cb1a5e4a0092d5f473a6ea5d7a3103a42cbfc7 100644 (file)
@@ -77,7 +77,7 @@
  * DUART Serial Driver.
  * Conflicts with AUART driver which can be set by board.
  */
-#define CONFIG_PL011_CLOCK             24000000
+#define CFG_PL011_CLOCK                24000000
 #define CONFIG_PL01x_PORTS             { (void *)MXS_UARTDBG_BASE }
 /* Default baudrate can be overridden by board! */
 
index bfe559f6e2cd4dba194c193cb4147bb75356d406..0e7d01925eefdc1eb4f3f4f9ada43aff7e9012f0 100644 (file)
@@ -76,7 +76,7 @@
 /*-----------------------------------------------------------------------
  * serial console configuration
  */
-#define CONFIG_PL011_CLOCK             50000000
+#define CFG_PL011_CLOCK                50000000
 #define CONFIG_PL01x_PORTS             {(void *)PHY_BASEADDR_UART0, \
                                         (void *)PHY_BASEADDR_UART1, \
                                         (void *)PHY_BASEADDR_UART2, \
index e65d6238163f8358d9131134eb2475612e8b9fad..350cc69c28dc475514d02ff57eef7c5e9850fed2 100644 (file)
@@ -31,7 +31,7 @@
 
 /* Serial (pl011)       */
 #define UART_CLK                       (62500000)
-#define CONFIG_PL011_CLOCK             UART_CLK
+#define CFG_PL011_CLOCK                UART_CLK
 #define CONFIG_PL01x_PORTS             {(void *)(0x2a400000)}
 
 /* Support MTD */
index 8ba40546b2c0496c7900e4f50c7ca0cea0fb2cf4..2bca86bed93923ff36a2dc8c3acab8f7e6137aa7 100644 (file)
@@ -17,7 +17,7 @@
 
 /* PL011 Serial Configuration */
 
-#define CONFIG_PL011_CLOCK             24000000
+#define CFG_PL011_CLOCK                24000000
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE                      (0x801000000000)
index e007be8e456404e7b3159732033e434c5c2d832d..436bf622e17428ac7e05c365900d136ceed6fb8d 100644 (file)
@@ -14,7 +14,7 @@
 #define UART0_BASE             0x7ff80000
 
 /* PL011 Serial Configuration */
-#define CONFIG_PL011_CLOCK     7372800
+#define CFG_PL011_CLOCK        7372800
 
 /* Miscellaneous configurable options */
 
index 87b8c5d57ee7bd40a6d1a97077c0bfdbd4698b53..43f7e454d812f24778e3e9a845fd7e6537382ac1 100644 (file)
@@ -86,9 +86,9 @@
 
 /* PL011 Serial Configuration */
 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
-#define CONFIG_PL011_CLOCK             7372800
+#define CFG_PL011_CLOCK                7372800
 #else
-#define CONFIG_PL011_CLOCK             24000000
+#define CFG_PL011_CLOCK                24000000
 #endif
 
 /* Physical Memory Map */
index 705a941e3603b32ce652b45f07d9fd66517fb7be..3fc70de577138503e79a4ee52e5477f369745e7b 100644 (file)
 #define CFG_SYS_TIMER_COUNTER  (V2M_TIMER01 + 0x4)
 
 /* PL011 Serial Configuration */
-#define CONFIG_PL011_CLOCK             24000000
+#define CFG_PL011_CLOCK                24000000
 #define CONFIG_PL01x_PORTS             {(void *)CFG_SYS_SERIAL0, \
                                         (void *)CFG_SYS_SERIAL1}