ARM: dts: r8a7740: Add missing extal2 to CPG node

The Clock Pulse Generator (CPG) device node lacks the extal2 clock.
This may lead to a failure registering the "r" clock, or to a wrong
parent for the "usb24s" clock, depending on MD_CK2 pin configuration and
boot loader CPG_USBCKCR register configuration.

This went unnoticed, as this does not affect the single upstream board
configuration, which relies on the first clock input only.

Fixes: e57c9e67aa261b7b ("ARM: shmobile: r8a7740: add SoC clocks to DTS")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20200508095918.6061-1-geert+renesas@glider.be

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index ebc1ff64f530d42c21b818fec618ccdd8b4dc6d6..90feb2cf99601af9d33c514476387234e200b64d 100644 (file)
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -479,7 +479,7 @@
                cpg_clocks: cpg_clocks@e6150000 {
                        compatible = "renesas,r8a7740-cpg-clocks";
                        reg = <0xe6150000 0x10000>;
-                       clocks = <&extal1_clk>, <&extalr_clk>;
+                       clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
                        #clock-cells = <1>;
                        clock-output-names = "system", "pllc0", "pllc1",
                                             "pllc2", "r",