drm/i915/tgl: Add DC3CO required register and bits

Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
   DC3CO enable bit will be used by driver to make DC3CO
   ready for DMC f/w and status bit will be used as DC3CO
   entry status.
2. Transcoder EXITLINE register and its bit fields and mask.
   Transcoder EXITLINE enable bit represents PSR2 idle frame
   reset should be applied at exit line and exitlines mask
   represent required number of scanlines at which DC3CO
   exit happens.

   B.Specs:49196

v1: Use of REG_BIT and using extra space for EXITLINE_ macro
    definition. [Animesh]
v2: Grouping EXITLINE reg bits with EXITLINE(trans) define,
    no functional change. [Ville]

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191007094607.2111-1-anshuman.gupta@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6d67bd238cfe207c8bdc57889d8e6f3e67426684..d252ee7803ccbdb1d2a0b0254c0a58e24d7ebca4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4145,6 +4145,7 @@ enum {
 #define _VTOTAL_A      0x6000c
 #define _VBLANK_A      0x60010
 #define _VSYNC_A       0x60014
+#define _EXITLINE_A    0x60018
 #define _PIPEASRC      0x6001c
 #define _BCLRPAT_A     0x60020
 #define _VSYNCSHIFT_A  0x60028
@@ -4196,6 +4197,11 @@ enum {
 #define PIPESRC(trans)         _MMIO_TRANS2(trans, _PIPEASRC)
 #define PIPE_MULT(trans)       _MMIO_TRANS2(trans, _PIPE_MULT_A)
 
+#define EXITLINE(trans)                _MMIO_TRANS2(trans, _EXITLINE_A)
+#define   EXITLINE_ENABLE      REG_BIT(31)
+#define   EXITLINE_MASK                REG_GENMASK(12, 0)
+#define   EXITLINE_SHIFT       0
+
 /*
  * HSW+ eDP PSR registers
  *
@@ -10291,6 +10297,8 @@ enum skl_power_gate {
 /* GEN9 DC */
 #define DC_STATE_EN                    _MMIO(0x45504)
 #define  DC_STATE_DISABLE              0
+#define  DC_STATE_EN_DC3CO             REG_BIT(30)
+#define  DC_STATE_DC3CO_STATUS         REG_BIT(29)
 #define  DC_STATE_EN_UPTO_DC5          (1 << 0)
 #define  DC_STATE_EN_DC9               (1 << 3)
 #define  DC_STATE_EN_UPTO_DC6          (2 << 0)