config ARCH_P2041
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
config ARCH_P3041
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
config ARCH_P4080
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
config ARCH_P5040
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
config ARCH_T1024
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
config ARCH_T1040
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
config ARCH_T1042
bool
+ select BACKSIDE_L2_CACHE
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
Number of TLB CAM entries for Book-E chips. 64 for E500MC,
16 for other E500 SoCs.
+config BACKSIDE_L2_CACHE
+ bool
+
config SYS_PPC64
bool
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_ENABLE_36BIT_PHYS
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_ENABLE_36BIT_PHYS