clk: versal: Enable only GATE type clocks

Clocks should be enabled or disabled only if they are of GATE type
clocks. If they are not of GATE type clocks, don't touch them.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/1632808827-6109-1-git-send-email-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index 62523d290999e40ec101c31d8b5c0afced556af8..a9dd57b098fe57fa3de28502a6a4f468902aafbc 100644 (file)
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk)
 
        clk_id = priv->clk[clk->id].clk_id;
 
-       return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
+       if (versal_clock_gate(clk_id))
+               return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
+
+       return 0;
 }
 
 static struct clk_ops versal_clk_ops = {