soc: sifive: ccache: determine the cache level from dts

Composable cache could be L2 or L3 cache, use 'cache-level' property of
device node to determine the level.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220913061817.22564-4-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 949b824e89adf681ec00682856ddcdf4e0be1dfe..b361b661ea09adb4a3bbeaa447b2b932ebcff7b7 100644 (file)
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -38,6 +38,7 @@
 static void __iomem *ccache_base;
 static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
 static struct riscv_cacheinfo_ops ccache_cache_ops;
+static int level;
 
 enum {
        DIR_CORR = 0,
@@ -144,7 +145,7 @@ static const struct attribute_group *ccache_get_priv_group(struct cacheinfo
                                                           *this_leaf)
 {
        /* We want to use private group for composable cache only */
-       if (this_leaf->level == 2)
+       if (this_leaf->level == level)
                return &priv_attr_group;
        else
                return NULL;
@@ -215,6 +216,9 @@ static int __init sifive_ccache_init(void)
        if (!ccache_base)
                return -ENOMEM;
 
+       if (of_property_read_u32(np, "cache-level", &level))
+               return -ENOENT;
+
        intr_num = of_property_count_u32_elems(np, "interrupts");
        if (!intr_num) {
                pr_err("CCACHE: no interrupts property\n");