Workaround for Cortex A78 erratum 1941498

Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1.  The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.

SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9

diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index d859cc58163bd5eca52322cfce3499aec569cfea..09aa3017f62b4ed06438ef853df329d83c1b85c0 100644 (file)
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -265,6 +265,9 @@ For Cortex-A78, the following errata build flags are defined :
 -  ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
    CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
 
+-  ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78
+   CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
+
 For Neoverse N1, the following errata build flags are defined :
 
 -  ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1

diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h
index 0d4712b6ae8650ee31d524b027a378c01d639973..caa512046cebb77db180a5933356e7996fff8138 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a78.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,17 +15,18 @@
  * CPU Extended Control register specific definitions.
  ******************************************************************************/
 #define CORTEX_A78_CPUECTLR_EL1                                S3_0_C15_C1_4
+#define CORTEX_A78_CPUECTLR_EL1_BIT_8                  (ULL(1) << 8)
 
 /*******************************************************************************
  * CPU Power Control register specific definitions
  ******************************************************************************/
-#define CORTEX_A78_CPUPWRCTLR_EL1                              S3_0_C15_C2_7
+#define CORTEX_A78_CPUPWRCTLR_EL1                      S3_0_C15_C2_7
 #define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT    U(1)
 
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A78_ACTLR_TAM_BIT                               (ULL(1) << 30)
+#define CORTEX_A78_ACTLR_TAM_BIT                       (ULL(1) << 30)
 
 #define CORTEX_A78_ACTLR2_EL1                          S3_0_C15_C1_1
 #define CORTEX_A78_ACTLR2_EL1_BIT_1                    (ULL(1) << 1)
@@ -33,12 +34,12 @@
 /*******************************************************************************
  * CPU Activity Monitor Unit register specific definitions.
  ******************************************************************************/
-#define CPUAMCNTENCLR0_EL0                                     S3_3_C15_C2_4
-#define CPUAMCNTENSET0_EL0                                     S3_3_C15_C2_5
-#define CPUAMCNTENCLR1_EL0                                     S3_3_C15_C3_0
-#define CPUAMCNTENSET1_EL0                                     S3_3_C15_C3_1
+#define CPUAMCNTENCLR0_EL0                             S3_3_C15_C2_4
+#define CPUAMCNTENSET0_EL0                             S3_3_C15_C2_5
+#define CPUAMCNTENCLR1_EL0                             S3_3_C15_C3_0
+#define CPUAMCNTENSET1_EL0                             S3_3_C15_C3_1
 
-#define CORTEX_A78_AMU_GROUP0_MASK                             U(0xF)
-#define CORTEX_A78_AMU_GROUP1_MASK                             U(0x7)
+#define CORTEX_A78_AMU_GROUP0_MASK                     U(0xF)
+#define CORTEX_A78_AMU_GROUP1_MASK                     U(0x7)
 
 #endif /* CORTEX_A78_H */

diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index 9914f12e8d852b9d13ee451aaf35b92492510db1..ef760ed8ab4aeac44b6e569fb69bebe7a12f6532 100644 (file)
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -31,7 +31,7 @@ func errata_a78_1688305_wa
        bl      check_errata_1688305
        cbz     x0, 1f
        mrs     x1, CORTEX_A78_ACTLR2_EL1
-       orr     x1, x1, CORTEX_A78_ACTLR2_EL1_BIT_1
+       orr     x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1
        msr     CORTEX_A78_ACTLR2_EL1, x1
        isb
 1:
@@ -44,6 +44,34 @@ func check_errata_1688305
        b       cpu_rev_var_ls
 endfunc check_errata_1688305
 
+       /* --------------------------------------------------
+        * Errata Workaround for Cortex A78 Errata #1941498.
+        * This applies to revisions r0p0, r1p0, and r1p1.
+        * x0: variant[4:7] and revision[0:3] of current cpu.
+        * Shall clobber: x0-x17
+        * --------------------------------------------------
+        */
+func errata_a78_1941498_wa
+       /* Compare x0 against revision <= r1p1 */
+       mov     x17, x30
+       bl      check_errata_1941498
+       cbz     x0, 1f
+
+       /* Set bit 8 in ECTLR_EL1 */
+       mrs     x1, CORTEX_A78_CPUECTLR_EL1
+       orr     x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8
+       msr     CORTEX_A78_CPUECTLR_EL1, x1
+       isb
+1:
+       ret     x17
+endfunc errata_a78_1941498_wa
+
+func check_errata_1941498
+       /* Check for revision <= r1p1, might need to be updated later. */
+       mov     x1, #0x11
+       b       cpu_rev_var_ls
+endfunc check_errata_1941498
+
        /* -------------------------------------------------
         * The CPU Ops reset function for Cortex-A78
         * -------------------------------------------------
@@ -58,6 +86,11 @@ func cortex_a78_reset_func
        bl      errata_a78_1688305_wa
 #endif
 
+#if ERRATA_A78_1941498
+       mov     x0, x18
+       bl      errata_a78_1941498_wa
+#endif
+
 #if ENABLE_AMU
        /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
        mrs     x0, actlr_el3
@@ -113,6 +146,7 @@ func cortex_a78_errata_report
         * checking functions of each errata.
         */
        report_errata ERRATA_A78_1688305, cortex_a78, 1688305
+       report_errata ERRATA_A78_1941498, cortex_a78, 1941498
 
        ldp     x8, x30, [sp], #16
        ret

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index da0157f4cb38fc3f5d5d01e81f664fc6f15ab34c..b7dec0b7790d00f1a8ac776574fc18a013ae18d8 100644 (file)
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
 # Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
@@ -294,6 +294,10 @@ ERRATA_A77_1925769 ?=0
 # to revisions r0p0 - r1p0 of the A78 cpu.
 ERRATA_A78_1688305     ?=0
 
+# Flag to apply erratum 1941498 workaround during reset. This erratum applies
+# to revisions r0p0, r1p0, and r1p1 of the A78 cpu.
+ERRATA_A78_1941498     ?=0
+
 # Flag to apply T32 CLREX workaround during reset. This erratum applies
 # only to r0p0 and r1p0 of the Neoverse N1 cpu.
 ERRATA_N1_1043202      ?=0
@@ -575,6 +579,10 @@ $(eval $(call add_define,ERRATA_A77_1925769))
 $(eval $(call assert_boolean,ERRATA_A78_1688305))
 $(eval $(call add_define,ERRATA_A78_1688305))
 
+# Process ERRATA_A78_1941498 flag
+$(eval $(call assert_boolean,ERRATA_A78_1941498))
+$(eval $(call add_define,ERRATA_A78_1941498))
+
 # Process ERRATA_N1_1043202 flag
 $(eval $(call assert_boolean,ERRATA_N1_1043202))
 $(eval $(call add_define,ERRATA_N1_1043202))