clk: renesas: r8a7796: Correct parent clock of INTC-AP

According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of
September 8, 2017, the parent clock of the INTC-AP module clock on R-Car
M3-W is S0D3.

This change has no functional impact.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index e5e7fb212288c3779dfa09ed0f001ee3f77b4408..b3767472088ac0965ef41fe13a6c2c1bde41bf2e 100644 (file)
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -143,7 +143,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
        DEF_MOD("usb-dmac1",             331,   R8A7796_CLK_S3D1),
        DEF_MOD("rwdt",                  402,   R8A7796_CLK_R),
        DEF_MOD("intc-ex",               407,   R8A7796_CLK_CP),
-       DEF_MOD("intc-ap",               408,   R8A7796_CLK_S3D1),
+       DEF_MOD("intc-ap",               408,   R8A7796_CLK_S0D3),
        DEF_MOD("audmac1",               501,   R8A7796_CLK_S0D3),
        DEF_MOD("audmac0",               502,   R8A7796_CLK_S0D3),
        DEF_MOD("drif7",                 508,   R8A7796_CLK_S3D2),