Oleksij Rempel says:
====================
port asix ax88772 to the PHYlib
changes v2:
- add Reviewed-by: Andrew Lunn <andrew@lunn.ch> to some patches
- refactor asix_read_phy_addr() and add error handling for all callers
- refactor asix_mdio_bus_read()
Port ax88772 part of asix driver to the phylib to be able to use more
advanced external PHY attached to this controller.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>