mips: Fix CPC_BASE_ADDR mask to match datasheet

According to 'MIPS32® interAptivTM Multiprocessing
System Programmer’s Guide' CPC_BASE_ADDR takes bits [31:15].

This change is tested ith mt7621 which wasn't working without it.

Signed-off-by: Nikolay Martynov <mar.kolya@gmail.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11766/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index d4635391c36a28240c9fbdd900d26fdf309e0ca9..4ac8e4b69fb5cb71f1bd7ce12545455750340bc1 100644 (file)
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -290,8 +290,8 @@ BUILD_CM_Cx_R_(tcid_8_priority,     0x80)
 #define CM_GCR_GIC_BASE_GICEN_MSK              (_ULCAST_(0x1) << 0)
 
 /* GCR_CPC_BASE register fields */
-#define CM_GCR_CPC_BASE_CPCBASE_SHF            17
-#define CM_GCR_CPC_BASE_CPCBASE_MSK            (_ULCAST_(0x7fff) << 17)
+#define CM_GCR_CPC_BASE_CPCBASE_SHF            15
+#define CM_GCR_CPC_BASE_CPCBASE_MSK            (_ULCAST_(0x1ffff) << 15)
 #define CM_GCR_CPC_BASE_CPCEN_SHF              0
 #define CM_GCR_CPC_BASE_CPCEN_MSK              (_ULCAST_(0x1) << 0)