fix(imx8m): add ddr4 dvfs sw workaround for ERR050712

APB Write data corruption following MRCTRL0.mr_wr=1 while
hardware-driven MR access is occurring

When performing a software driven MR access, the following
sequence must be done automatically before performing other
APB register accesses:

1. Set MRCTRL0.mr_wr=1
2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2)
3. Check for MRSTAT.mr_wr_busy=0 again (for the second time),
   if not, go to step (2).

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ie26e08bcc83d3ed4844ed04a853162308dcdccd0

diff --git a/plat/imx/imx8m/ddr/ddr4_dvfs.c b/plat/imx/imx8m/ddr/ddr4_dvfs.c
index d58a0cc1d9c2ad7ba081b2252ca88fa9c6c5f4cd..94bfaba7e14f1958e8df6d1408a967733634f8ef 100644 (file)
--- a/plat/imx/imx8m/ddr/ddr4_dvfs.c
+++ b/plat/imx/imx8m/ddr/ddr4_dvfs.c
@@ -18,9 +18,23 @@ void ddr4_mr_write(uint32_t mr, uint32_t data, uint32_t mr_type,
         * 1. Poll MRSTAT.mr_wr_busy until it is 0 to make sure
         * that there is no outstanding MR transAction.
         */
-       while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) {
-               ;
-       }
+
+       /*
+        * ERR050712:
+        * When performing a software driven MR access, the following sequence
+        * must be done automatically before performing other APB register accesses.
+        * 1. Set MRCTRL0.mr_wr=1
+        * 2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2)
+        * 3. Check for MRSTAT.mr_wr_busy=0 again (for the second time). If not, go to step (2)
+        */
+       mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31));
+
+       do {
+               while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) {
+                       ;
+               }
+
+       } while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1);
 
        /*
         * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank