drm/i915: Display WA #1185 WaDisableDARBFClkGating:cnl, glk

Display is not sending a PMRsp when a PMReq is received
at the same time that all planes are turned off.
State machine in the dcprunit is stuck in the WAIT4DONE
state which means that there is no fill_done.

WA: disable arbiter clock gating, set bit [27] of 0x46530

v2: As Ville pointed out, based on the description the issue
    can happen when disabling the planes, similar to
    WaRsPkgCStateDisplayPMReq:hsw
    Also description of the issue was updated on commit
    message to make it more clear that we need this
    earlier.
v3: Restore comment about possibility to system hang
    to where we are sure about it, without speculation. (Ville).
v4: Remove doubled sob. Actually do v3 changes :/

Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171111000319.5040-1-rodrigo.vivi@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d7e24426120d0f55b6eb0816fe4579aef4abf96f..cfdf4f821ac3ac7b7ea94241941f586a414846ee 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3852,6 +3852,7 @@ enum {
  * GEN9 clock gating regs
  */
 #define GEN9_CLKGATE_DIS_0             _MMIO(0x46530)
+#define   DARBF_GATING_DIS             (1 << 27)
 #define   PWM2_GATING_DIS              (1 << 14)
 #define   PWM1_GATING_DIS              (1 << 13)
 

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ed6a4a8d92734b79d627a25fcecf7eaf1062e51f..23aa7191024ef9e11fc0294fb4483d3f8290976f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15148,6 +15148,23 @@ get_encoder_power_domains(struct drm_i915_private *dev_priv)
        }
 }
 
+static void intel_early_display_was(struct drm_i915_private *dev_priv)
+{
+       /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
+       if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+               I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
+                          DARBF_GATING_DIS);
+
+       if (IS_HASWELL(dev_priv)) {
+               /*
+                * WaRsPkgCStateDisplayPMReq:hsw
+                * System hang if this isn't done before disabling all planes!
+                */
+               I915_WRITE(CHICKEN_PAR1_1,
+                          I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
+       }
+}
+
 /* Scan out the current hw modeset state,
  * and sanitizes it to the current state
  */
@@ -15161,15 +15178,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
        struct intel_encoder *encoder;
        int i;
 
-       if (IS_HASWELL(dev_priv)) {
-               /*
-                * WaRsPkgCStateDisplayPMReq:hsw
-                * System hang if this isn't done before disabling all planes!
-                */
-               I915_WRITE(CHICKEN_PAR1_1,
-                          I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
-       }
-
+       intel_early_display_was(dev_priv);
        intel_modeset_readout_hw_state(dev);
 
        /* HW state is read out, now we need to sanitize this mess. */