Replace CONFIG_MPC832* with proper CONFIG_ARCH_MPC832* Kconfig options.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
config TARGET_MPC8323ERDB
bool "Support MPC8323ERDB"
+ select ARCH_MPC832X
config TARGET_MPC832XEMDS
bool "Support MPC832XEMDS"
+ select ARCH_MPC832X
select BOARD_EARLY_INIT_F
config TARGET_MPC8349EMDS
bool "Support suvd3"
select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMTEGR1"
select ARCH_MPC8309 if SYS_EXTRA_OPTIONS="KMVECT1"
+ select ARCH_MPC832X if SYS_EXTRA_OPTIONS="SUVD3"
imply CMD_CRAMFS
imply FS_CRAMFS
config TARGET_TUXX1
bool "Support tuxx1"
+ select ARCH_MPC832X
imply CMD_CRAMFS
imply FS_CRAMFS
bool
select ARCH_MPC831X
+config ARCH_MPC832X
+ bool
+
source "board/esd/vme8349/Kconfig"
source "board/freescale/mpc8308rdb/Kconfig"
source "board/freescale/mpc8313erdb/Kconfig"
#endif
u32 core_clk;
u32 i2c1_clk;
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
u32 i2c2_clk;
#endif
#if defined(CONFIG_ARCH_MPC8315)
i2c1_clk = tsec2_clk;
#elif defined(CONFIG_MPC8360)
i2c1_clk = csb_clk;
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
i2c1_clk = enc_clk;
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
i2c1_clk = enc_clk;
#elif defined(CONFIG_ARCH_MPC8309)
i2c1_clk = csb_clk;
#endif
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif
#endif
gd->arch.core_clk = core_clk;
gd->arch.i2c1_clk = i2c1_clk;
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
gd->arch.i2c2_clk = i2c2_clk;
#endif
#if !defined(CONFIG_ARCH_MPC8309)
#endif
printf(" I2C1: %-4s MHz\n",
strmhz(buf, gd->arch.i2c1_clk));
-#if !defined(CONFIG_MPC832x)
+#if !defined(CONFIG_ARCH_MPC832X)
printf(" I2C2: %-4s MHz\n",
strmhz(buf, gd->arch.i2c2_clk));
#endif
u8 qe[0x100000]; /* QE block */
} immap_t;
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
/*
* System Clock Setup
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
/*
* High Level Configuration Options
*/
#define CONFIG_QE /* Has QE */
-#define CONFIG_MPC832x /* MPC832x CPU specific */
#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
#define QE_MURAM_SIZE 0xc000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
-#elif defined(CONFIG_MPC832x) || defined(CONFIG_ARCH_MPC8309)
+#elif defined(CONFIG_ARCH_MPC832X) || defined(CONFIG_ARCH_MPC8309)
#define QE_MURAM_SIZE 0x4000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define SICRH_UC2E1OBI 0x00000002
#define SICRH_UC2E2OBI 0x00000001
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
/* SICRL bits - MPC832x specific */
#define SICRL_LDP_LCS_A 0x80000000
#define SICRL_IRQ_CKS 0x20000000
#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
#define HRCWL_CORE_TO_CSB_3X1 0x00060000
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_ARCH_MPC832X)
#define HRCWL_CEVCOD 0x000000C0
#define HRCWL_CEVCOD_SHIFT 6
#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
#define CSCONFIG_ODT_WR_ALL 0x00040000
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_ARCH_MPC832X)
#define CSCONFIG_ODT_RD_CFG 0x00400000
#define CSCONFIG_ODT_WR_CFG 0x00040000
#elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x)
CONFIG_MPC8313ERDB
CONFIG_MPC8315ERDB
CONFIG_MPC832XEMDS
-CONFIG_MPC832x
CONFIG_MPC8349
CONFIG_MPC8349ITX
CONFIG_MPC834x