drm/amdgpu/gmc10: switch to using amdgpu_gmc_get_vbios_allocations

The new helper centralizes the logic in one place.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 187c108f2fde45f9fbccacaa358eaf337f454b7d..f0f50e785dcd1d0793c1affef47bc3544b3b169a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -572,6 +572,28 @@ static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
        }
 }
 
+static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
+{
+       u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
+       unsigned size;
+
+       if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
+               size = AMDGPU_VBIOS_VGA_ALLOCATION;
+       } else {
+               u32 viewport;
+               u32 pitch;
+
+               viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
+               pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
+               size = (REG_GET_FIELD(viewport,
+                                       HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
+                               REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
+                               4);
+       }
+
+       return size;
+}
+
 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
        .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
        .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
@@ -579,7 +601,8 @@ static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
        .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
        .map_mtype = gmc_v10_0_map_mtype,
        .get_vm_pde = gmc_v10_0_get_vm_pde,
-       .get_vm_pte = gmc_v10_0_get_vm_pte
+       .get_vm_pte = gmc_v10_0_get_vm_pte,
+       .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size,
 };
 
 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
@@ -741,36 +764,6 @@ static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
        return amdgpu_gart_table_vram_alloc(adev);
 }
 
-static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
-{
-       u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
-       unsigned size;
-
-       if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
-               size = AMDGPU_VBIOS_VGA_ALLOCATION;
-       } else {
-               u32 viewport;
-               u32 pitch;
-
-               viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
-               pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
-               size = (REG_GET_FIELD(viewport,
-                                       HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
-                               REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
-                               4);
-       }
-       /* return 0 if the pre-OS buffer uses up most of vram */
-       if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) {
-               DRM_ERROR("Warning: pre-OS buffer uses most of vram, \
-                               be aware of gart table overwrite\n");
-               return 0;
-       }
-
-       return size;
-}
-
-
-
 static int gmc_v10_0_sw_init(void *handle)
 {
        int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
@@ -860,7 +853,7 @@ static int gmc_v10_0_sw_init(void *handle)
        if (r)
                return r;
 
-       adev->gmc.stolen_vga_size = gmc_v10_0_get_vbios_fb_size(adev);
+       amdgpu_gmc_get_vbios_allocations(adev);
 
        /* Memory manager */
        r = amdgpu_bo_init(adev);