clk: socfpga: stratix10: use new parent data scheme

Convert, where possible, the stratix10 clock driver to the new parent
data scheme by specifying the parent data for clocks that have multiple
parents.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20200512181647.5071-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c
index 8be4722f606498406ed448a86f222b8ba8b93e08..083b2ec21fdd64968b19ca7c7ec07c8a2db7cdbf 100644 (file)
--- a/drivers/clk/socfpga/clk-gate-s10.c
+++ b/drivers/clk/socfpga/clk-gate-s10.c
@@ -70,7 +70,6 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __io
        struct clk *clk;
        struct socfpga_gate_clk *socfpga_clk;
        struct clk_init_data init;
-       const char * const *parent_names = clks->parent_names;
        const char *parent_name = clks->parent_name;
 
        socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
@@ -108,7 +107,9 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __io
        init.flags = clks->flags;
 
        init.num_parents = clks->num_parents;
-       init.parent_names = parent_names ? parent_names : &parent_name;
+       init.parent_names = parent_name ? &parent_name : NULL;
+       if (init.parent_names == NULL)
+               init.parent_data = clks->parent_data;
        socfpga_clk->hw.hw.init = &init;
 
        clk = clk_register(NULL, &socfpga_clk->hw.hw);

diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c
index dd6d4056e9de1391e976de9d14e8dca22360f378..397b77b89b166eabd43b4a5ec41f098a06fc39a7 100644 (file)
--- a/drivers/clk/socfpga/clk-periph-s10.c
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -81,7 +81,6 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
        struct clk_init_data init;
        const char *name = clks->name;
        const char *parent_name = clks->parent_name;
-       const char * const *parent_names = clks->parent_names;
 
        periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
        if (WARN_ON(!periph_clk))
@@ -94,7 +93,9 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
        init.flags = clks->flags;
 
        init.num_parents = clks->num_parents;
-       init.parent_names = parent_names ? parent_names : &parent_name;
+       init.parent_names = parent_name ? &parent_name : NULL;
+       if (init.parent_names == NULL)
+               init.parent_data = clks->parent_data;
 
        periph_clk->hw.hw.init = &init;
 
@@ -114,7 +115,6 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks
        struct clk_init_data init;
        const char *name = clks->name;
        const char *parent_name = clks->parent_name;
-       const char * const *parent_names = clks->parent_names;
 
        periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
        if (WARN_ON(!periph_clk))
@@ -137,7 +137,9 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks
        init.flags = clks->flags;
 
        init.num_parents = clks->num_parents;
-       init.parent_names = parent_names ? parent_names : &parent_name;
+       init.parent_names = parent_name ? &parent_name : NULL;
+       if (init.parent_names == NULL)
+               init.parent_data = clks->parent_data;
 
        periph_clk->hw.hw.init = &init;
 

diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index a301bb22f36c0bc13388aea6af8b9f4c5a35712a..bcd3f14e9145f1ade97537a5753042be147c77cd 100644 (file)
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -117,7 +117,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
        struct socfpga_pll *pll_clk;
        struct clk_init_data init;
        const char *name = clks->name;
-       const char * const *parent_names = clks->parent_names;
 
        pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
        if (WARN_ON(!pll_clk))
@@ -134,7 +133,8 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
        init.flags = clks->flags;
 
        init.num_parents = clks->num_parents;
-       init.parent_names = parent_names;
+       init.parent_names = NULL;
+       init.parent_data = clks->parent_data;
        pll_clk->hw.hw.init = &init;
 
        pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;

diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index dea7c6c7d2698845b4ff2348035181fda19cb952..c1dfc9b34e4e92444273ad2d760b07285036d624 100644 (file)
--- a/drivers/clk/socfpga/clk-s10.c
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -12,35 +12,137 @@
 
 #include "stratix10-clk.h"
 
-static const char * const pll_mux[] = { "osc1", "cb-intosc-hs-div2-clk",
-                                       "f2s-free-clk",};
-static const char * const cntr_mux[] = { "main_pll", "periph_pll",
-                                        "osc1", "cb-intosc-hs-div2-clk",
-                                        "f2s-free-clk"};
-static const char * const boot_mux[] = { "osc1", "cb-intosc-hs-div2-clk",};
-
-static const char * const noc_free_mux[] = {"main_noc_base_clk",
-                                           "peri_noc_base_clk",
-                                           "osc1", "cb-intosc-hs-div2-clk",
-                                           "f2s-free-clk"};
-
-static const char * const emaca_free_mux[] = {"peri_emaca_clk", "boot_clk"};
-static const char * const emacb_free_mux[] = {"peri_emacb_clk", "boot_clk"};
-static const char * const emac_ptp_free_mux[] = {"peri_emac_ptp_clk", "boot_clk"};
-static const char * const gpio_db_free_mux[] = {"peri_gpio_db_clk", "boot_clk"};
-static const char * const sdmmc_free_mux[] = {"main_sdmmc_clk", "boot_clk"};
-static const char * const s2f_usr1_free_mux[] = {"peri_s2f_usr1_clk", "boot_clk"};
-static const char * const psi_ref_free_mux[] = {"peri_psi_ref_clk", "boot_clk"};
-static const char * const mpu_mux[] = { "mpu_free_clk", "boot_clk",};
-
-static const char * const s2f_usr0_mux[] = {"f2s-free-clk", "boot_clk"};
-static const char * const emac_mux[] = {"emaca_free_clk", "emacb_free_clk"};
-static const char * const noc_mux[] = {"noc_free_clk", "boot_clk"};
-
-static const char * const mpu_free_mux[] = {"main_mpu_base_clk",
-                                           "peri_mpu_base_clk",
-                                           "osc1", "cb-intosc-hs-div2-clk",
-                                           "f2s-free-clk"};
+static const struct clk_parent_data pll_mux[] = {
+       { .fw_name = "osc1",
+         .name = "osc1" },
+       { .fw_name = "cb-intosc-hs-div2-clk",
+         .name = "cb-intosc-hs-div2-clk" },
+       { .fw_name = "f2s-free-clk",
+         .name = "f2s-free-clk" },
+};
+
+static const struct clk_parent_data cntr_mux[] = {
+       { .fw_name =  "main_pll",
+         .name = "main_pll", },
+       { .fw_name = "periph_pll",
+         .name = "periph_pll", },
+       { .fw_name = "osc1",
+         .name = "osc1", },
+       { .fw_name = "cb-intosc-hs-div2-clk",
+         .name = "cb-intosc-hs-div2-clk", },
+       { .fw_name = "f2s-free-clk",
+         .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data boot_mux[] = {
+       { .fw_name = "osc1",
+         .name = "osc1" },
+       { .fw_name = "cb-intosc-hs-div2-clk",
+         .name = "cb-intosc-hs-div2-clk" },
+};
+
+static const struct clk_parent_data noc_free_mux[] = {
+       { .fw_name = "main_noc_base_clk",
+         .name = "main_noc_base_clk", },
+       { .fw_name = "peri_noc_base_clk",
+         .name = "peri_noc_base_clk", },
+       { .fw_name = "osc1",
+         .name = "osc1", },
+       { .fw_name = "cb-intosc-hs-div2-clk",
+         .name = "cb-intosc-hs-div2-clk", },
+       { .fw_name = "f2s-free-clk",
+         .name = "f2s-free-clk", },
+};
+
+static const struct clk_parent_data emaca_free_mux[] = {
+       { .fw_name = "peri_emaca_clk",
+         .name = "peri_emaca_clk", },
+       { .fw_name = "boot_clk",
+         .name = "boot_clk", },
+};
+
+static const struct clk_parent_data emacb_free_mux[] = {
+       { .fw_name = "peri_emacb_clk",
+         .name = "peri_emacb_clk", },
+       { .fw_name = "boot_clk",
+         .name = "boot_clk", },
+};
+
+static const struct clk_parent_data emac_ptp_free_mux[] = {
+       { .fw_name = "peri_emac_ptp_clk",
+         .name = "peri_emac_ptp_clk", },
+       { .fw_name = "boot_clk",
+         .name = "boot_clk", },
+};
+
+static const struct clk_parent_data gpio_db_free_mux[] = {
+       { .fw_name = "peri_gpio_db_clk",
+         .name = "peri_gpio_db_clk", },
+       { .fw_name = "boot_clk",
+         .name = "boot_clk", },
+};
+
+static const struct clk_parent_data sdmmc_free_mux[] = {
+       { .fw_name = "main_sdmmc_clk",
+         .name = "main_sdmmc_clk", },
+       { .fw_name = "boot_clk",
+         .name = "boot_clk", },
+};
+
+static const struct clk_parent_data s2f_usr1_free_mux[] = {
+       { .fw_name = "peri_s2f_usr1_clk",
+         .name = "peri_s2f_usr1_clk", },
+       { .fw_name = "boot_clk",
+         .name = "boot_clk", },
+};
+
+static const struct clk_parent_data psi_ref_free_mux[] = {
+       { .fw_name = "peri_psi_ref_clk",
+         .name = "peri_psi_ref_clk", },
+       { .fw_name = "boot_clk",
+         .name = "boot_clk", },
+};
+
+static const struct clk_parent_data mpu_mux[] = {
+       { .fw_name = "mpu_free_clk",
+         .name = "mpu_free_clk", },
+       { .fw_name = "boot_clk",
+         .name = "boot_clk", },
+};
+
+static const struct clk_parent_data s2f_usr0_mux[] = {
+       { .fw_name = "f2s-free-clk",
+         .name = "f2s-free-clk", },
+       { .fw_name = "boot_clk",
+         .name = "boot_clk", },
+};
+
+static const struct clk_parent_data emac_mux[] = {
+       { .fw_name = "emaca_free_clk",
+         .name = "emaca_free_clk", },
+       { .fw_name = "emacb_free_clk",
+         .name = "emacb_free_clk", },
+};
+
+static const struct clk_parent_data noc_mux[] = {
+       { .fw_name = "noc_free_clk",
+         .name = "noc_free_clk", },
+       { .fw_name = "boot_clk",
+         .name = "boot_clk", },
+};
+
+static const struct clk_parent_data mpu_free_mux[] = {
+       { .fw_name = "main_mpu_base_clk",
+         .name = "main_mpu_base_clk", },
+       { .fw_name = "peri_mpu_base_clk",
+         .name = "peri_mpu_base_clk", },
+       { .fw_name = "osc1",
+         .name = "osc1", },
+       { .fw_name = "cb-intosc-hs-div2-clk",
+         .name = "cb-intosc-hs-div2-clk", },
+       { .fw_name = "f2s-free-clk",
+         .name = "f2s-free-clk", },
+};
 
 /* clocks in AO (always on) controller */
 static const struct stratix10_pll_clock s10_pll_clks[] = {

diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h
index fcabef42249c1e3aa9b4be9299ccef2136465537..ffbd1fb2c8efb46cd2b7cc42291db6faa1fa49f4 100644 (file)
--- a/drivers/clk/socfpga/stratix10-clk.h
+++ b/drivers/clk/socfpga/stratix10-clk.h
@@ -14,7 +14,7 @@ struct stratix10_clock_data {
 struct stratix10_pll_clock {
        unsigned int            id;
        const char              *name;
-       const char              *const *parent_names;
+       const struct clk_parent_data    *parent_data;
        u8                      num_parents;
        unsigned long           flags;
        unsigned long           offset;
@@ -24,7 +24,7 @@ struct stratix10_perip_c_clock {
        unsigned int            id;
        const char              *name;
        const char              *parent_name;
-       const char              *const *parent_names;
+       const struct clk_parent_data    *parent_data;
        u8                      num_parents;
        unsigned long           flags;
        unsigned long           offset;
@@ -34,7 +34,7 @@ struct stratix10_perip_cnt_clock {
        unsigned int            id;
        const char              *name;
        const char              *parent_name;
-       const char              *const *parent_names;
+       const struct clk_parent_data    *parent_data;
        u8                      num_parents;
        unsigned long           flags;
        unsigned long           offset;
@@ -47,7 +47,7 @@ struct stratix10_gate_clock {
        unsigned int            id;
        const char              *name;
        const char              *parent_name;
-       const char              *const *parent_names;
+       const struct clk_parent_data    *parent_data;
        u8                      num_parents;
        unsigned long           flags;
        unsigned long           gate_reg;