]> git.baikalelectronics.ru Git - uboot.git/commitdiff
clk: imx8mp: fix root clock names for ecspi
authorAndrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Fri, 3 Jun 2022 15:15:21 +0000 (17:15 +0200)
committerStefano Babic <sbabic@denx.de>
Tue, 14 Jun 2022 19:25:26 +0000 (21:25 +0200)
Root clock name contained underscore, which does not match to the actual
clock name.

Correct the name to match what is present in the FDT.

Fixes: 92ac4727079b ("clk: imx8mp: Add ECSPI clocks")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
drivers/clk/imx/clk-imx8mp.c

index ac727b7e404b82a9e95c2f5096da1ce08cff3d9f..cbed86a6843f74e6ab9ccb76ca9f27a3fe0a653c 100644 (file)
@@ -122,15 +122,15 @@ static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_p
                                        "sys_pll2_100m", "sys_pll1_800m",
                                        "sys_pll2_500m", "clk_ext4", "audio_pll2_out" };
 
-static const char *imx8mp_ecspi1_sels[] = {"clock-osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char *imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
                                                  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
                                                  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char *imx8mp_ecspi2_sels[] = {"clock-osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char *imx8mp_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
                                                  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
                                                  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char *imx8mp_ecspi3_sels[] = {"clock-osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char *imx8mp_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
                                                  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
                                                  "sys_pll2_250m", "audio_pll2_out", };