drm/i915/icl: Add register definitions for Multi Segmented gamma

Add macros to define multi segmented gamma registers

V2: Addressed Ville's comments:
    	Add gen-lable before bit definition
    Addressed Jani's comment
	- Use REG_GENMASK() and REG_BIT()
V3: Addressed Ville's comments:
    - Put comments at the end of line.
    - Change the comment at start of ICL multisegmented gamma registers.
    Added Ville's r-b

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1560321900-18318-3-git-send-email-uma.shankar@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index daee496aade634a5127e0209ad79b4f2b8cc1336..1d0279d1fb87c87ba2e4c8dc54388e2c1f0e881e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7204,7 +7204,8 @@ enum {
 #define  GAMMA_MODE_MODE_8BIT  (0 << 0)
 #define  GAMMA_MODE_MODE_10BIT (1 << 0)
 #define  GAMMA_MODE_MODE_12BIT (2 << 0)
-#define  GAMMA_MODE_MODE_SPLIT (3 << 0)
+#define  GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
+#define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
 
 /* DMC/CSR */
 #define CSR_PROGRAM(i)         _MMIO(0x80000 + (i) * 4)
@@ -10177,6 +10178,22 @@ enum skl_power_gate {
 #define PRE_CSC_GAMC_INDEX(pipe)       _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
 #define PRE_CSC_GAMC_DATA(pipe)                _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
 
+/* ICL Multi segmented gamma */
+#define _PAL_PREC_MULTI_SEG_INDEX_A    0x4A408
+#define _PAL_PREC_MULTI_SEG_INDEX_B    0x4AC08
+#define  PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT         REG_BIT(15)
+#define  PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK       REG_GENMASK(4, 0)
+
+#define _PAL_PREC_MULTI_SEG_DATA_A     0x4A40C
+#define _PAL_PREC_MULTI_SEG_DATA_B     0x4AC0C
+
+#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
+                                       _PAL_PREC_MULTI_SEG_INDEX_A, \
+                                       _PAL_PREC_MULTI_SEG_INDEX_B)
+#define PREC_PAL_MULTI_SEG_DATA(pipe)  _MMIO_PIPE(pipe, \
+                                       _PAL_PREC_MULTI_SEG_DATA_A, \
+                                       _PAL_PREC_MULTI_SEG_DATA_B)
+
 /* pipe CSC & degamma/gamma LUTs on CHV */
 #define _CGM_PIPE_A_CSC_COEFF01        (VLV_DISPLAY_BASE + 0x67900)
 #define _CGM_PIPE_A_CSC_COEFF23        (VLV_DISPLAY_BASE + 0x67904)