feat(imx8mq): add the dram retention support for imx8mq

Add the dram retention support for i.MX8MQ. As there is
no enough ocram space available before entering TF-A,
so the timing info need to be copied from dram into ocram.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id8264c342fd62e297b1969cba5ed505450c78a25

diff --git a/plat/imx/imx8m/ddr/dram.c b/plat/imx/imx8m/ddr/dram.c
index 4a9f4eef8d291b9a9dae4a7b6b053e56d6d68756..f5f9df7a48f672573631daeabc162d34d29466f0 100644 (file)
--- a/plat/imx/imx8m/ddr/dram.c
+++ b/plat/imx/imx8m/ddr/dram.c
@@ -20,6 +20,11 @@ struct dram_info dram_info;
 /* lock used for DDR DVFS */
 spinlock_t dfs_lock;
 
+#if defined(PLAT_imx8mq)
+/* ocram used to dram timing */
+static uint8_t dram_timing_saved[13 * 1024] __aligned(8);
+#endif
+
 static volatile uint32_t wfe_done;
 static volatile bool wait_ddrc_hwffc_done = true;
 static unsigned int dev_fsp = 0x1;
@@ -30,6 +35,31 @@ static uint32_t fsp_init_reg[3][4] = {
        { DDRC_FREQ2_INIT3(0), DDRC_FREQ2_INIT4(0), DDRC_FREQ2_INIT6(0), DDRC_FREQ2_INIT7(0) },
 };
 
+#if defined(PLAT_imx8mq)
+static inline struct dram_cfg_param *get_cfg_ptr(void *ptr,
+               void *old_base, void *new_base)
+{
+       uintptr_t offset = (uintptr_t)ptr & ~((uintptr_t)old_base);
+
+       return (struct dram_cfg_param *)(offset + new_base);
+}
+
+/* copy the dram timing info from DRAM to OCRAM */
+void imx8mq_dram_timing_copy(struct dram_timing_info *from)
+{
+       struct dram_timing_info *info = (struct dram_timing_info *)dram_timing_saved;
+
+       /* copy the whole 13KB content used for dram timing info */
+       memcpy(dram_timing_saved, from, sizeof(dram_timing_saved));
+
+       /* correct the header after copied into ocram */
+       info->ddrc_cfg = get_cfg_ptr(info->ddrc_cfg, from, dram_timing_saved);
+       info->ddrphy_cfg = get_cfg_ptr(info->ddrphy_cfg, from, dram_timing_saved);
+       info->ddrphy_trained_csr = get_cfg_ptr(info->ddrphy_trained_csr, from, dram_timing_saved);
+       info->ddrphy_pie = get_cfg_ptr(info->ddrphy_pie, from, dram_timing_saved);
+}
+#endif
+
 #if defined(PLAT_imx8mp)
 static uint32_t lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
 {
@@ -200,6 +230,10 @@ void dram_info_init(unsigned long dram_timing_base)
        dram_info.boot_fsp = current_fsp;
        dram_info.current_fsp = current_fsp;
 
+#if defined(PLAT_imx8mq)
+       imx8mq_dram_timing_copy((struct dram_timing_info *)dram_timing_base);
+       dram_timing_base = (unsigned long) dram_timing_saved;
+#endif
        get_mr_values(dram_info.mr_table);
 
        dram_info.timing_info = (struct dram_timing_info *)dram_timing_base;

diff --git a/plat/imx/imx8m/ddr/dram_retention.c b/plat/imx/imx8m/ddr/dram_retention.c
index 7572e86927b700dd5d2433480fc8d4413e254448..983f6e2dac2901bf977e998fa7b359ee7d003a76 100644 (file)
--- a/plat/imx/imx8m/ddr/dram_retention.c
+++ b/plat/imx/imx8m/ddr/dram_retention.c
@@ -23,8 +23,6 @@
 #define CCM_CCGR(n)            (CCM_CCGR_OFFSET + 0x10 * (n))
 #define CCM_TARGET_ROOT(n)     (CCM_TARGET_ROOT_OFFSET + 0x80 * (n))
 
-#define DRAM_PLL_CTRL          (IMX_ANAMIX_BASE + 0x50)
-
 #define DBGCAM_EMPTY           0x36000000
 
 static void rank_setting_update(void)

diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
index 264d920f74334d478e4bf3e4744d4368ec151cd6..661f8e2913f4cb128d368a6dba692825a3d0ed47 100644 (file)
--- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
@@ -21,6 +21,7 @@
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
 
+#include <dram.h>
 #include <gpc.h>
 #include <imx_aipstz.h>
 #include <imx_uart.h>
@@ -34,6 +35,8 @@ static const mmap_region_t imx_mmap[] = {
        MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */
        MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
        MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */
+       MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX map */
+       MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
        {0},
 };
 
@@ -212,6 +215,8 @@ void bl31_platform_setup(void)
 
        /* gpc init */
        imx_gpc_init();
+
+       dram_info_init(SAVED_DRAM_TIMING_BASE);
 }
 
 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)

diff --git a/plat/imx/imx8m/imx8mq/imx8mq_psci.c b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
index 01582afe490ceea0b5f2f7455562693caf0b42de..6209fea892cd0597433d3ea885d942ed3e7b5574 100644 (file)
--- a/plat/imx/imx8m/imx8mq/imx8mq_psci.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,6 +12,7 @@
 #include <lib/mmio.h>
 #include <lib/psci/psci.h>
 
+#include <dram.h>
 #include <gpc.h>
 #include <imx8m_psci.h>
 #include <plat_imx8.h>
@@ -63,6 +64,7 @@ void imx_domain_suspend(const psci_power_state_t *target_state)
 
        if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
                imx_set_sys_lpm(core_id, true);
+               dram_enter_retention();
        }
 }
 
@@ -73,6 +75,7 @@ void imx_domain_suspend_finish(const psci_power_state_t *target_state)
 
        /* check the system level status */
        if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
+               dram_exit_retention();
                imx_set_sys_lpm(core_id, false);
                imx_clear_rbc_count();
        }

diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h
index bb570748f5730b8f014d705546a6084ae9e0402f..2526a02db0010fb6ed65cde26446671d16dd5978 100644 (file)
--- a/plat/imx/imx8m/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mq/include/platform_def.h
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <lib/utils_def.h>
 #include <plat/common/common_def.h>
 
 #define PLATFORM_LINKER_FORMAT         "elf64-littleaarch64"
@@ -82,6 +83,9 @@
 #define IMX_DDRC_BASE                  U(0x3d400000)
 #define IMX_DDRPHY_BASE                        U(0x3c000000)
 #define IMX_DDR_IPS_BASE               U(0x3d000000)
+#define IMX_DDR_IPS_SIZE               U(0x1800000)
+#define IMX_DRAM_BASE                  U(0x40000000)
+#define IMX_DRAM_SIZE                  U(0xc0000000)
 
 #define IMX_ROM_BASE                   U(0x00000000)
 #define IMX_ROM_SIZE                   U(0x20000)
@@ -119,6 +123,12 @@
 #define SNVS_LPCR_DP_EN                        BIT(5)
 #define SNVS_LPCR_TOP                  BIT(6)
 
+#define SAVED_DRAM_TIMING_BASE         U(0x40000000)
+
+#define HW_DRAM_PLL_CFG0               (IMX_ANAMIX_BASE + 0x60)
+#define HW_DRAM_PLL_CFG1               (IMX_ANAMIX_BASE + 0x64)
+#define HW_DRAM_PLL_CFG2               (IMX_ANAMIX_BASE + 0x68)
+#define DRAM_PLL_CTRL                  HW_DRAM_PLL_CFG0
 
 #define IOMUXC_GPR10                   U(0x28)
 #define GPR_TZASC_EN                   BIT(0)

diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk
index 901a974a591e7be6c4b0f0cc8c8d5606dec3b6af..284ccee9d6733fd7b6bf7aa30694db2d0a766d69 100644 (file)
--- a/plat/imx/imx8m/imx8mq/platform.mk
+++ b/plat/imx/imx8m/imx8mq/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -14,6 +14,12 @@ PLAT_INCLUDES                :=      -Iplat/imx/common/include               \
 # Include GICv3 driver files
 include drivers/arm/gic/v3/gicv3.mk
 
+IMX_DRAM_SOURCES       :=      plat/imx/imx8m/ddr/dram.c               \
+                               plat/imx/imx8m/ddr/clock.c              \
+                               plat/imx/imx8m/ddr/dram_retention.c     \
+                               plat/imx/imx8m/ddr/ddr4_dvfs.c          \
+                               plat/imx/imx8m/ddr/lpddr4_dvfs.c
+
 IMX_GIC_SOURCES                :=      ${GICV3_SOURCES}                        \
                                plat/common/plat_gicv3.c                \
                                plat/common/plat_psci_common.c          \
@@ -36,6 +42,7 @@ BL31_SOURCES          +=      plat/imx/common/imx8_helpers.S                  \
                                drivers/delay_timer/delay_timer.c               \
                                drivers/delay_timer/generic_delay_timer.c       \
                                ${XLAT_TABLES_LIB_SRCS}                         \
+                               ${IMX_DRAM_SOURCES}                             \
                                ${IMX_GIC_SOURCES}
 
 ENABLE_PIE             :=      1