arm: socfpga: misc_s10: Fix EMAC register address calculation

Fix EMAC register address calculation, address need to multiply
with sizeof(u32) or 4.

This fixes write to invalid address.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index ccff78a2307f833996d2eb0777ed1f141d12f38e..670bfa1a31fdd5d414b36de87564491fd52457f1 100644 (file)
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -68,7 +68,7 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
                return -EINVAL;
 
        clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 +
-                       gmac_index,
+                       (gmac_index * sizeof(u32)),
                        SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
 
        return 0;