drm/i915/ehl: Restrict w/a 1607087056 for EHL/JSL

This w/a is fixed in B0 stepping and needs to be restricted for
A0 stepping only.
Bspec: 33451

Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200512180050.6785-1-swathi.dhanavanthri@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index aa90e6b7a118058fc8950e0ad108ecfda3a14c85..90a2b9e399b094b50300f5c8e753ee2ad4bf94cc 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -917,10 +917,13 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
                    GAMT_CHKN_BIT_REG,
                    GAMT_CHKN_DISABLE_L3_COH_PIPE);
 
-       /* Wa_1607087056:icl */
-       wa_write_or(wal,
-                   SLICE_UNIT_LEVEL_CLKGATE,
-                   L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
+       /* Wa_1607087056:icl,ehl,jsl */
+       if (IS_ICELAKE(i915) ||
+           IS_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) {
+               wa_write_or(wal,
+                           SLICE_UNIT_LEVEL_CLKGATE,
+                           L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
+       }
 }
 
 static void

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7fad6f2d80faa090e5f38dc4e9c341a85a9e4a02..5ca932c1fe371bba8cc8654ba3b49495de42a168 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1514,6 +1514,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_ICL_REVID(p, since, until) \
        (IS_ICELAKE(p) && IS_REVID(p, since, until))
 
+#define EHL_REVID_A0            0x0
+
+#define IS_EHL_REVID(p, since, until) \
+       (IS_ELKHARTLAKE(p) && IS_REVID(p, since, until))
+
 #define TGL_REVID_A0           0x0
 #define TGL_REVID_B0           0x1
 #define TGL_REVID_C0           0x2