pata_hpt3x2n: fix writing to wrong register in hpt3x2n_bmdma_stop()

The driver's bmdma_stop() method writes to the wrong PCI config register
(0x52 intead of 0x54) when trying to clear the state machine on secondary
channel -- "luckily", the write falls on a read-only part of the primary
channel MISC. control 3 register, so no collateral damage is done...

Alan Cox fixed the HPT37x driver in commit 6719ccbb7e75 ("[PATCH] hpt37x:
Two important bug fixes") but forgot to check the HPT3x2N driver which has
the same bug. :-/

Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>

diff --git a/drivers/ata/pata_hpt3x2n.c b/drivers/ata/pata_hpt3x2n.c
index cbe57aba39bcab2cad9d52e1e580140aad9287b5..8772cbb29ee13b676c4daf95f17114233de9a5b9 100644 (file)
--- a/drivers/ata/pata_hpt3x2n.c
+++ b/drivers/ata/pata_hpt3x2n.c
@@ -24,7 +24,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME       "pata_hpt3x2n"
-#define DRV_VERSION    "0.3.16"
+#define DRV_VERSION    "0.3.17"
 
 enum {
        HPT_PCI_FAST    =       (1 << 31),
@@ -251,7 +251,7 @@ static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
 {
        struct ata_port *ap = qc->ap;
        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
-       int mscreg = 0x50 + 2 * ap->port_no;
+       int mscreg = 0x50 + 4 * ap->port_no;
        u8 bwsr_stat, msc_stat;
 
        pci_read_config_byte(pdev, 0x6A, &bwsr_stat);